arm64: tegra: Add missing DFLL reset on Tegra210

BugLink: https://bugs.launchpad.net/bugs/1981864
commit 0017f2c856e21bb900be88469e15dac4f41f4065 upstream.

Commit 4782c0a5dd88 ("clk: tegra: Don't deassert reset on enabling
clocks") removed deassertion of reset lines when enabling peripheral
clocks. This breaks the initialization of the DFLL driver which relied
on this behaviour.

In order to be able to fix this, add the corresponding reset to the DT.
Tested on Google Pixel C.

Cc: stable@vger.kernel.org
Fixes: 4782c0a5dd88 ("clk: tegra: Don't deassert reset on enabling clocks")
Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Kamal Mostafa <kamal@canonical.com>
Signed-off-by: Stefan Bader <stefan.bader@canonical.com>

diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 26b3f98a211c2f1a39bee85b6c7fbb13c9980574..f88dc820389b2cff42a9858d0a3a6ed249f1a499 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -1355,8 +1355,9 @@
                         <&tegra_car TEGRA210_CLK_DFLL_REF>,
                         <&tegra_car TEGRA210_CLK_I2C5>;
                clock-names = "soc", "ref", "i2c";
-               resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>;
-               reset-names = "dvco";
+               resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>,
+                        <&tegra_car 155>;
+               reset-names = "dvco", "dfll";
                #clock-cells = <0>;
                clock-output-names = "dfllCPU_out";
                status = "disabled";