net: hns3: refactor function hclge_parse_capability()

The function hclge_parse_capability() uses too many if statement, and
it may add more in the future. To improve code readability, maintainability
and simplicity, refactor this function by using a bit mapping array of IMP
capabilities and driver capabilities.

Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
index 444c46241afc7afc557d0f6a5d83a25845b5ad46..474c6d1664e764800060a57e44d8e25a35e1714e 100644 (file)
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
@@ -362,41 +362,34 @@ static void hclge_set_default_capability(struct hclge_dev *hdev)
        }
 }
 
+const struct hclge_caps_bit_map hclge_cmd_caps_bit_map0[] = {
+       {HCLGE_CAP_UDP_GSO_B, HNAE3_DEV_SUPPORT_UDP_GSO_B},
+       {HCLGE_CAP_PTP_B, HNAE3_DEV_SUPPORT_PTP_B},
+       {HCLGE_CAP_INT_QL_B, HNAE3_DEV_SUPPORT_INT_QL_B},
+       {HCLGE_CAP_TQP_TXRX_INDEP_B, HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B},
+       {HCLGE_CAP_HW_TX_CSUM_B, HNAE3_DEV_SUPPORT_HW_TX_CSUM_B},
+       {HCLGE_CAP_UDP_TUNNEL_CSUM_B, HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B},
+       {HCLGE_CAP_FD_FORWARD_TC_B, HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B},
+       {HCLGE_CAP_FEC_B, HNAE3_DEV_SUPPORT_FEC_B},
+       {HCLGE_CAP_PAUSE_B, HNAE3_DEV_SUPPORT_PAUSE_B},
+       {HCLGE_CAP_PHY_IMP_B, HNAE3_DEV_SUPPORT_PHY_IMP_B},
+       {HCLGE_CAP_RAS_IMP_B, HNAE3_DEV_SUPPORT_RAS_IMP_B},
+       {HCLGE_CAP_RXD_ADV_LAYOUT_B, HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B},
+       {HCLGE_CAP_PORT_VLAN_BYPASS_B, HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B},
+       {HCLGE_CAP_PORT_VLAN_BYPASS_B, HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B},
+};
+
 static void hclge_parse_capability(struct hclge_dev *hdev,
                                   struct hclge_query_version_cmd *cmd)
 {
        struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
-       u32 caps;
+       u32 caps, i;
 
        caps = __le32_to_cpu(cmd->caps[0]);
-       if (hnae3_get_bit(caps, HCLGE_CAP_UDP_GSO_B))
-               set_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps);
-       if (hnae3_get_bit(caps, HCLGE_CAP_PTP_B))
-               set_bit(HNAE3_DEV_SUPPORT_PTP_B, ae_dev->caps);
-       if (hnae3_get_bit(caps, HCLGE_CAP_INT_QL_B))
-               set_bit(HNAE3_DEV_SUPPORT_INT_QL_B, ae_dev->caps);
-       if (hnae3_get_bit(caps, HCLGE_CAP_TQP_TXRX_INDEP_B))
-               set_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, ae_dev->caps);
-       if (hnae3_get_bit(caps, HCLGE_CAP_HW_TX_CSUM_B))
-               set_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps);
-       if (hnae3_get_bit(caps, HCLGE_CAP_UDP_TUNNEL_CSUM_B))
-               set_bit(HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, ae_dev->caps);
-       if (hnae3_get_bit(caps, HCLGE_CAP_FD_FORWARD_TC_B))
-               set_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps);
-       if (hnae3_get_bit(caps, HCLGE_CAP_FEC_B))
-               set_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps);
-       if (hnae3_get_bit(caps, HCLGE_CAP_PAUSE_B))
-               set_bit(HNAE3_DEV_SUPPORT_PAUSE_B, ae_dev->caps);
-       if (hnae3_get_bit(caps, HCLGE_CAP_PHY_IMP_B))
-               set_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, ae_dev->caps);
-       if (hnae3_get_bit(caps, HCLGE_CAP_RAS_IMP_B))
-               set_bit(HNAE3_DEV_SUPPORT_RAS_IMP_B, ae_dev->caps);
-       if (hnae3_get_bit(caps, HCLGE_CAP_RXD_ADV_LAYOUT_B))
-               set_bit(HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, ae_dev->caps);
-       if (hnae3_get_bit(caps, HCLGE_CAP_PORT_VLAN_BYPASS_B)) {
-               set_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, ae_dev->caps);
-               set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps);
-       }
+       for (i = 0; i < ARRAY_SIZE(hclge_cmd_caps_bit_map0); i++)
+               if (hnae3_get_bit(caps, hclge_cmd_caps_bit_map0[i].imp_bit))
+                       set_bit(hclge_cmd_caps_bit_map0[i].local_bit,
+                               ae_dev->caps);
 }
 
 static __le32 hclge_build_api_caps(void)

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
index afca9ee9ca4f2bbc5e1c5f323e807de656547391..0583e88d31d37ac9300f01336800ad3c21780dc4 100644 (file)
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
@@ -1234,6 +1234,12 @@ struct hclge_phy_reg_cmd {
        u8 rsv1[18];
 };
 
+/* capabilities bits map between imp firmware and local driver */
+struct hclge_caps_bit_map {
+       u16 imp_bit;
+       u16 local_bit;
+};
+
 int hclge_cmd_init(struct hclge_dev *hdev);
 static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value)
 {