Revert "parisc: Drop LDCW barrier in CAS code when running UP"

BugLink: https://bugs.launchpad.net/bugs/1892417
commit 462fb756c7de1ffe5bc6099149136031c2d9c02a upstream.

This reverts commit e6eb5fe9123f05dcbf339ae5c0b6d32fcc0685d5.
We need to optimize it differently. A follow up patch will correct it.

Signed-off-by: Helge Deller <deller@gmx.de>
Cc: <stable@vger.kernel.org> # v5.2+
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Kamal Mostafa <kamal@canonical.com>
Signed-off-by: Kelsey Skunberg <kelsey.skunberg@canonical.com>

diff --git a/arch/parisc/kernel/syscall.S b/arch/parisc/kernel/syscall.S
index 97ac707c6bfff0248e8814b1e6207782e7e61236..e54d5e4d3489f39eb2cd84eafa6d4d7090dd1d3a 100644 (file)
--- a/arch/parisc/kernel/syscall.S
+++ b/arch/parisc/kernel/syscall.S
@@ -641,8 +641,7 @@ cas_action:
 2:     stw     %r24, 0(%r26)
        /* Free lock */
 #ifdef CONFIG_SMP
-98:    LDCW    0(%sr2,%r20), %r1                       /* Barrier */
-99:    ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
+       LDCW    0(%sr2,%r20), %r1                       /* Barrier */
 #endif
        stw     %r20, 0(%sr2,%r20)
 #if ENABLE_LWS_DEBUG
@@ -659,8 +658,7 @@ cas_action:
        /* Error occurred on load or store */
        /* Free lock */
 #ifdef CONFIG_SMP
-98:    LDCW    0(%sr2,%r20), %r1                       /* Barrier */
-99:    ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
+       LDCW    0(%sr2,%r20), %r1                       /* Barrier */
 #endif
        stw     %r20, 0(%sr2,%r20)
 #if ENABLE_LWS_DEBUG
@@ -864,8 +862,7 @@ cas2_action:
 cas2_end:
        /* Free lock */
 #ifdef CONFIG_SMP
-98:    LDCW    0(%sr2,%r20), %r1                       /* Barrier */
-99:    ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
+       LDCW    0(%sr2,%r20), %r1                       /* Barrier */
 #endif
        stw     %r20, 0(%sr2,%r20)
        /* Enable interrupts */
@@ -878,8 +875,7 @@ cas2_end:
        /* Error occurred on load or store */
        /* Free lock */
 #ifdef CONFIG_SMP
-98:    LDCW    0(%sr2,%r20), %r1                       /* Barrier */
-99:    ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
+       LDCW    0(%sr2,%r20), %r1                       /* Barrier */
 #endif
        stw     %r20, 0(%sr2,%r20)
        ssm     PSW_SM_I, %r0