#endif
qemu_irq *cpu_irqs[MAX_CPUS];
const uint32_t *intbit_to_level;
- uint32_t cputimer_bit;
+ uint32_t cputimer_lbit, cputimer_mbit;
uint32_t pil_out[MAX_CPUS];
} SLAVIO_INTCTLState;
if (pending & (1 << j))
pil_pending |= 1 << s->intbit_to_level[j];
}
- pil_pending |= s->intreg_pending[i] & CPU_HARDIRQ_MASK;
}
pil_pending |= (s->intreg_pending[i] & CPU_SOFTIRQ_MASK) >> 16;
DPRINTF("Set cpu %d local timer level %d\n", cpu, level);
- if (level)
- s->intreg_pending[cpu] |= s->cputimer_bit;
- else
- s->intreg_pending[cpu] &= ~s->cputimer_bit;
+ if (level) {
+ s->intregm_pending |= s->cputimer_mbit;
+ s->intreg_pending[cpu] |= s->cputimer_lbit;
+ } else {
+ s->intregm_pending &= ~s->cputimer_mbit;
+ s->intreg_pending[cpu] &= ~s->cputimer_lbit;
+ }
slavio_check_interrupts(s);
}
*irq = qemu_allocate_irqs(slavio_set_irq, s, 32);
*cpu_irq = qemu_allocate_irqs(slavio_set_timer_irq_cpu, s, MAX_CPUS);
- s->cputimer_bit = 1 << cputimer;
+ s->cputimer_mbit = 1 << cputimer;
+ s->cputimer_lbit = 1 << intbit_to_level[cputimer];
slavio_intctl_reset(s);
return s;
}
target_phys_addr_t sun4c_intctl_base, sun4c_counter_base;
long vram_size, nvram_size;
// IRQ numbers are not PIL ones, but master interrupt controller
- // register bit numbers except for clock_irq, which indexes cpu
- // interrupt controller register
+ // register bit numbers
int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq;
int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq;
int machine_id; // For NVRAM
.nvram_size = 0x2000,
.esp_irq = 18,
.le_irq = 16,
- .clock_irq = 14,
+ .clock_irq = 7,
.clock1_irq = 19,
.ms_kb_irq = 14,
.ser_irq = 15,
.nvram_size = 0x2000,
.esp_irq = 18,
.le_irq = 16,
- .clock_irq = 14,
+ .clock_irq = 7,
.clock1_irq = 19,
.ms_kb_irq = 14,
.ser_irq = 15,
.nvram_size = 0x2000,
.esp_irq = 18,
.le_irq = 16,
- .clock_irq = 14,
+ .clock_irq = 7,
.clock1_irq = 19,
.ms_kb_irq = 14,
.ser_irq = 15,
.nvram_size = 0x2000,
.esp_irq = 18,
.le_irq = 16,
- .clock_irq = 14,
+ .clock_irq = 7,
.clock1_irq = 19,
.ms_kb_irq = 14,
.ser_irq = 15,