net/mlx5e: TX, Add geneve tunnel stateless offload support

Currently support only default geneve udp port (6081).
For the tx side, the HW is assisted by SW parsing, which sets the
headers offset to offload tunneled LSO and csum. Note that for udp
tunnels, we don't use special rx offloads, as rss on the outer headers
is enough, we support checksum complete and GRO takes care of
aggregation.

Geneve TSO BW and CPU load results (tested using iperf single tcp
stream).
In this patch we add TSO support over Geneve, so the "before" result
doesn't actually get to using the TSO HW offload even when turned on.
Tested on ConnectX-5, Intel(R) Xeon(R) CPU E5-2660 v2 @2.20GHz.

 __________________________________
| Before         | After           |
|________________|_________________|
| 12.6 Gbits/sec | 21.7 Gbits/sec  |
| 100% CPU load  | 61.5% CPU load  |
|________________|_________________|

Signed-off-by: Moshe Shemesh <moshe@mellanox.com>
Acked-by: Or Gerlitz <ogerlitz@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/ethernet/mellanox/mlx5/core/en.h
index 16a64485a13b56e4dee87f0b2f08681663bc3f41..9e71cf03369cc418000b60096fad9ee88dc770cb 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/en.h
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h
@@ -884,6 +884,12 @@ static inline bool mlx5e_tunnel_inner_ft_supported(struct mlx5_core_dev *mdev)
                MLX5_CAP_FLOWTABLE_NIC_RX(mdev, ft_field_support.inner_ip_version));
 }
 
+static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev)
+{
+       return MLX5_CAP_ETH(mdev, swp) &&
+               MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso);
+}
+
 struct mlx5e_swp_spec {
        __be16 l3_proto;
        u8 l4_proto;

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h
index 1dd225380a66075eeceebe290209bfaf20cddf8c..6da7c88742dca01484bad12223ec35fa9ed982c1 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h
@@ -40,6 +40,57 @@
 #include "en_accel/tls_rxtx.h"
 #include "en.h"
 
+#if IS_ENABLED(CONFIG_GENEVE)
+static inline bool mlx5_geneve_tx_allowed(struct mlx5_core_dev *mdev)
+{
+       return mlx5_tx_swp_supported(mdev);
+}
+
+static inline void
+mlx5e_tx_tunnel_accel(struct sk_buff *skb, struct mlx5_wqe_eth_seg *eseg)
+{
+       struct mlx5e_swp_spec swp_spec = {};
+       unsigned int offset = 0;
+       __be16 l3_proto;
+       u8 l4_proto;
+
+       l3_proto = vlan_get_protocol(skb);
+       switch (l3_proto) {
+       case htons(ETH_P_IP):
+               l4_proto = ip_hdr(skb)->protocol;
+               break;
+       case htons(ETH_P_IPV6):
+               l4_proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
+               break;
+       default:
+               return;
+       }
+
+       if (l4_proto != IPPROTO_UDP ||
+           udp_hdr(skb)->dest != cpu_to_be16(GENEVE_UDP_PORT))
+               return;
+       swp_spec.l3_proto = l3_proto;
+       swp_spec.l4_proto = l4_proto;
+       swp_spec.is_tun = true;
+       if (inner_ip_hdr(skb)->version == 6) {
+               swp_spec.tun_l3_proto = htons(ETH_P_IPV6);
+               swp_spec.tun_l4_proto = inner_ipv6_hdr(skb)->nexthdr;
+       } else {
+               swp_spec.tun_l3_proto = htons(ETH_P_IP);
+               swp_spec.tun_l4_proto = inner_ip_hdr(skb)->protocol;
+       }
+
+       mlx5e_set_eseg_swp(skb, eseg, &swp_spec);
+}
+
+#else
+static inline bool mlx5_geneve_tx_allowed(struct mlx5_core_dev *mdev)
+{
+       return false;
+}
+
+#endif /* CONFIG_GENEVE */
+
 static inline void
 mlx5e_udp_gso_handle_tx_skb(struct sk_buff *skb)
 {

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
index b5fdbd3190d9fa99e6207c25e183354b1d5dad01..e08a1eb04e221c3497091c6ba8ef8d0e5f0060d0 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
@@ -34,6 +34,7 @@
 #include <net/pkt_cls.h>
 #include <linux/mlx5/fs.h>
 #include <net/vxlan.h>
+#include <net/geneve.h>
 #include <linux/bpf.h>
 #include <linux/if_bridge.h>
 #include <net/page_pool.h>
@@ -43,6 +44,7 @@
 #include "en_rep.h"
 #include "en_accel/ipsec.h"
 #include "en_accel/ipsec_rxtx.h"
+#include "en_accel/en_accel.h"
 #include "en_accel/tls.h"
 #include "accel/ipsec.h"
 #include "accel/tls.h"
@@ -2173,10 +2175,13 @@ static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
 {
        void *sqc = param->sqc;
        void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
+       bool allow_swp;
 
+       allow_swp = mlx5_geneve_tx_allowed(priv->mdev) ||
+                   !!MLX5_IPSEC_DEV(priv->mdev);
        mlx5e_build_sq_param_common(priv, param);
        MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
-       MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
+       MLX5_SET(sqc, sqc, allow_swp, allow_swp);
 }
 
 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
@@ -4103,6 +4108,12 @@ static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
                /* Verify if UDP port is being offloaded by HW */
                if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
                        return features;
+
+#if IS_ENABLED(CONFIG_GENEVE)
+               /* Support Geneve offload for default UDP port */
+               if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
+                       return features;
+#endif
        }
 
 out:
@@ -4674,7 +4685,8 @@ static void mlx5e_build_nic_netdev(struct net_device *netdev)
        netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
        netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
 
-       if (mlx5_vxlan_allowed(mdev->vxlan) || MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
+       if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev) ||
+           MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
                netdev->hw_enc_features |= NETIF_F_IP_CSUM;
                netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
                netdev->hw_enc_features |= NETIF_F_TSO;
@@ -4682,7 +4694,7 @@ static void mlx5e_build_nic_netdev(struct net_device *netdev)
                netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
        }
 
-       if (mlx5_vxlan_allowed(mdev->vxlan)) {
+       if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
                netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
                                           NETIF_F_GSO_UDP_TUNNEL_CSUM;
                netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c
index ce1406bb1512bff9d397b5b7839a04b4bfd7447d..41e2a01d3713f36bb956a566980a467e2d980f04 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c
@@ -32,6 +32,7 @@
 
 #include <linux/tcp.h>
 #include <linux/if_vlan.h>
+#include <net/geneve.h>
 #include <net/dsfield.h>
 #include "en.h"
 #include "ipoib/ipoib.h"
@@ -391,6 +392,10 @@ netdev_tx_t mlx5e_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb,
        eseg = &wqe->eth;
        dseg =  wqe->data;
 
+#if IS_ENABLED(CONFIG_GENEVE)
+       if (skb->encapsulation)
+               mlx5e_tx_tunnel_accel(skb, eseg);
+#endif
        mlx5e_txwqe_build_eseg_csum(sq, skb, eseg);
 
        eseg->mss = mss;