drm/amd/powerplay: add Vega20 support for gpu metrics export

Add Vega20 gpu metrics export interface.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index bacbe2fa1f9acd8c4ed3fa4b2af54ddc3a4ef431..037bebda2eaec7f7b5a576dddd5e58c14cebfbcd 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -55,6 +55,11 @@
 #define smnPCIE_LC_SPEED_CNTL                  0x11140290
 #define smnPCIE_LC_LINK_WIDTH_CNTL             0x11140288
 
+#define LINK_WIDTH_MAX                         6
+#define LINK_SPEED_MAX                         3
+static int link_width[] = {0, 1, 2, 4, 8, 12, 16};
+static int link_speed[] = {25, 50, 80, 160};
+
 static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr)
 {
        struct vega20_hwmgr *data =
@@ -3265,6 +3270,46 @@ static int vega20_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfe
        return 0;
 }
 
+static int vega20_get_current_pcie_link_width_level(struct pp_hwmgr *hwmgr)
+{
+       struct amdgpu_device *adev = hwmgr->adev;
+
+       return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
+               PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
+               >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
+}
+
+static int vega20_get_current_pcie_link_width(struct pp_hwmgr *hwmgr)
+{
+       uint32_t width_level;
+
+       width_level = vega20_get_current_pcie_link_width_level(hwmgr);
+       if (width_level > LINK_WIDTH_MAX)
+               width_level = 0;
+
+       return link_width[width_level];
+}
+
+static int vega20_get_current_pcie_link_speed_level(struct pp_hwmgr *hwmgr)
+{
+       struct amdgpu_device *adev = hwmgr->adev;
+
+       return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
+               PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
+               >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
+}
+
+static int vega20_get_current_pcie_link_speed(struct pp_hwmgr *hwmgr)
+{
+       uint32_t speed_level;
+
+       speed_level = vega20_get_current_pcie_link_speed_level(hwmgr);
+       if (speed_level > LINK_SPEED_MAX)
+               speed_level = 0;
+
+       return link_speed[speed_level];
+}
+
 static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
                enum pp_clock_type type, char *buf)
 {
@@ -3277,7 +3322,6 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
        struct phm_ppt_v3_information *pptable_information =
                (struct phm_ppt_v3_information *)hwmgr->pptable;
        PPTable_t *pptable = (PPTable_t *)pptable_information->smc_pptable;
-       struct amdgpu_device *adev = hwmgr->adev;
        struct pp_clock_levels_with_latency clocks;
        struct vega20_single_dpm_table *fclk_dpm_table =
                        &(data->dpm_table.fclk_table);
@@ -3371,12 +3415,10 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
                break;
 
        case PP_PCIE:
-               current_gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
-                            PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
-                           >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
-               current_lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
-                             PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
-                           >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
+               current_gen_speed =
+                       vega20_get_current_pcie_link_speed_level(hwmgr);
+               current_lane_width =
+                       vega20_get_current_pcie_link_width_level(hwmgr);
                for (i = 0; i < NUM_LINK_LEVELS; i++) {
                        if (i == 1 && data->pcie_parameters_override) {
                                gen_speed = data->pcie_gen_level1;
@@ -4218,6 +4260,72 @@ static int vega20_set_xgmi_pstate(struct pp_hwmgr *hwmgr,
        return ret;
 }
 
+static void vega20_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics)
+{
+       memset(gpu_metrics, 0xFF, sizeof(struct gpu_metrics_v1_0));
+
+       gpu_metrics->common_header.structure_size =
+                               sizeof(struct gpu_metrics_v1_0);
+       gpu_metrics->common_header.format_revision = 1;
+       gpu_metrics->common_header.content_revision = 0;
+
+       gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
+}
+
+static ssize_t vega20_get_gpu_metrics(struct pp_hwmgr *hwmgr,
+                                     void **table)
+{
+       struct vega20_hwmgr *data =
+                       (struct vega20_hwmgr *)(hwmgr->backend);
+       struct gpu_metrics_v1_0 *gpu_metrics =
+                       &data->gpu_metrics_table;
+       SmuMetrics_t metrics;
+       uint32_t fan_speed_rpm;
+       int ret;
+
+       ret = vega20_get_metrics_table(hwmgr, &metrics);
+       if (ret)
+               return ret;
+
+       vega20_init_gpu_metrics_v1_0(gpu_metrics);
+
+       gpu_metrics->temperature_edge = metrics.TemperatureEdge;
+       gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
+       gpu_metrics->temperature_mem = metrics.TemperatureHBM;
+       gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
+       gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
+       gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
+
+       gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
+       gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
+
+       gpu_metrics->average_socket_power = metrics.AverageSocketPower;
+
+       gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
+       gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
+       gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
+
+       gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
+       gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
+       gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
+       gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
+       gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
+
+       gpu_metrics->throttle_status = metrics.ThrottlerStatus;
+
+       vega20_fan_ctrl_get_fan_speed_rpm(hwmgr, &fan_speed_rpm);
+       gpu_metrics->current_fan_speed = (uint16_t)fan_speed_rpm;
+
+       gpu_metrics->pcie_link_width =
+                       vega20_get_current_pcie_link_width(hwmgr);
+       gpu_metrics->pcie_link_speed =
+                       vega20_get_current_pcie_link_speed(hwmgr);
+
+       *table = (void *)gpu_metrics;
+
+       return sizeof(struct gpu_metrics_v1_0);
+}
+
 static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
        /* init/fini related */
        .backend_init = vega20_hwmgr_backend_init,
@@ -4288,6 +4396,7 @@ static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
        .smu_i2c_bus_access = vega20_smu_i2c_bus_access,
        .set_df_cstate = vega20_set_df_cstate,
        .set_xgmi_pstate = vega20_set_xgmi_pstate,
+       .get_gpu_metrics = vega20_get_gpu_metrics,
 };
 
 int vega20_hwmgr_init(struct pp_hwmgr *hwmgr)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h
index 2c3125f82b24acf2f6e6c7698694e88f3ee8a640..075c0094da9c0aee7ba889b23b8e8c4596984b8d 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h
@@ -527,6 +527,7 @@ struct vega20_hwmgr {
 
        unsigned long                  metrics_time;
        SmuMetrics_t                   metrics_table;
+       struct gpu_metrics_v1_0        gpu_metrics_table;
 
        bool                           pcie_parameters_override;
        uint32_t                       pcie_gen_level1;