extern void init_VISWS_APIC_irqs(void);
extern void setup_IO_APIC(void);
extern void disable_IO_APIC(void);
+
+struct io_apic_irq_attr {
+ int ioapic;
+ int ioapic_pin;
+ int trigger;
+ int polarity;
+};
+
+static inline void set_io_apic_irq_attr(struct io_apic_irq_attr *irq_attr,
+ int ioapic, int ioapic_pin,
+ int trigger, int polarity)
+{
+ irq_attr->ioapic = ioapic;
+ irq_attr->ioapic_pin = ioapic_pin;
+ irq_attr->trigger = trigger;
+ irq_attr->polarity = polarity;
+}
+
extern int IO_APIC_get_PCI_irq_vector(int bus, int devfn, int pin,
- int *ioapic, int *ioapic_pin,
- int *trigger, int *polarity);
+ struct io_apic_irq_attr *irq_attr);
extern void setup_ioapic_dest(void);
extern void enable_IO_APIC(void);
extern int io_apic_get_redir_entries(int ioapic);
#endif /* CONFIG_ACPI */
-extern int io_apic_set_pci_routing(struct device *dev, int ioapic, int pin,
- int irq, int edge_level, int active_high_low);
+struct io_apic_irq_attr;
+extern int io_apic_set_pci_routing(struct device *dev, int irq,
+ struct io_apic_irq_attr *irq_attr);
extern int (*ioapic_renumber_irq)(int ioapic, int irq);
extern void ioapic_init_mappings(void);
* success: return IRQ number (>=0)
* failure: return < 0
*/
-int acpi_register_gsi(struct device *dev, u32 gsi, int triggering, int polarity)
+int acpi_register_gsi(struct device *dev, u32 gsi, int trigger, int polarity)
{
unsigned int irq;
unsigned int plat_gsi = gsi;
* Make sure all (legacy) PCI IRQs are set as level-triggered.
*/
if (acpi_irq_model == ACPI_IRQ_MODEL_PIC) {
- if (triggering == ACPI_LEVEL_SENSITIVE)
+ if (trigger == ACPI_LEVEL_SENSITIVE)
eisa_set_level_irq(gsi);
}
#endif
#ifdef CONFIG_X86_IO_APIC
if (acpi_irq_model == ACPI_IRQ_MODEL_IOAPIC) {
- plat_gsi = mp_register_gsi(dev, gsi, triggering, polarity);
+ plat_gsi = mp_register_gsi(dev, gsi, trigger, polarity);
}
#endif
acpi_gsi_to_irq(plat_gsi, &irq);
}
}
-static int mp_config_acpi_gsi(struct device *dev, u32 gsi, int triggering,
+static int mp_config_acpi_gsi(struct device *dev, u32 gsi, int trigger,
int polarity)
{
#ifdef CONFIG_X86_MPPARSE
/* print the entry should happen on mptable identically */
mp_irq.type = MP_INTSRC;
mp_irq.irqtype = mp_INT;
- mp_irq.irqflag = (triggering == ACPI_EDGE_SENSITIVE ? 4 : 0x0c) |
+ mp_irq.irqflag = (trigger == ACPI_EDGE_SENSITIVE ? 4 : 0x0c) |
(polarity == ACPI_ACTIVE_HIGH ? 1 : 3);
mp_irq.srcbus = number;
mp_irq.srcbusirq = (((devfn >> 3) & 0x1f) << 2) | ((pin - 1) & 3);
return 0;
}
-int mp_register_gsi(struct device *dev, u32 gsi, int triggering, int polarity)
+int mp_register_gsi(struct device *dev, u32 gsi, int trigger, int polarity)
{
int ioapic;
int ioapic_pin;
+ struct io_apic_irq_attr irq_attr;
if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC)
return gsi;
ioapic_pin);
return gsi;
}
- mp_config_acpi_gsi(dev, gsi, triggering, polarity);
+ mp_config_acpi_gsi(dev, gsi, trigger, polarity);
- io_apic_set_pci_routing(dev, ioapic, ioapic_pin, gsi,
- triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
- polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
+ set_io_apic_irq_attr(&irq_attr, ioapic, ioapic_pin,
+ trigger == ACPI_EDGE_SENSITIVE ? 0 : 1,
+ polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
+ io_apic_set_pci_routing(dev, gsi, &irq_attr);
return gsi;
}
* Not an __init, possibly needed by modules
*/
int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
- int *ioapic, int *ioapic_pin,
- int *trigger, int *polarity)
+ struct io_apic_irq_attr *irq_attr)
{
int apic, i, best_guess = -1;
continue;
if (pin == (mp_irqs[i].srcbusirq & 3)) {
- *ioapic = apic;
- *ioapic_pin = mp_irqs[i].dstirq;
- *trigger = irq_trigger(i);
- *polarity = irq_polarity(i);
+ set_io_apic_irq_attr(irq_attr, apic,
+ mp_irqs[i].dstirq,
+ irq_trigger(i),
+ irq_polarity(i));
return irq;
}
/*
* best-guess fuzzy result for broken mptables.
*/
if (best_guess < 0) {
- *ioapic = apic;
- *ioapic_pin = mp_irqs[i].dstirq;
- *trigger = irq_trigger(i);
- *polarity = irq_polarity(i);
+ set_io_apic_irq_attr(irq_attr, apic,
+ mp_irqs[i].dstirq,
+ irq_trigger(i),
+ irq_polarity(i));
best_guess = irq;
}
}
}
#endif
-static int __io_apic_set_pci_routing(struct device *dev, int ioapic, int pin, int irq,
- int triggering, int polarity)
+static int __io_apic_set_pci_routing(struct device *dev, int irq,
+ struct io_apic_irq_attr *irq_attr)
{
struct irq_desc *desc;
struct irq_cfg *cfg;
int node;
+ int ioapic, pin;
+ int trigger, polarity;
+ ioapic = irq_attr->ioapic;
if (!IO_APIC_IRQ(irq)) {
apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
ioapic);
return 0;
}
+ pin = irq_attr->ioapic_pin;
+ trigger = irq_attr->trigger;
+ polarity = irq_attr->polarity;
+
/*
* IRQs < 16 are already in the irq_2_pin[] map
*/
add_pin_to_irq_node(cfg, node, ioapic, pin);
}
- setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity);
+ setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity);
return 0;
}
-int io_apic_set_pci_routing(struct device *dev, int ioapic, int pin, int irq,
- int triggering, int polarity)
+int io_apic_set_pci_routing(struct device *dev, int irq,
+ struct io_apic_irq_attr *irq_attr)
{
-
+ int ioapic, pin;
/*
* Avoid pin reprogramming. PRTs typically include entries
* with redundant pin->gsi mappings (but unique PCI devices);
* we only program the IOAPIC on the first.
*/
+ ioapic = irq_attr->ioapic;
+ pin = irq_attr->ioapic_pin;
if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) {
pr_debug("Pin %d-%d already programmed\n",
mp_ioapics[ioapic].apicid, pin);
}
set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed);
- return __io_apic_set_pci_routing(dev, ioapic, pin, irq,
- triggering, polarity);
+ return __io_apic_set_pci_routing(dev, irq, irq_attr);
}
/* --------------------------------------------------------------------------
#ifdef CONFIG_X86_IO_APIC
struct pci_dev *temp_dev;
int irq;
- int ioapic = -1, ioapic_pin = -1;
- int triggering, polarity;
+ struct io_apic_irq_attr irq_attr;
irq = IO_APIC_get_PCI_irq_vector(dev->bus->number,
PCI_SLOT(dev->devfn),
- pin - 1,
- &ioapic, &ioapic_pin,
- &triggering, &polarity);
+ pin - 1, &irq_attr);
/*
* Busses behind bridges are typically not listed in the MP-table.
* In this case we have to look up the IRQ based on the parent bus,
pin = pci_swizzle_interrupt_pin(dev, pin);
irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
PCI_SLOT(bridge->devfn),
- pin - 1,
- &ioapic, &ioapic_pin,
- &triggering, &polarity);
+ pin - 1, &irq_attr);
if (irq >= 0)
dev_warn(&dev->dev, "using bridge %s "
"INT %c to get IRQ %d\n",
}
dev = temp_dev;
if (irq >= 0) {
- io_apic_set_pci_routing(&dev->dev, ioapic,
- ioapic_pin, irq,
- triggering, polarity);
+ io_apic_set_pci_routing(&dev->dev, irq,
+ &irq_attr);
dev->irq = irq;
dev_info(&dev->dev, "PCI->APIC IRQ transform: "
"INT %c -> IRQ %d\n", 'A' + pin - 1, irq);
for (loop = 0; loop < len; loop++) {
if ((*cur_slot)->number == rtable->slots[loop].slot &&
(*cur_slot)->bus == rtable->slots[loop].bus) {
- int ioapic = -1, ioapic_pin = -1;
- int triggering, polarity;
+ struct io_apic_irq_attr irq_attr;
(*cur_slot)->device = PCI_SLOT(rtable->slots[loop].devfn);
for (i = 0; i < 4; i++)
(*cur_slot)->irq[i] = IO_APIC_get_PCI_irq_vector((int) (*cur_slot)->bus,
(int) (*cur_slot)->device, i,
- &ioapic, &ioapic_pin,
- &triggering, &polarity);
+ &irq_attr);
debug("(*cur_slot)->irq[0] = %x\n",
(*cur_slot)->irq[0]);