drm/msm/dpu: inline IRQ_n_MASK defines

IRQ masks are rarely shared between different DPU revisions. Inline them
to the dpu_mdss_cfg intances and drop them from the dpu_hw_catalog.c

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/530875/
Link: https://lore.kernel.org/r/20230404130622.509628-36-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index 8e6650aaa8a2a04423cf4cf318ff32bad5112a16..e5a42ebda4d7a98e38fd48df86a0f4412bc4caae 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -197,7 +197,14 @@ static const struct dpu_mdss_cfg msm8998_dpu_cfg = {
        .vbif = msm8998_vbif,
        .reg_dma_count = 0,
        .perf = &msm8998_perf_data,
-       .mdss_irqs = IRQ_SM8250_MASK,
+       .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
+                    BIT(MDP_SSPP_TOP0_INTR2) | \
+                    BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+                    BIT(MDP_INTF0_INTR) | \
+                    BIT(MDP_INTF1_INTR) | \
+                    BIT(MDP_INTF2_INTR) | \
+                    BIT(MDP_INTF3_INTR) | \
+                    BIT(MDP_INTF4_INTR),
 };
 
 #endif

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
index 3e3b9967dd12327c52cdfb079a76afaa5b949184..46b0e9e50ced4b0ebbef7f209c1ab3b96fed4e0f 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
@@ -196,7 +196,15 @@ static const struct dpu_mdss_cfg sdm845_dpu_cfg = {
        .reg_dma_count = 1,
        .dma_cfg = &sdm845_regdma,
        .perf = &sdm845_perf_data,
-       .mdss_irqs = IRQ_SDM845_MASK,
+       .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
+                    BIT(MDP_SSPP_TOP0_INTR2) | \
+                    BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+                    BIT(MDP_INTF0_INTR) | \
+                    BIT(MDP_INTF1_INTR) | \
+                    BIT(MDP_INTF2_INTR) | \
+                    BIT(MDP_INTF3_INTR) | \
+                    BIT(MDP_AD4_0_INTR) | \
+                    BIT(MDP_AD4_1_INTR),
 };
 
 #endif

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index 29bcbc88cd5acb4e2ea1abec48f3a87c894ddd63..0d9c627b467bb6f7f3c7e410667711a4059ab19e 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -223,7 +223,15 @@ static const struct dpu_mdss_cfg sm8150_dpu_cfg = {
        .reg_dma_count = 1,
        .dma_cfg = &sm8150_regdma,
        .perf = &sm8150_perf_data,
-       .mdss_irqs = IRQ_SDM845_MASK,
+       .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
+                    BIT(MDP_SSPP_TOP0_INTR2) | \
+                    BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+                    BIT(MDP_INTF0_INTR) | \
+                    BIT(MDP_INTF1_INTR) | \
+                    BIT(MDP_INTF2_INTR) | \
+                    BIT(MDP_INTF3_INTR) | \
+                    BIT(MDP_AD4_0_INTR) | \
+                    BIT(MDP_AD4_1_INTR),
 };
 
 #endif

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
index fb8cdcd6bfe9d827180e084b6ac5d2bf3cf836b8..b01dfd47ed2fa683b66d4a28ada7c6c6f388b1f6 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
@@ -201,7 +201,17 @@ static const struct dpu_mdss_cfg sc8180x_dpu_cfg = {
        .reg_dma_count = 1,
        .dma_cfg = &sm8150_regdma,
        .perf = &sc8180x_perf_data,
-       .mdss_irqs = IRQ_SC8180X_MASK,
+       .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
+                    BIT(MDP_SSPP_TOP0_INTR2) | \
+                    BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+                    BIT(MDP_INTF0_INTR) | \
+                    BIT(MDP_INTF1_INTR) | \
+                    BIT(MDP_INTF2_INTR) | \
+                    BIT(MDP_INTF3_INTR) | \
+                    BIT(MDP_INTF4_INTR) | \
+                    BIT(MDP_INTF5_INTR) | \
+                    BIT(MDP_AD4_0_INTR) | \
+                    BIT(MDP_AD4_1_INTR),
 };
 
 #endif

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
index 233ea66155bd98fc04e30b2786a40faa3cbd6ffe..857f8aab4e0d08c5375cba6ee639c284872b95a2 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
@@ -231,7 +231,14 @@ static const struct dpu_mdss_cfg sm8250_dpu_cfg = {
        .reg_dma_count = 1,
        .dma_cfg = &sm8250_regdma,
        .perf = &sm8250_perf_data,
-       .mdss_irqs = IRQ_SM8250_MASK,
+       .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
+                    BIT(MDP_SSPP_TOP0_INTR2) | \
+                    BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+                    BIT(MDP_INTF0_INTR) | \
+                    BIT(MDP_INTF1_INTR) | \
+                    BIT(MDP_INTF2_INTR) | \
+                    BIT(MDP_INTF3_INTR) | \
+                    BIT(MDP_INTF4_INTR),
 };
 
 #endif

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
index 433f7b259f7b44c9bc156de6b07d9062b6c2f976..19dbc72aa137d74e95cbf55b6de923e6a8918eab 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
@@ -146,7 +146,11 @@ static const struct dpu_mdss_cfg sc7180_dpu_cfg = {
        .reg_dma_count = 1,
        .dma_cfg = &sdm845_regdma,
        .perf = &sc7180_perf_data,
-       .mdss_irqs = IRQ_SC7180_MASK,
+       .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
+                    BIT(MDP_SSPP_TOP0_INTR2) | \
+                    BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+                    BIT(MDP_INTF0_INTR) | \
+                    BIT(MDP_INTF1_INTR),
 };
 
 #endif

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
index e741cb3e7888bd8ffc61cd8f6955d8e648ef0288..8b276e0b5b716ac7f23715a366513dbb9522bab5 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
@@ -119,7 +119,11 @@ static const struct dpu_mdss_cfg sm6115_dpu_cfg = {
        .vbif_count = ARRAY_SIZE(sdm845_vbif),
        .vbif = sdm845_vbif,
        .perf = &sm6115_perf_data,
-       .mdss_irqs = IRQ_SC7180_MASK,
+       .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
+                    BIT(MDP_SSPP_TOP0_INTR2) | \
+                    BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+                    BIT(MDP_INTF0_INTR) | \
+                    BIT(MDP_INTF1_INTR),
 };
 
 #endif

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
index c0f95473611d72e611d65fb61b3c7a198eaacb83..9c4ad9795c1b6da478148ddb80765a67abdfd481 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
@@ -109,7 +109,11 @@ static const struct dpu_mdss_cfg qcm2290_dpu_cfg = {
        .vbif_count = ARRAY_SIZE(sdm845_vbif),
        .vbif = sdm845_vbif,
        .perf = &qcm2290_perf_data,
-       .mdss_irqs = IRQ_SC7180_MASK,
+       .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
+                    BIT(MDP_SSPP_TOP0_INTR2) | \
+                    BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+                    BIT(MDP_INTF0_INTR) | \
+                    BIT(MDP_INTF1_INTR),
 };
 
 #endif

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index a5818878ee0ad5057526e1f3792e169bebe3935c..7846c2f3a1fe28bb3797f646d39a035d30de2473 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -214,7 +214,13 @@ static const struct dpu_mdss_cfg sm8350_dpu_cfg = {
        .reg_dma_count = 1,
        .dma_cfg = &sm8350_regdma,
        .perf = &sm8350_perf_data,
-       .mdss_irqs = IRQ_SM8350_MASK,
+       .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
+                    BIT(MDP_SSPP_TOP0_INTR2) | \
+                    BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+                    BIT(MDP_INTF0_7xxx_INTR) | \
+                    BIT(MDP_INTF1_7xxx_INTR) | \
+                    BIT(MDP_INTF2_7xxx_INTR) | \
+                    BIT(MDP_INTF3_7xxx_INTR),
 };
 
 #endif

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index 0b10e2060591a887501546c361e75520ecaf611a..11ef3b8f1fa45a2d95329dcac190aec5b7dfadfc 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -147,7 +147,12 @@ static const struct dpu_mdss_cfg sc7280_dpu_cfg = {
        .vbif_count = ARRAY_SIZE(sdm845_vbif),
        .vbif = sdm845_vbif,
        .perf = &sc7280_perf_data,
-       .mdss_irqs = IRQ_SC7280_MASK,
+       .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
+                    BIT(MDP_SSPP_TOP0_INTR2) | \
+                    BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+                    BIT(MDP_INTF0_7xxx_INTR) | \
+                    BIT(MDP_INTF1_7xxx_INTR) | \
+                    BIT(MDP_INTF5_7xxx_INTR),
 };
 
 #endif

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index 0d100f7b3c032d85d784f9cfed8bf6fbff26fbdb..e83df053838dd7f679d753d80f7707a43e0451c6 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -205,7 +205,18 @@ static const struct dpu_mdss_cfg sc8280xp_dpu_cfg = {
        .reg_dma_count = 1,
        .dma_cfg = &sc8280xp_regdma,
        .perf = &sc8280xp_perf_data,
-       .mdss_irqs = IRQ_SC8280XP_MASK,
+       .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
+                    BIT(MDP_SSPP_TOP0_INTR2) | \
+                    BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+                    BIT(MDP_INTF0_7xxx_INTR) | \
+                    BIT(MDP_INTF1_7xxx_INTR) | \
+                    BIT(MDP_INTF2_7xxx_INTR) | \
+                    BIT(MDP_INTF3_7xxx_INTR) | \
+                    BIT(MDP_INTF4_7xxx_INTR) | \
+                    BIT(MDP_INTF5_7xxx_INTR) | \
+                    BIT(MDP_INTF6_7xxx_INTR) | \
+                    BIT(MDP_INTF7_7xxx_INTR) | \
+                    BIT(MDP_INTF8_7xxx_INTR),
 };
 
 #endif

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index fa603034ffabc085eeb434d8657fd9cb0da1d635..8205b5076bd32e8cd709952aaafb13cebdc67e96 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -222,7 +222,13 @@ static const struct dpu_mdss_cfg sm8450_dpu_cfg = {
        .reg_dma_count = 1,
        .dma_cfg = &sm8450_regdma,
        .perf = &sm8450_perf_data,
-       .mdss_irqs = IRQ_SM8450_MASK,
+       .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
+                    BIT(MDP_SSPP_TOP0_INTR2) | \
+                    BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+                    BIT(MDP_INTF0_7xxx_INTR) | \
+                    BIT(MDP_INTF1_7xxx_INTR) | \
+                    BIT(MDP_INTF2_7xxx_INTR) | \
+                    BIT(MDP_INTF3_7xxx_INTR),
 };
 
 #endif

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index 9acd9fcf39a1d89abbece62216fdd180fe73ee0f..aafb1680c9a22e6858a150579497b80fc6646146 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -227,7 +227,13 @@ static const struct dpu_mdss_cfg sm8550_dpu_cfg = {
        .reg_dma_count = 1,
        .dma_cfg = &sm8450_regdma,
        .perf = &sm8550_perf_data,
-       .mdss_irqs = IRQ_SM8450_MASK,
+       .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
+                    BIT(MDP_SSPP_TOP0_INTR2) | \
+                    BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+                    BIT(MDP_INTF0_7xxx_INTR) | \
+                    BIT(MDP_INTF1_7xxx_INTR) | \
+                    BIT(MDP_INTF2_7xxx_INTR) | \
+                    BIT(MDP_INTF3_7xxx_INTR),
 };
 
 #endif

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 547546d8547430dd5109428507f37be23a1ba044..0fcde3757b728a3a14cef2f149de5cc05cc26150 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -102,79 +102,6 @@
 
 #define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN)
 
-#define IRQ_SDM845_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
-                        BIT(MDP_SSPP_TOP0_INTR2) | \
-                        BIT(MDP_SSPP_TOP0_HIST_INTR) | \
-                        BIT(MDP_INTF0_INTR) | \
-                        BIT(MDP_INTF1_INTR) | \
-                        BIT(MDP_INTF2_INTR) | \
-                        BIT(MDP_INTF3_INTR) | \
-                        BIT(MDP_AD4_0_INTR) | \
-                        BIT(MDP_AD4_1_INTR))
-
-#define IRQ_SC7180_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
-                        BIT(MDP_SSPP_TOP0_INTR2) | \
-                        BIT(MDP_SSPP_TOP0_HIST_INTR) | \
-                        BIT(MDP_INTF0_INTR) | \
-                        BIT(MDP_INTF1_INTR))
-
-#define IRQ_SC7280_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
-                        BIT(MDP_SSPP_TOP0_INTR2) | \
-                        BIT(MDP_SSPP_TOP0_HIST_INTR) | \
-                        BIT(MDP_INTF0_7xxx_INTR) | \
-                        BIT(MDP_INTF1_7xxx_INTR) | \
-                        BIT(MDP_INTF5_7xxx_INTR))
-
-#define IRQ_SM8250_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
-                        BIT(MDP_SSPP_TOP0_INTR2) | \
-                        BIT(MDP_SSPP_TOP0_HIST_INTR) | \
-                        BIT(MDP_INTF0_INTR) | \
-                        BIT(MDP_INTF1_INTR) | \
-                        BIT(MDP_INTF2_INTR) | \
-                        BIT(MDP_INTF3_INTR) | \
-                        BIT(MDP_INTF4_INTR))
-
-#define IRQ_SM8350_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
-                        BIT(MDP_SSPP_TOP0_INTR2) | \
-                        BIT(MDP_SSPP_TOP0_HIST_INTR) | \
-                        BIT(MDP_INTF0_7xxx_INTR) | \
-                        BIT(MDP_INTF1_7xxx_INTR) | \
-                        BIT(MDP_INTF2_7xxx_INTR) | \
-                        BIT(MDP_INTF3_7xxx_INTR))
-
-#define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
-                         BIT(MDP_SSPP_TOP0_INTR2) | \
-                         BIT(MDP_SSPP_TOP0_HIST_INTR) | \
-                         BIT(MDP_INTF0_INTR) | \
-                         BIT(MDP_INTF1_INTR) | \
-                         BIT(MDP_INTF2_INTR) | \
-                         BIT(MDP_INTF3_INTR) | \
-                         BIT(MDP_INTF4_INTR) | \
-                         BIT(MDP_INTF5_INTR) | \
-                         BIT(MDP_AD4_0_INTR) | \
-                         BIT(MDP_AD4_1_INTR))
-
-#define IRQ_SC8280XP_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
-                          BIT(MDP_SSPP_TOP0_INTR2) | \
-                          BIT(MDP_SSPP_TOP0_HIST_INTR) | \
-                          BIT(MDP_INTF0_7xxx_INTR) | \
-                          BIT(MDP_INTF1_7xxx_INTR) | \
-                          BIT(MDP_INTF2_7xxx_INTR) | \
-                          BIT(MDP_INTF3_7xxx_INTR) | \
-                          BIT(MDP_INTF4_7xxx_INTR) | \
-                          BIT(MDP_INTF5_7xxx_INTR) | \
-                          BIT(MDP_INTF6_7xxx_INTR) | \
-                          BIT(MDP_INTF7_7xxx_INTR) | \
-                          BIT(MDP_INTF8_7xxx_INTR))
-
-#define IRQ_SM8450_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
-                        BIT(MDP_SSPP_TOP0_INTR2) | \
-                        BIT(MDP_SSPP_TOP0_HIST_INTR) | \
-                        BIT(MDP_INTF0_7xxx_INTR) | \
-                        BIT(MDP_INTF1_7xxx_INTR) | \
-                        BIT(MDP_INTF2_7xxx_INTR) | \
-                        BIT(MDP_INTF3_7xxx_INTR))
-
 #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \
                         BIT(DPU_WB_UBWC) | \
                         BIT(DPU_WB_YUV_CONFIG) | \