]> git.proxmox.com Git - mirror_ubuntu-kernels.git/commitdiff
net: mdio: Fix spelling mistakes
authorZheng Yongjun <zhengyongjun3@huawei.com>
Tue, 1 Jun 2021 14:18:59 +0000 (22:18 +0800)
committerDavid S. Miller <davem@davemloft.net>
Wed, 2 Jun 2021 00:05:05 +0000 (17:05 -0700)
informations  ==> information
typicaly  ==> typically
derrive  ==> derive
eventhough  ==> even though

Signed-off-by: Zheng Yongjun <zhengyongjun3@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/mdio/mdio-bcm-unimac.c
drivers/net/mdio/mdio-mux-bcm-iproc.c
drivers/net/mdio/mdio-mux-meson-g12a.c
drivers/net/mdio/of_mdio.c

index 5d171e7f118df40c4b08303f5c18deedc6e623dd..bfc9be23c9731181d1925f89ce6c1451602cfde2 100644 (file)
@@ -203,7 +203,7 @@ static void unimac_mdio_clk_set(struct unimac_mdio_priv *priv)
                return;
        }
 
-       /* The MDIO clock is the reference clock (typicaly 250Mhz) divided by
+       /* The MDIO clock is the reference clock (typically 250Mhz) divided by
         * 2 x (MDIO_CLK_DIV + 1)
         */
        reg = unimac_mdio_readl(priv, MDIO_CFG);
index 03261e6b9ceb5b07be834509f91a9a48ae62064a..239e88c7a272e983b0b468bb4f2970420e09ed33 100644 (file)
@@ -65,7 +65,7 @@ static void mdio_mux_iproc_config(struct iproc_mdiomux_desc *md)
        writel(val, md->base + MDIO_SCAN_CTRL_OFFSET);
 
        if (md->core_clk) {
-               /* use rate adjust regs to derrive the mdio's operating
+               /* use rate adjust regs to derive the mdio's operating
                 * frequency from the specified core clock
                 */
                divisor = clk_get_rate(md->core_clk) / MDIO_OPERATING_FREQUENCY;
index bf86c9c7a288366fe6ff5849764626cc0e6c5ea9..b8866bc3f2e8b7b77f5d3639f81e771ddd9c6779 100644 (file)
@@ -95,7 +95,7 @@ static int g12a_ephy_pll_enable(struct clk_hw *hw)
 
        /* Poll on the digital lock instead of the usual analog lock
         * This is done because bit 31 is unreliable on some SoC. Bit
-        * 31 may indicate that the PLL is not lock eventhough the clock
+        * 31 may indicate that the PLL is not lock even though the clock
         * is actually running
         */
        return readl_poll_timeout(pll->base + ETH_PLL_CTL0, val,
index 094494a68ddfe2ecb9ff130605cb187376d6623f..8e97d5b825f5a4aaed661d10534f6feae6fbeac9 100644 (file)
@@ -466,7 +466,7 @@ EXPORT_SYMBOL(of_phy_get_and_connect);
  * of_phy_is_fixed_link() and of_phy_register_fixed_link() must
  * support two DT bindings:
  * - the old DT binding, where 'fixed-link' was a property with 5
- *   cells encoding various informations about the fixed PHY
+ *   cells encoding various information about the fixed PHY
  * - the new DT binding, where 'fixed-link' is a sub-node of the
  *   Ethernet device.
  */