arm64/sysreg: Convert MVFR0_EL1 to automatic generation

Convert MVFR0_EL1 to be automatically generated as per DDI0487I.a,
no functional changes.

Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: James Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20221130171637.718182-33-james.morse@arm.com
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index ccb64dc09a4e6e2968afe5b87c88ff20e939f331..561968f7b66d25729bd46e1ef26ea7679f4781bb 100644 (file)
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -170,7 +170,6 @@
 #define SYS_ID_AFR0_EL1                        sys_reg(3, 0, 0, 1, 3)
 #define SYS_ID_MMFR5_EL1               sys_reg(3, 0, 0, 3, 6)
 
-#define SYS_MVFR0_EL1                  sys_reg(3, 0, 0, 3, 0)
 #define SYS_MVFR1_EL1                  sys_reg(3, 0, 0, 3, 1)
 #define SYS_MVFR2_EL1                  sys_reg(3, 0, 0, 3, 2)
 
@@ -693,15 +692,6 @@
 #define ID_DFR0_EL1_CopSDbg_SHIFT      4
 #define ID_DFR0_EL1_CopDbg_SHIFT       0
 
-#define MVFR0_EL1_FPRound_SHIFT                28
-#define MVFR0_EL1_FPShVec_SHIFT                24
-#define MVFR0_EL1_FPSqrt_SHIFT         20
-#define MVFR0_EL1_FPDivide_SHIFT       16
-#define MVFR0_EL1_FPTrap_SHIFT         12
-#define MVFR0_EL1_FPDP_SHIFT           8
-#define MVFR0_EL1_FPSP_SHIFT           4
-#define MVFR0_EL1_SIMDReg_SHIFT                0
-
 #define MVFR1_EL1_SIMDFMAC_SHIFT       28
 #define MVFR1_EL1_FPHP_SHIFT           24
 #define MVFR1_EL1_SIMDHP_SHIFT 20

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 667428a8957882bb374fc68bf34723b1f9a86cfa..7a56a9a0efdf25eff68b2a2aafd0509a40368d4c 100644 (file)
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -606,6 +606,45 @@ Enum       3:0     SpecSEI
 EndEnum
 EndSysreg
 
+Sysreg MVFR0_EL1       3       0       0       3       0
+Res0   63:32
+Enum   31:28   FPRound
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   27:24   FPShVec
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   23:20   FPSqrt
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   19:16   FPDivide
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   15:12   FPTrap
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   11:8    FPDP
+       0b0000  NI
+       0b0001  VFPv2
+       0b0001  VFPv3
+EndEnum
+Enum   7:4     FPSP
+       0b0000  NI
+       0b0001  VFPv2
+       0b0001  VFPv3
+EndEnum
+Enum   3:0     SIMDReg
+       0b0000  NI
+       0b0001  IMP_16x64
+       0b0001  IMP_32x64
+EndEnum
+EndSysreg
+
 Sysreg ID_PFR2_EL1     3       0       0       3       4
 Res0   63:12
 Enum   11:8    RAS_frac