ARM: 7207/1: Use generic ARM instruction set condition code checks for nwfpe.

This patch changes the nwfpe implementation to use the new generic
ARM instruction set condition code checks, rather than a local
implementation. It also removes the existing condition code checking,
which has been used for the generic support (in kernel/opcodes.{ch}).

This code has not been tested beyond building, linking and booting.

Signed-off-by: Leif Lindholm <leif.lindholm@arm.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/arch/arm/nwfpe/entry.S b/arch/arm/nwfpe/entry.S
index cafa1835433977808d47ce5900d85bbc19a3ea7f..d18dde95b8aae6a12dd319e71747ff58dfad8d84 100644 (file)
--- a/arch/arm/nwfpe/entry.S
+++ b/arch/arm/nwfpe/entry.S
@@ -20,6 +20,8 @@
     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */
 
+#include <asm/opcodes.h>
+
 /* This is the kernel's entry point into the floating point emulator.
 It is called from the kernel with code similar to this:
 
@@ -81,11 +83,11 @@ nwfpe_enter:
        mov     r6, r0                  @ save the opcode
 emulate:
        ldr     r1, [sp, #S_PSR]        @ fetch the PSR
-       bl      checkCondition          @ check the condition
-       cmp     r0, #0                  @ r0 = 0 ==> condition failed
+       bl      arm_check_condition     @ check the condition
+       cmp     r0, #ARM_OPCODE_CONDTEST_PASS   @ condition passed?
 
        @ if condition code failed to match, next insn
-       beq     next                    @ get the next instruction;
+       bne     next                    @ get the next instruction;
 
        mov     r0, r6                  @ prepare for EmulateAll()
        bl      EmulateAll              @ emulate the instruction

diff --git a/arch/arm/nwfpe/fpopcode.c b/arch/arm/nwfpe/fpopcode.c
index 922b81107585f324ccf7e5878643232729ad5d79..ff9834673085cb72c403fc97ee4398f59e2b087c 100644 (file)
--- a/arch/arm/nwfpe/fpopcode.c
+++ b/arch/arm/nwfpe/fpopcode.c
@@ -61,29 +61,3 @@ const float32 float32Constant[] = {
        0x41200000              /* single 10.0 */
 };
 
-/* condition code lookup table
- index into the table is test code: EQ, NE, ... LT, GT, AL, NV
- bit position in short is condition code: NZCV */
-static const unsigned short aCC[16] = {
-       0xF0F0,                 // EQ == Z set
-       0x0F0F,                 // NE
-       0xCCCC,                 // CS == C set
-       0x3333,                 // CC
-       0xFF00,                 // MI == N set
-       0x00FF,                 // PL
-       0xAAAA,                 // VS == V set
-       0x5555,                 // VC
-       0x0C0C,                 // HI == C set && Z clear
-       0xF3F3,                 // LS == C clear || Z set
-       0xAA55,                 // GE == (N==V)
-       0x55AA,                 // LT == (N!=V)
-       0x0A05,                 // GT == (!Z && (N==V))
-       0xF5FA,                 // LE == (Z || (N!=V))
-       0xFFFF,                 // AL always
-       0                       // NV
-};
-
-unsigned int checkCondition(const unsigned int opcode, const unsigned int ccodes)
-{
-       return (aCC[opcode >> 28] >> (ccodes >> 28)) & 1;
-}

diff --git a/arch/arm/nwfpe/fpopcode.h b/arch/arm/nwfpe/fpopcode.h
index 786e4c96156dcea95429d0ebca6fd9c0c2bfad23..78f02dbfaa8ffea4efda621044b119367f1e57e4 100644 (file)
--- a/arch/arm/nwfpe/fpopcode.h
+++ b/arch/arm/nwfpe/fpopcode.h
@@ -475,9 +475,6 @@ static inline unsigned int getDestinationSize(const unsigned int opcode)
        return (nRc);
 }
 
-extern unsigned int checkCondition(const unsigned int opcode,
-                                  const unsigned int ccodes);
-
 extern const float64 float64Constant[];
 extern const float32 float32Constant[];