drm/gma500/cdv: Cedarview display cleanups

Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>

diff --git a/drivers/gpu/drm/gma500/cdv_intel_display.c b/drivers/gpu/drm/gma500/cdv_intel_display.c
index 8fbfa06da62d867d8b70d944a7e195388ab36848..7ff91ce3b12a29c04290b23b2997448ff1e6cd75 100644 (file)
--- a/drivers/gpu/drm/gma500/cdv_intel_display.c
+++ b/drivers/gpu/drm/gma500/cdv_intel_display.c
@@ -412,8 +412,11 @@ static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit,
                                  int refclk,
                                  struct gma_clock_t *best_clock)
 {
+       struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
        struct gma_clock_t clock;
-       if (refclk == 27000) {
+
+       switch (refclk) {
+       case 27000:
                if (target < 200000) {
                        clock.p1 = 2;
                        clock.p2 = 10;
@@ -427,7 +430,9 @@ static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit,
                        clock.m1 = 0;
                        clock.m2 = 98;
                }
-       } else if (refclk == 100000) {
+               break;
+
+       case 100000:
                if (target < 200000) {
                        clock.p1 = 2;
                        clock.p2 = 10;
@@ -441,12 +446,13 @@ static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit,
                        clock.m1 = 0;
                        clock.m2 = 133;
                }
-       } else
+               break;
+
+       default:
                return false;
-       clock.m = clock.m2 + 2;
-       clock.p = clock.p1 * clock.p2;
-       clock.vco = (refclk * clock.m) / clock.n;
-       clock.dot = clock.vco / clock.p;
+       }
+
+       gma_crtc->clock_funcs->clock(refclk, &clock);
        memcpy(best_clock, &clock, sizeof(struct gma_clock_t));
        return true;
 }
@@ -468,49 +474,6 @@ static bool cdv_intel_pipe_enabled(struct drm_device *dev, int pipe)
        return true;
 }
 
-static bool cdv_intel_single_pipe_active (struct drm_device *dev)
-{
-       uint32_t pipe_enabled = 0;
-
-       if (cdv_intel_pipe_enabled(dev, 0))
-               pipe_enabled |= FIFO_PIPEA;
-
-       if (cdv_intel_pipe_enabled(dev, 1))
-               pipe_enabled |= FIFO_PIPEB;
-
-
-       DRM_DEBUG_KMS("pipe enabled %x\n", pipe_enabled);
-
-       if (pipe_enabled == FIFO_PIPEA || pipe_enabled == FIFO_PIPEB)
-               return true;
-       else
-               return false;
-}
-
-static bool is_pipeb_lvds(struct drm_device *dev, struct drm_crtc *crtc)
-{
-       struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
-       struct drm_mode_config *mode_config = &dev->mode_config;
-       struct drm_connector *connector;
-
-       if (gma_crtc->pipe != 1)
-               return false;
-
-       list_for_each_entry(connector, &mode_config->connector_list, head) {
-               struct gma_encoder *gma_encoder =
-                                       gma_attached_encoder(connector);
-
-               if (!connector->encoder
-                   || connector->encoder->crtc != crtc)
-                       continue;
-
-               if (gma_encoder->type == INTEL_OUTPUT_LVDS)
-                       return true;
-       }
-
-       return false;
-}
-
 void cdv_disable_sr(struct drm_device *dev)
 {
        if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) {
@@ -535,8 +498,10 @@ void cdv_disable_sr(struct drm_device *dev)
 void cdv_update_wm(struct drm_device *dev, struct drm_crtc *crtc)
 {
        struct drm_psb_private *dev_priv = dev->dev_private;
+       struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
 
-       if (cdv_intel_single_pipe_active(dev)) {
+       /* Is only one pipe enabled? */
+       if (cdv_intel_pipe_enabled(dev, 0) ^ cdv_intel_pipe_enabled(dev, 1)) {
                u32 fw;
 
                fw = REG_READ(DSPFW1);
@@ -557,7 +522,9 @@ void cdv_update_wm(struct drm_device *dev, struct drm_crtc *crtc)
 
                /* ignore FW4 */
 
-               if (is_pipeb_lvds(dev, crtc)) {
+               /* Is pipe b lvds ? */
+               if (gma_crtc->pipe == 1 &&
+                   gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
                        REG_WRITE(DSPFW5, 0x00040330);
                } else {
                        fw = (3 << DSP_PLANE_B_FIFO_WM1_SHIFT) |