+++ /dev/null
-A. HISTORY OF THE SOFTWARE
-==========================
-
-Python was created in the early 1990s by Guido van Rossum at Stichting
-Mathematisch Centrum (CWI, see http://www.cwi.nl) in the Netherlands
-as a successor of a language called ABC. Guido remains Python's
-principal author, although it includes many contributions from others.
-
-In 1995, Guido continued his work on Python at the Corporation for
-National Research Initiatives (CNRI, see http://www.cnri.reston.va.us)
-in Reston, Virginia where he released several versions of the
-software.
-
-In May 2000, Guido and the Python core development team moved to
-BeOpen.com to form the BeOpen PythonLabs team. In October of the same
-year, the PythonLabs team moved to Digital Creations (now Zope
-Corporation, see http://www.zope.com). In 2001, the Python Software
-Foundation (PSF, see http://www.python.org/psf/) was formed, a
-non-profit organization created specifically to own Python-related
-Intellectual Property. Zope Corporation is a sponsoring member of
-the PSF.
-
-All Python releases are Open Source (see http://www.opensource.org for
-the Open Source Definition). Historically, most, but not all, Python
-releases have also been GPL-compatible; the table below summarizes
-the various releases.
-
- Release Derived Year Owner GPL-
- from compatible? (1)
-
- 0.9.0 thru 1.2 1991-1995 CWI yes
- 1.3 thru 1.5.2 1.2 1995-1999 CNRI yes
- 1.6 1.5.2 2000 CNRI no
- 2.0 1.6 2000 BeOpen.com no
- 1.6.1 1.6 2001 CNRI yes (2)
- 2.1 2.0+1.6.1 2001 PSF no
- 2.0.1 2.0+1.6.1 2001 PSF yes
- 2.1.1 2.1+2.0.1 2001 PSF yes
- 2.2 2.1.1 2001 PSF yes
- 2.1.2 2.1.1 2002 PSF yes
- 2.1.3 2.1.2 2002 PSF yes
- 2.2.1 2.2 2002 PSF yes
- 2.2.2 2.2.1 2002 PSF yes
- 2.2.3 2.2.2 2003 PSF yes
- 2.3 2.2.2 2002-2003 PSF yes
- 2.3.1 2.3 2002-2003 PSF yes
- 2.3.2 2.3.1 2002-2003 PSF yes
- 2.3.3 2.3.2 2002-2003 PSF yes
- 2.3.4 2.3.3 2004 PSF yes
- 2.3.5 2.3.4 2005 PSF yes
- 2.4 2.3 2004 PSF yes
- 2.4.1 2.4 2005 PSF yes
- 2.4.2 2.4.1 2005 PSF yes
- 2.4.3 2.4.2 2006 PSF yes
- 2.5 2.4 2006 PSF yes
- 2.7 2.6 2010 PSF yes
-
-Footnotes:
-
-(1) GPL-compatible doesn't mean that we're distributing Python under
- the GPL. All Python licenses, unlike the GPL, let you distribute
- a modified version without making your changes open source. The
- GPL-compatible licenses make it possible to combine Python with
- other software that is released under the GPL; the others don't.
-
-(2) According to Richard Stallman, 1.6.1 is not GPL-compatible,
- because its license has a choice of law clause. According to
- CNRI, however, Stallman's lawyer has told CNRI's lawyer that 1.6.1
- is "not incompatible" with the GPL.
-
-Thanks to the many outside volunteers who have worked under Guido's
-direction to make these releases possible.
-
-
-B. TERMS AND CONDITIONS FOR ACCESSING OR OTHERWISE USING PYTHON
-===============================================================
-
-PYTHON SOFTWARE FOUNDATION LICENSE VERSION 2
---------------------------------------------
-
-1. This LICENSE AGREEMENT is between the Python Software Foundation
-("PSF"), and the Individual or Organization ("Licensee") accessing and
-otherwise using this software ("Python") in source or binary form and
-its associated documentation.
-
-2. Subject to the terms and conditions of this License Agreement, PSF
-hereby grants Licensee a nonexclusive, royalty-free, world-wide
-license to reproduce, analyze, test, perform and/or display publicly,
-prepare derivative works, distribute, and otherwise use Python
-alone or in any derivative version, provided, however, that PSF's
-License Agreement and PSF's notice of copyright, i.e., "Copyright (c)
-2001, 2002, 2003, 2004, 2005, 2006 Python Software Foundation; All Rights
-Reserved" are retained in Python alone or in any derivative version
-prepared by Licensee.
-
-3. In the event Licensee prepares a derivative work that is based on
-or incorporates Python or any part thereof, and wants to make
-the derivative work available to others as provided herein, then
-Licensee hereby agrees to include in any such work a brief summary of
-the changes made to Python.
-
-4. PSF is making Python available to Licensee on an "AS IS"
-basis. PSF MAKES NO REPRESENTATIONS OR WARRANTIES, EXPRESS OR
-IMPLIED. BY WAY OF EXAMPLE, BUT NOT LIMITATION, PSF MAKES NO AND
-DISCLAIMS ANY REPRESENTATION OR WARRANTY OF MERCHANTABILITY OR FITNESS
-FOR ANY PARTICULAR PURPOSE OR THAT THE USE OF PYTHON WILL NOT
-INFRINGE ANY THIRD PARTY RIGHTS.
-
-5. PSF SHALL NOT BE LIABLE TO LICENSEE OR ANY OTHER USERS OF PYTHON
-FOR ANY INCIDENTAL, SPECIAL, OR CONSEQUENTIAL DAMAGES OR LOSS AS
-A RESULT OF MODIFYING, DISTRIBUTING, OR OTHERWISE USING PYTHON,
-OR ANY DERIVATIVE THEREOF, EVEN IF ADVISED OF THE POSSIBILITY THEREOF.
-
-6. This License Agreement will automatically terminate upon a material
-breach of its terms and conditions.
-
-7. Nothing in this License Agreement shall be deemed to create any
-relationship of agency, partnership, or joint venture between PSF and
-Licensee. This License Agreement does not grant permission to use PSF
-trademarks or trade name in a trademark sense to endorse or promote
-products or services of Licensee, or any third party.
-
-8. By copying, installing or otherwise using Python, Licensee
-agrees to be bound by the terms and conditions of this License
-Agreement.
-
-
-BEOPEN.COM LICENSE AGREEMENT FOR PYTHON 2.0
--------------------------------------------
-
-BEOPEN PYTHON OPEN SOURCE LICENSE AGREEMENT VERSION 1
-
-1. This LICENSE AGREEMENT is between BeOpen.com ("BeOpen"), having an
-office at 160 Saratoga Avenue, Santa Clara, CA 95051, and the
-Individual or Organization ("Licensee") accessing and otherwise using
-this software in source or binary form and its associated
-documentation ("the Software").
-
-2. Subject to the terms and conditions of this BeOpen Python License
-Agreement, BeOpen hereby grants Licensee a non-exclusive,
-royalty-free, world-wide license to reproduce, analyze, test, perform
-and/or display publicly, prepare derivative works, distribute, and
-otherwise use the Software alone or in any derivative version,
-provided, however, that the BeOpen Python License is retained in the
-Software, alone or in any derivative version prepared by Licensee.
-
-3. BeOpen is making the Software available to Licensee on an "AS IS"
-basis. BEOPEN MAKES NO REPRESENTATIONS OR WARRANTIES, EXPRESS OR
-IMPLIED. BY WAY OF EXAMPLE, BUT NOT LIMITATION, BEOPEN MAKES NO AND
-DISCLAIMS ANY REPRESENTATION OR WARRANTY OF MERCHANTABILITY OR FITNESS
-FOR ANY PARTICULAR PURPOSE OR THAT THE USE OF THE SOFTWARE WILL NOT
-INFRINGE ANY THIRD PARTY RIGHTS.
-
-4. BEOPEN SHALL NOT BE LIABLE TO LICENSEE OR ANY OTHER USERS OF THE
-SOFTWARE FOR ANY INCIDENTAL, SPECIAL, OR CONSEQUENTIAL DAMAGES OR LOSS
-AS A RESULT OF USING, MODIFYING OR DISTRIBUTING THE SOFTWARE, OR ANY
-DERIVATIVE THEREOF, EVEN IF ADVISED OF THE POSSIBILITY THEREOF.
-
-5. This License Agreement will automatically terminate upon a material
-breach of its terms and conditions.
-
-6. This License Agreement shall be governed by and interpreted in all
-respects by the law of the State of California, excluding conflict of
-law provisions. Nothing in this License Agreement shall be deemed to
-create any relationship of agency, partnership, or joint venture
-between BeOpen and Licensee. This License Agreement does not grant
-permission to use BeOpen trademarks or trade names in a trademark
-sense to endorse or promote products or services of Licensee, or any
-third party. As an exception, the "BeOpen Python" logos available at
-http://www.pythonlabs.com/logos.html may be used according to the
-permissions granted on that web page.
-
-7. By copying, installing or otherwise using the software, Licensee
-agrees to be bound by the terms and conditions of this License
-Agreement.
-
-
-CNRI LICENSE AGREEMENT FOR PYTHON 1.6.1
----------------------------------------
-
-1. This LICENSE AGREEMENT is between the Corporation for National
-Research Initiatives, having an office at 1895 Preston White Drive,
-Reston, VA 20191 ("CNRI"), and the Individual or Organization
-("Licensee") accessing and otherwise using Python 1.6.1 software in
-source or binary form and its associated documentation.
-
-2. Subject to the terms and conditions of this License Agreement, CNRI
-hereby grants Licensee a nonexclusive, royalty-free, world-wide
-license to reproduce, analyze, test, perform and/or display publicly,
-prepare derivative works, distribute, and otherwise use Python 1.6.1
-alone or in any derivative version, provided, however, that CNRI's
-License Agreement and CNRI's notice of copyright, i.e., "Copyright (c)
-1995-2001 Corporation for National Research Initiatives; All Rights
-Reserved" are retained in Python 1.6.1 alone or in any derivative
-version prepared by Licensee. Alternately, in lieu of CNRI's License
-Agreement, Licensee may substitute the following text (omitting the
-quotes): "Python 1.6.1 is made available subject to the terms and
-conditions in CNRI's License Agreement. This Agreement together with
-Python 1.6.1 may be located on the Internet using the following
-unique, persistent identifier (known as a handle): 1895.22/1013. This
-Agreement may also be obtained from a proxy server on the Internet
-using the following URL: http://hdl.handle.net/1895.22/1013".
-
-3. In the event Licensee prepares a derivative work that is based on
-or incorporates Python 1.6.1 or any part thereof, and wants to make
-the derivative work available to others as provided herein, then
-Licensee hereby agrees to include in any such work a brief summary of
-the changes made to Python 1.6.1.
-
-4. CNRI is making Python 1.6.1 available to Licensee on an "AS IS"
-basis. CNRI MAKES NO REPRESENTATIONS OR WARRANTIES, EXPRESS OR
-IMPLIED. BY WAY OF EXAMPLE, BUT NOT LIMITATION, CNRI MAKES NO AND
-DISCLAIMS ANY REPRESENTATION OR WARRANTY OF MERCHANTABILITY OR FITNESS
-FOR ANY PARTICULAR PURPOSE OR THAT THE USE OF PYTHON 1.6.1 WILL NOT
-INFRINGE ANY THIRD PARTY RIGHTS.
-
-5. CNRI SHALL NOT BE LIABLE TO LICENSEE OR ANY OTHER USERS OF PYTHON
-1.6.1 FOR ANY INCIDENTAL, SPECIAL, OR CONSEQUENTIAL DAMAGES OR LOSS AS
-A RESULT OF MODIFYING, DISTRIBUTING, OR OTHERWISE USING PYTHON 1.6.1,
-OR ANY DERIVATIVE THEREOF, EVEN IF ADVISED OF THE POSSIBILITY THEREOF.
-
-6. This License Agreement will automatically terminate upon a material
-breach of its terms and conditions.
-
-7. This License Agreement shall be governed by the federal
-intellectual property law of the United States, including without
-limitation the federal copyright law, and, to the extent such
-U.S. federal law does not apply, by the law of the Commonwealth of
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-Notwithstanding the foregoing, with regard to derivative works based
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-installing or otherwise using Python 1.6.1, Licensee agrees to be
-bound by the terms and conditions of this License Agreement.
-
- ACCEPT
-
-
-CWI LICENSE AGREEMENT FOR PYTHON 0.9.0 THROUGH 1.2
---------------------------------------------------
-
-Copyright (c) 1991 - 1995, Stichting Mathematisch Centrum Amsterdam,
-The Netherlands. All rights reserved.
-
-Permission to use, copy, modify, and distribute this software and its
-documentation for any purpose and without fee is hereby granted,
-provided that the above copyright notice appear in all copies and that
-both that copyright notice and this permission notice appear in
-supporting documentation, and that the name of Stichting Mathematisch
-Centrum or CWI not be used in advertising or publicity pertaining to
-distribution of the software without specific, written prior
-permission.
-
-STICHTING MATHEMATISCH CENTRUM DISCLAIMS ALL WARRANTIES WITH REGARD TO
-THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND
-FITNESS, IN NO EVENT SHALL STICHTING MATHEMATISCH CENTRUM BE LIABLE
-FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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-OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
F: include/hw/display/vga.h
F: include/hw/display/bochs-vbe.h
+ramfb
+M: Gerd Hoffmann <kraxel@redhat.com>
+S: Maintained
+F: hw/display/ramfb*.c
+F: include/hw/display/ramfb.h
+
virtio-gpu
M: Gerd Hoffmann <kraxel@redhat.com>
S: Maintained
EOF
virgl_cflags=$($pkg_config --cflags virglrenderer 2>/dev/null)
virgl_libs=$($pkg_config --libs virglrenderer 2>/dev/null)
+ virgl_version=$($pkg_config --modversion virglrenderer 2>/dev/null)
if $pkg_config virglrenderer >/dev/null 2>&1 && \
compile_prog "$virgl_cflags" "$virgl_libs" ; then
virglrenderer="yes"
echo "nettle kdf $nettle_kdf"
echo "libtasn1 $tasn1"
echo "curses support $curses"
-echo "virgl support $virglrenderer"
+echo "virgl support $virglrenderer $(echo_version $virglrenderer $virgl_version)"
echo "curl support $curl"
echo "mingw32 support $mingw32"
echo "Audio drivers $audio_drv_list"
done
# set up tests data directory
-if [ ! -e tests/data ]; then
- symlink "$source_path/tests/data" tests/data
-fi
+for tests_subdir in acceptance data; do
+ if [ ! -e tests/$tests_subdir ]; then
+ symlink "$source_path/tests/$tests_subdir" tests/$tests_subdir
+ fi
+done
# set up qemu-iotests in this build directory
iotests_common_env="tests/qemu-iotests/common.env"
CONFIG_MAC=y
CONFIG_ESCC=y
CONFIG_MACIO=y
+CONFIG_MACIO_GPIO=y
CONFIG_SUNGEM=y
CONFIG_MOS6522=y
CONFIG_CUDA=y
CONFIG_ADB=y
CONFIG_MAC_NVRAM=y
CONFIG_MAC_DBDMA=y
+CONFIG_MAC_PMU=y
CONFIG_HEATHROW_PIC=y
CONFIG_GRACKLE_PCI=y
CONFIG_UNIN_PCI=y
Alternatively, some command different from "qemu-img info" can be tested, by
changing the ``-c`` option.
+
+Acceptance tests using the Avocado Framework
+============================================
+
+The ``tests/acceptance`` directory hosts functional tests, also known
+as acceptance level tests. They're usually higher level tests, and
+may interact with external resources and with various guest operating
+systems.
+
+These tests are written using the Avocado Testing Framework (which must
+be installed separately) in conjunction with a the ``avocado_qemu.Test``
+class, implemented at ``tests/acceptance/avocado_qemu``.
+
+Tests based on ``avocado_qemu.Test`` can easily:
+
+ * Customize the command line arguments given to the convenience
+ ``self.vm`` attribute (a QEMUMachine instance)
+
+ * Interact with the QEMU monitor, send QMP commands and check
+ their results
+
+ * Interact with the guest OS, using the convenience console device
+ (which may be useful to assert the effectiveness and correctness of
+ command line arguments or QMP commands)
+
+ * Interact with external data files that accompany the test itself
+ (see ``self.get_data()``)
+
+ * Download (and cache) remote data files, such as firmware and kernel
+ images
+
+ * Have access to a library of guest OS images (by means of the
+ ``avocado.utils.vmimage`` library)
+
+ * Make use of various other test related utilities available at the
+ test class itself and at the utility library:
+
+ - http://avocado-framework.readthedocs.io/en/latest/api/test/avocado.html#avocado.Test
+ - http://avocado-framework.readthedocs.io/en/latest/api/utils/avocado.utils.html
+
+Installation
+------------
+
+To install Avocado and its dependencies, run:
+
+.. code::
+
+ pip install --user avocado-framework
+
+Alternatively, follow the instructions on this link:
+
+ http://avocado-framework.readthedocs.io/en/latest/GetStartedGuide.html#installing-avocado
+
+Overview
+--------
+
+This directory provides the ``avocado_qemu`` Python module, containing
+the ``avocado_qemu.Test`` class. Here's a simple usage example:
+
+.. code::
+
+ from avocado_qemu import Test
+
+
+ class Version(Test):
+ """
+ :avocado: enable
+ :avocado: tags=quick
+ """
+ def test_qmp_human_info_version(self):
+ self.vm.launch()
+ res = self.vm.command('human-monitor-command',
+ command_line='info version')
+ self.assertRegexpMatches(res, r'^(\d+\.\d+\.\d)')
+
+To execute your test, run:
+
+.. code::
+
+ avocado run version.py
+
+Tests may be classified according to a convention by using docstring
+directives such as ``:avocado: tags=TAG1,TAG2``. To run all tests
+in the current directory, tagged as "quick", run:
+
+.. code::
+
+ avocado run -t quick .
+
+The ``avocado_qemu.Test`` base test class
+-----------------------------------------
+
+The ``avocado_qemu.Test`` class has a number of characteristics that
+are worth being mentioned right away.
+
+First of all, it attempts to give each test a ready to use QEMUMachine
+instance, available at ``self.vm``. Because many tests will tweak the
+QEMU command line, launching the QEMUMachine (by using ``self.vm.launch()``)
+is left to the test writer.
+
+At test "tear down", ``avocado_qemu.Test`` handles the QEMUMachine
+shutdown.
+
+QEMUMachine
+~~~~~~~~~~~
+
+The QEMUMachine API is already widely used in the Python iotests,
+device-crash-test and other Python scripts. It's a wrapper around the
+execution of a QEMU binary, giving its users:
+
+ * the ability to set command line arguments to be given to the QEMU
+ binary
+
+ * a ready to use QMP connection and interface, which can be used to
+ send commands and inspect its results, as well as asynchronous
+ events
+
+ * convenience methods to set commonly used command line arguments in
+ a more succinct and intuitive way
+
+QEMU binary selection
+~~~~~~~~~~~~~~~~~~~~~
+
+The QEMU binary used for the ``self.vm`` QEMUMachine instance will
+primarily depend on the value of the ``qemu_bin`` parameter. If it's
+not explicitly set, its default value will be the result of a dynamic
+probe in the same source tree. A suitable binary will be one that
+targets the architecture matching host machine.
+
+Based on this description, test writers will usually rely on one of
+the following approaches:
+
+1) Set ``qemu_bin``, and use the given binary
+
+2) Do not set ``qemu_bin``, and use a QEMU binary named like
+ "${arch}-softmmu/qemu-system-${arch}", either in the current
+ working directory, or in the current source tree.
+
+The resulting ``qemu_bin`` value will be preserved in the
+``avocado_qemu.Test`` as an attribute with the same name.
+
+Attribute reference
+-------------------
+
+Besides the attributes and methods that are part of the base
+``avocado.Test`` class, the following attributes are available on any
+``avocado_qemu.Test`` instance.
+
+vm
+~~
+
+A QEMUMachine instance, initially configured according to the given
+``qemu_bin`` parameter.
+
+qemu_bin
+~~~~~~~~
+
+The preserved value of the ``qemu_bin`` parameter or the result of the
+dynamic probe for a QEMU binary in the current working directory or
+source tree.
+
+Parameter reference
+-------------------
+
+To understand how Avocado parameters are accessed by tests, and how
+they can be passed to tests, please refer to::
+
+ http://avocado-framework.readthedocs.io/en/latest/WritingTests.html#accessing-test-parameters
+
+Parameter values can be easily seen in the log files, and will look
+like the following:
+
+.. code::
+
+ PARAMS (key=qemu_bin, path=*, default=x86_64-softmmu/qemu-system-x86_64) => 'x86_64-softmmu/qemu-system-x86_64
+
+qemu_bin
+~~~~~~~~
+
+The exact QEMU binary to be used on QEMUMachine.
+
+Uninstalling Avocado
+--------------------
+
+If you've followed the installation instructions above, you can easily
+uninstall Avocado. Start by listing the packages you have installed::
+
+ pip list --user
+
+And remove any package you want with::
+
+ pip uninstall <package_name>
#include "hw/vfio/vfio-platform.h"
#include "hw/vfio/vfio-calxeda-xgmac.h"
#include "hw/vfio/vfio-amd-xgbe.h"
+#include "hw/display/ramfb.h"
#include "hw/arm/fdt.h"
/*
#endif /* CONFIG_LINUX */
+static int no_fdt_node(SysBusDevice *sbdev, void *opaque)
+{
+ return 0;
+}
+
/* list of supported dynamic sysbus devices */
static const NodeCreationPair add_fdt_node_functions[] = {
#ifdef CONFIG_LINUX
{TYPE_VFIO_CALXEDA_XGMAC, add_calxeda_midway_xgmac_fdt_node},
{TYPE_VFIO_AMD_XGBE, add_amd_xgbe_fdt_node},
#endif
+ {TYPE_RAMFB_DEVICE, no_fdt_node},
{"", NULL}, /* last element */
};
#include "hw/arm/virt.h"
#include "hw/vfio/vfio-calxeda-xgmac.h"
#include "hw/vfio/vfio-amd-xgbe.h"
+#include "hw/display/ramfb.h"
#include "hw/devices.h"
#include "net/net.h"
#include "sysemu/device_tree.h"
mc->max_cpus = 255;
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC);
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE);
+ machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
mc->block_default_type = IF_VIRTIO;
mc->no_cdrom = 1;
mc->pci_allow_0_address = true;
QLIST_INSERT_HEAD(&bus->parent->child_bus, bus, sibling);
bus->parent->num_child_bus++;
object_property_add_child(OBJECT(bus->parent), bus->name, OBJECT(bus), NULL);
+ object_unref(OBJECT(bus));
} else if (bus != sysbus_get_default()) {
/* TODO: once all bus devices are qdevified,
only reset handler for main_system_bus should be registered here. */
+common-obj-y += ramfb.o
+common-obj-y += ramfb-standalone.o
+
common-obj-$(CONFIG_ADS7846) += ads7846.o
common-obj-$(CONFIG_VGA_CIRRUS) += cirrus_vga.o
common-obj-$(CONFIG_G364FB) += g364fb.o
--- /dev/null
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/loader.h"
+#include "hw/isa/isa.h"
+#include "hw/display/ramfb.h"
+#include "ui/console.h"
+#include "sysemu/sysemu.h"
+
+#define RAMFB(obj) OBJECT_CHECK(RAMFBStandaloneState, (obj), TYPE_RAMFB_DEVICE)
+
+typedef struct RAMFBStandaloneState {
+ SysBusDevice parent_obj;
+ QemuConsole *con;
+ RAMFBState *state;
+} RAMFBStandaloneState;
+
+static void display_update_wrapper(void *dev)
+{
+ RAMFBStandaloneState *ramfb = RAMFB(dev);
+
+ if (0 /* native driver active */) {
+ /* non-standalone device would run native display update here */;
+ } else {
+ ramfb_display_update(ramfb->con, ramfb->state);
+ }
+}
+
+static const GraphicHwOps wrapper_ops = {
+ .gfx_update = display_update_wrapper,
+};
+
+static void ramfb_realizefn(DeviceState *dev, Error **errp)
+{
+ RAMFBStandaloneState *ramfb = RAMFB(dev);
+
+ ramfb->con = graphic_console_init(dev, 0, &wrapper_ops, dev);
+ ramfb->state = ramfb_setup(errp);
+}
+
+static void ramfb_class_initfn(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
+ dc->realize = ramfb_realizefn;
+ dc->desc = "ram framebuffer standalone device";
+ dc->user_creatable = true;
+}
+
+static const TypeInfo ramfb_info = {
+ .name = TYPE_RAMFB_DEVICE,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(RAMFBStandaloneState),
+ .class_init = ramfb_class_initfn,
+};
+
+static void ramfb_register_types(void)
+{
+ type_register_static(&ramfb_info);
+}
+
+type_init(ramfb_register_types)
--- /dev/null
+/*
+ * early boot framebuffer in guest ram
+ * configured using fw_cfg
+ *
+ * Copyright Red Hat, Inc. 2017
+ *
+ * Author:
+ * Gerd Hoffmann <kraxel@redhat.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/loader.h"
+#include "hw/display/ramfb.h"
+#include "ui/console.h"
+#include "sysemu/sysemu.h"
+
+struct QEMU_PACKED RAMFBCfg {
+ uint64_t addr;
+ uint32_t fourcc;
+ uint32_t flags;
+ uint32_t width;
+ uint32_t height;
+ uint32_t stride;
+};
+
+struct RAMFBState {
+ DisplaySurface *ds;
+ uint32_t width, height;
+ struct RAMFBCfg cfg;
+};
+
+static void ramfb_fw_cfg_write(void *dev, off_t offset, size_t len)
+{
+ RAMFBState *s = dev;
+ void *framebuffer;
+ uint32_t stride, fourcc, format;
+ hwaddr addr, length;
+
+ s->width = be32_to_cpu(s->cfg.width);
+ s->height = be32_to_cpu(s->cfg.height);
+ stride = be32_to_cpu(s->cfg.stride);
+ fourcc = be32_to_cpu(s->cfg.fourcc);
+ addr = be64_to_cpu(s->cfg.addr);
+ length = stride * s->height;
+ format = qemu_drm_format_to_pixman(fourcc);
+
+ fprintf(stderr, "%s: %dx%d @ 0x%" PRIx64 "\n", __func__,
+ s->width, s->height, addr);
+ framebuffer = address_space_map(&address_space_memory,
+ addr, &length, false,
+ MEMTXATTRS_UNSPECIFIED);
+ if (!framebuffer || length < stride * s->height) {
+ s->width = 0;
+ s->height = 0;
+ return;
+ }
+ s->ds = qemu_create_displaysurface_from(s->width, s->height,
+ format, stride, framebuffer);
+}
+
+void ramfb_display_update(QemuConsole *con, RAMFBState *s)
+{
+ if (!s->width || !s->height) {
+ return;
+ }
+
+ if (s->ds) {
+ dpy_gfx_replace_surface(con, s->ds);
+ s->ds = NULL;
+ }
+
+ /* simple full screen update */
+ dpy_gfx_update_full(con);
+}
+
+RAMFBState *ramfb_setup(Error **errp)
+{
+ FWCfgState *fw_cfg = fw_cfg_find();
+ RAMFBState *s;
+
+ if (!fw_cfg || !fw_cfg->dma_enabled) {
+ error_setg(errp, "ramfb device requires fw_cfg with DMA");
+ return NULL;
+ }
+
+ s = g_new0(RAMFBState, 1);
+
+ fw_cfg_add_file_callback(fw_cfg, "etc/ramfb",
+ NULL, ramfb_fw_cfg_write, s,
+ &s->cfg, sizeof(s->cfg), false);
+ return s;
+}
switch (addr) {
case SM501_SYSTEM_CONTROL:
- s->system_control = value & 0xE300B8F7;
+ s->system_control &= 0x10DB0000;
+ s->system_control |= value & 0xEF00B8F7;
break;
case SM501_MISC_CONTROL:
- s->misc_control = value & 0xFF7FFF20;
+ s->misc_control &= 0xEF;
+ s->misc_control |= value & 0xFF7FFF10;
break;
case SM501_GPIO31_0_CONTROL:
s->gpio_31_0_control = value;
break;
case SM501_GPIO63_32_CONTROL:
- s->gpio_63_32_control = value;
+ s->gpio_63_32_control = value & 0xFF80FFFF;
break;
case SM501_DRAM_CONTROL:
s->local_mem_size_index = (value >> 13) & 0x7;
/* TODO : check validity of size change */
- s->dram_control |= value & 0x7FFFFFC3;
+ s->dram_control &= 0x80000000;
+ s->dram_control |= value & 0x7FFFFFC3;
break;
case SM501_ARBTRTN_CONTROL:
- s->arbitration_control = value & 0x37777777;
+ s->arbitration_control = value & 0x37777777;
break;
case SM501_IRQ_MASK:
- s->irq_mask = value;
+ s->irq_mask = value & 0xFFDF3F5F;
break;
case SM501_MISC_TIMING:
s->misc_timing = value & 0xF31F1FFF;
#include "hw/loader.h"
#include "hw/i386/pc.h"
#include "hw/i386/apic.h"
+#include "hw/display/ramfb.h"
#include "hw/smbios/smbios.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_ids.h"
m->desc = "Standard PC (i440FX + PIIX, 1996)";
m->default_machine_opts = "firmware=bios-256k.bin";
m->default_display = "std";
+ machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE);
}
static void pc_i440fx_3_0_machine_options(MachineClass *m)
#include "hw/i386/ich9.h"
#include "hw/i386/amd_iommu.h"
#include "hw/i386/intel_iommu.h"
+#include "hw/display/ramfb.h"
#include "hw/smbios/smbios.h"
#include "hw/ide/pci.h"
#include "hw/ide/ahci.h"
m->no_floppy = 1;
machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE);
machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE);
+ machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE);
m->max_cpus = 288;
}
trace_adb_kbd_request_change_addr(d->devaddr);
break;
default:
- d->devaddr = buf[1] & 0xf;
- /* we support handlers:
- * 1: Apple Standard Keyboard
- * 2: Apple Extended Keyboard (LShift = RShift)
- * 3: Apple Extended Keyboard (LShift != RShift)
- */
- if (buf[2] == 1 || buf[2] == 2 || buf[2] == 3) {
- d->handler = buf[2];
+ if (!d->disable_direct_reg3_writes) {
+ d->devaddr = buf[1] & 0xf;
+
+ /* we support handlers:
+ * 1: Apple Standard Keyboard
+ * 2: Apple Extended Keyboard (LShift = RShift)
+ * 3: Apple Extended Keyboard (LShift != RShift)
+ */
+ if (buf[2] == 1 || buf[2] == 2 || buf[2] == 3) {
+ d->handler = buf[2];
+ }
+
+ trace_adb_kbd_request_change_addr_and_handler(d->devaddr,
+ d->handler);
}
-
- trace_adb_kbd_request_change_addr_and_handler(d->devaddr,
- d->handler);
break;
}
}
olen = 2;
break;
case 3:
- obuf[0] = d->handler;
- obuf[1] = d->devaddr;
+ obuf[0] = d->devaddr;
+ obuf[1] = d->handler;
olen = 2;
break;
}
trace_adb_mouse_request_change_addr(d->devaddr);
break;
default:
- d->devaddr = buf[1] & 0xf;
- /* we support handlers:
- * 0x01: Classic Apple Mouse Protocol / 100 cpi operations
- * 0x02: Classic Apple Mouse Protocol / 200 cpi operations
- * we don't support handlers (at least):
- * 0x03: Mouse systems A3 trackball
- * 0x04: Extended Apple Mouse Protocol
- * 0x2f: Microspeed mouse
- * 0x42: Macally
- * 0x5f: Microspeed mouse
- * 0x66: Microspeed mouse
- */
- if (buf[2] == 1 || buf[2] == 2) {
- d->handler = buf[2];
+ if (!d->disable_direct_reg3_writes) {
+ d->devaddr = buf[1] & 0xf;
+
+ /* we support handlers:
+ * 0x01: Classic Apple Mouse Protocol / 100 cpi operations
+ * 0x02: Classic Apple Mouse Protocol / 200 cpi operations
+ * we don't support handlers (at least):
+ * 0x03: Mouse systems A3 trackball
+ * 0x04: Extended Apple Mouse Protocol
+ * 0x2f: Microspeed mouse
+ * 0x42: Macally
+ * 0x5f: Microspeed mouse
+ * 0x66: Microspeed mouse
+ */
+ if (buf[2] == 1 || buf[2] == 2) {
+ d->handler = buf[2];
+ }
+
+ trace_adb_mouse_request_change_addr_and_handler(
+ d->devaddr, d->handler);
}
-
- trace_adb_mouse_request_change_addr_and_handler(d->devaddr,
- d->handler);
break;
}
}
case 1:
break;
case 3:
- obuf[0] = d->handler;
- obuf[1] = d->devaddr;
+ obuf[0] = d->devaddr;
+ obuf[1] = d->handler;
olen = 2;
break;
}
bus->devices[bus->nb_devices++] = d;
}
+static Property adb_device_properties[] = {
+ DEFINE_PROP_BOOL("disable-direct-reg3-writes", ADBDevice,
+ disable_direct_reg3_writes, false),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void adb_device_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
dc->realize = adb_device_realizefn;
+ dc->props = adb_device_properties;
dc->bus_type = TYPE_ADB_BUS;
}
kvm_device_access(kernel_xics_fd, KVM_DEV_XICS_GRP_SOURCES,
i + ics->offset, &state, false, &local_err);
if (local_err) {
- error_report("Unable to retrieve KVM interrupt controller state"
- " for IRQ %d: %s", i + ics->offset, strerror(errno));
+ error_report_err(local_err);
exit(1);
}
state |= KVM_XICS_QUEUED;
}
- kvm_device_access(kernel_xics_fd, KVM_DEV_XICS_GRP_SOURCES,
- i + ics->offset, &state, true, &local_err);
+ ret = kvm_device_access(kernel_xics_fd, KVM_DEV_XICS_GRP_SOURCES,
+ i + ics->offset, &state, true, &local_err);
if (local_err) {
- error_report("Unable to restore KVM interrupt controller state"
- " for IRQs %d: %s", i + ics->offset, strerror(errno));
+ error_report_err(local_err);
return ret;
}
}
common-obj-y += macio.o
common-obj-$(CONFIG_CUDA) += cuda.o
+common-obj-$(CONFIG_MAC_PMU) += pmu.o
common-obj-$(CONFIG_MAC_DBDMA) += mac_dbdma.o
+common-obj-$(CONFIG_MACIO_GPIO) += gpio.o
--- /dev/null
+/*
+ * PowerMac NewWorld MacIO GPIO emulation
+ *
+ * Copyright (c) 2016 Benjamin Herrenschmidt
+ * Copyright (c) 2018 Mark Cave-Ayland
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/hw.h"
+#include "hw/ppc/mac.h"
+#include "hw/misc/macio/macio.h"
+#include "hw/misc/macio/gpio.h"
+#include "hw/nmi.h"
+#include "qemu/log.h"
+#include "trace.h"
+
+
+void macio_set_gpio(MacIOGPIOState *s, uint32_t gpio, bool state)
+{
+ uint8_t new_reg;
+
+ trace_macio_set_gpio(gpio, state);
+
+ if (s->gpio_regs[gpio] & 4) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "GPIO: Setting GPIO %d while it's an output\n", gpio);
+ }
+
+ new_reg = s->gpio_regs[gpio] & ~2;
+ if (state) {
+ new_reg |= 2;
+ }
+
+ if (new_reg == s->gpio_regs[gpio]) {
+ return;
+ }
+
+ s->gpio_regs[gpio] = new_reg;
+
+ /* This is will work until we fix the binding between MacIO and
+ * the MPIC properly so we can route all GPIOs and avoid going
+ * via the top level platform code.
+ *
+ * Note that we probably need to get access to the MPIC config to
+ * decode polarity since qemu always use "raise" regardless.
+ *
+ * For now, we hard wire known GPIOs
+ */
+
+ switch (gpio) {
+ case 1:
+ /* Level low */
+ if (!state) {
+ trace_macio_gpio_irq_assert(gpio);
+ qemu_irq_raise(s->gpio_extirqs[gpio]);
+ } else {
+ trace_macio_gpio_irq_deassert(gpio);
+ qemu_irq_lower(s->gpio_extirqs[gpio]);
+ }
+ break;
+
+ case 9:
+ /* Edge, triggered by NMI below */
+ if (state) {
+ trace_macio_gpio_irq_assert(gpio);
+ qemu_irq_raise(s->gpio_extirqs[gpio]);
+ } else {
+ trace_macio_gpio_irq_deassert(gpio);
+ qemu_irq_lower(s->gpio_extirqs[gpio]);
+ }
+ break;
+
+ default:
+ qemu_log_mask(LOG_UNIMP, "GPIO: setting unimplemented GPIO %d", gpio);
+ }
+}
+
+static void macio_gpio_write(void *opaque, hwaddr addr, uint64_t value,
+ unsigned size)
+{
+ MacIOGPIOState *s = opaque;
+ uint8_t ibit;
+
+ trace_macio_gpio_write(addr, value);
+
+ /* Levels regs are read-only */
+ if (addr < 8) {
+ return;
+ }
+
+ addr -= 8;
+ if (addr < 36) {
+ value &= ~2;
+
+ if (value & 4) {
+ ibit = (value & 1) << 1;
+ } else {
+ ibit = s->gpio_regs[addr] & 2;
+ }
+
+ s->gpio_regs[addr] = value | ibit;
+ }
+}
+
+static uint64_t macio_gpio_read(void *opaque, hwaddr addr, unsigned size)
+{
+ MacIOGPIOState *s = opaque;
+ uint64_t val = 0;
+
+ /* Levels regs */
+ if (addr < 8) {
+ val = s->gpio_levels[addr];
+ } else {
+ addr -= 8;
+
+ if (addr < 36) {
+ val = s->gpio_regs[addr];
+ }
+ }
+
+ trace_macio_gpio_write(addr, val);
+ return val;
+}
+
+static const MemoryRegionOps macio_gpio_ops = {
+ .read = macio_gpio_read,
+ .write = macio_gpio_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
+};
+
+static void macio_gpio_realize(DeviceState *dev, Error **errp)
+{
+ MacIOGPIOState *s = MACIO_GPIO(dev);
+
+ s->gpio_extirqs[1] = qdev_get_gpio_in(DEVICE(s->pic),
+ NEWWORLD_EXTING_GPIO1);
+ s->gpio_extirqs[9] = qdev_get_gpio_in(DEVICE(s->pic),
+ NEWWORLD_EXTING_GPIO9);
+}
+
+static void macio_gpio_init(Object *obj)
+{
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ MacIOGPIOState *s = MACIO_GPIO(obj);
+
+ object_property_add_link(obj, "pic", TYPE_OPENPIC,
+ (Object **) &s->pic,
+ qdev_prop_allow_set_link_before_realize,
+ 0, NULL);
+
+ memory_region_init_io(&s->gpiomem, OBJECT(s), &macio_gpio_ops, obj,
+ "gpio", 0x30);
+ sysbus_init_mmio(sbd, &s->gpiomem);
+}
+
+static const VMStateDescription vmstate_macio_gpio = {
+ .name = "macio_gpio",
+ .version_id = 0,
+ .minimum_version_id = 0,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT8_ARRAY(gpio_levels, MacIOGPIOState, 8),
+ VMSTATE_UINT8_ARRAY(gpio_regs, MacIOGPIOState, 36),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void macio_gpio_reset(DeviceState *dev)
+{
+ MacIOGPIOState *s = MACIO_GPIO(dev);
+
+ /* GPIO 1 is up by default */
+ macio_set_gpio(s, 1, true);
+}
+
+static void macio_gpio_nmi(NMIState *n, int cpu_index, Error **errp)
+{
+ macio_set_gpio(MACIO_GPIO(n), 9, true);
+ macio_set_gpio(MACIO_GPIO(n), 9, false);
+}
+
+static void macio_gpio_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ NMIClass *nc = NMI_CLASS(oc);
+
+ dc->realize = macio_gpio_realize;
+ dc->reset = macio_gpio_reset;
+ dc->vmsd = &vmstate_macio_gpio;
+ nc->nmi_monitor_handler = macio_gpio_nmi;
+}
+
+static const TypeInfo macio_gpio_init_info = {
+ .name = TYPE_MACIO_GPIO,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(MacIOGPIOState),
+ .instance_init = macio_gpio_init,
+ .class_init = macio_gpio_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { TYPE_NMI },
+ { }
+ },
+};
+
+static void macio_gpio_register_types(void)
+{
+ type_register_static(&macio_gpio_init_info);
+}
+
+type_init(macio_gpio_register_types)
memory_region_add_subregion(&s->bar, 0x08000,
sysbus_mmio_get_region(sysbus_dev, 0));
- qdev_prop_set_uint64(DEVICE(&s->cuda), "timebase-frequency",
- s->frequency);
- object_property_set_bool(OBJECT(&s->cuda), true, "realized", &err);
- if (err) {
- error_propagate(errp, err);
- return;
- }
- sysbus_dev = SYS_BUS_DEVICE(&s->cuda);
- memory_region_add_subregion(&s->bar, 0x16000,
- sysbus_mmio_get_region(sysbus_dev, 0));
-
qdev_prop_set_uint32(DEVICE(&s->escc), "disabled", 0);
qdev_prop_set_uint32(DEVICE(&s->escc), "frequency", ESCC_CLOCK);
qdev_prop_set_uint32(DEVICE(&s->escc), "it_shift", 4);
return;
}
+ qdev_prop_set_uint64(DEVICE(&s->cuda), "timebase-frequency",
+ s->frequency);
+ object_property_set_bool(OBJECT(&s->cuda), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
sysbus_dev = SYS_BUS_DEVICE(&s->cuda);
+ memory_region_add_subregion(&s->bar, 0x16000,
+ sysbus_mmio_get_region(sysbus_dev, 0));
sysbus_connect_irq(sysbus_dev, 0, qdev_get_gpio_in(pic_dev,
OLDWORLD_CUDA_IRQ));
qdev_prop_allow_set_link_before_realize,
0, NULL);
+ object_initialize(&s->cuda, sizeof(s->cuda), TYPE_CUDA);
+ qdev_set_parent_bus(DEVICE(&s->cuda), sysbus_get_default());
+ object_property_add_child(obj, "cuda", OBJECT(&s->cuda), NULL);
+
object_initialize(&os->nvram, sizeof(os->nvram), TYPE_MACIO_NVRAM);
dev = DEVICE(&os->nvram);
qdev_prop_set_uint32(dev, "size", 0x2000);
return;
}
- sysbus_dev = SYS_BUS_DEVICE(&s->cuda);
- sysbus_connect_irq(sysbus_dev, 0, qdev_get_gpio_in(pic_dev,
- NEWWORLD_CUDA_IRQ));
-
sysbus_dev = SYS_BUS_DEVICE(&s->escc);
sysbus_connect_irq(sysbus_dev, 0, qdev_get_gpio_in(pic_dev,
NEWWORLD_ESCCB_IRQ));
memory_region_init_io(timer_memory, OBJECT(s), &timer_ops, NULL, "timer",
0x1000);
memory_region_add_subregion(&s->bar, 0x15000, timer_memory);
+
+ if (ns->has_pmu) {
+ /* GPIOs */
+ sysbus_dev = SYS_BUS_DEVICE(&ns->gpio);
+ object_property_set_link(OBJECT(&ns->gpio), OBJECT(pic_dev), "pic",
+ &error_abort);
+ memory_region_add_subregion(&s->bar, 0x50,
+ sysbus_mmio_get_region(sysbus_dev, 0));
+ object_property_set_bool(OBJECT(&ns->gpio), true, "realized", &err);
+
+ /* PMU */
+ object_initialize(&s->pmu, sizeof(s->pmu), TYPE_VIA_PMU);
+ object_property_set_link(OBJECT(&s->pmu), OBJECT(sysbus_dev), "gpio",
+ &error_abort);
+ qdev_prop_set_bit(DEVICE(&s->pmu), "has-adb", ns->has_adb);
+ qdev_set_parent_bus(DEVICE(&s->pmu), sysbus_get_default());
+ object_property_add_child(OBJECT(s), "pmu", OBJECT(&s->pmu), NULL);
+
+ object_property_set_bool(OBJECT(&s->pmu), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ sysbus_dev = SYS_BUS_DEVICE(&s->pmu);
+ sysbus_connect_irq(sysbus_dev, 0, qdev_get_gpio_in(pic_dev,
+ NEWWORLD_PMU_IRQ));
+ memory_region_add_subregion(&s->bar, 0x16000,
+ sysbus_mmio_get_region(sysbus_dev, 0));
+ } else {
+ /* CUDA */
+ object_initialize(&s->cuda, sizeof(s->cuda), TYPE_CUDA);
+ qdev_set_parent_bus(DEVICE(&s->cuda), sysbus_get_default());
+ object_property_add_child(OBJECT(s), "cuda", OBJECT(&s->cuda), NULL);
+ qdev_prop_set_uint64(DEVICE(&s->cuda), "timebase-frequency",
+ s->frequency);
+
+ object_property_set_bool(OBJECT(&s->cuda), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ sysbus_dev = SYS_BUS_DEVICE(&s->cuda);
+ sysbus_connect_irq(sysbus_dev, 0, qdev_get_gpio_in(pic_dev,
+ NEWWORLD_CUDA_IRQ));
+ memory_region_add_subregion(&s->bar, 0x16000,
+ sysbus_mmio_get_region(sysbus_dev, 0));
+ }
}
static void macio_newworld_init(Object *obj)
qdev_prop_allow_set_link_before_realize,
0, NULL);
+ object_initialize(&ns->gpio, sizeof(ns->gpio), TYPE_MACIO_GPIO);
+ qdev_set_parent_bus(DEVICE(&ns->gpio), sysbus_get_default());
+
for (i = 0; i < 2; i++) {
macio_init_ide(s, &ns->ide[i], sizeof(ns->ide[i]), i);
}
memory_region_init(&s->bar, obj, "macio", 0x80000);
- object_initialize(&s->cuda, sizeof(s->cuda), TYPE_CUDA);
- qdev_set_parent_bus(DEVICE(&s->cuda), sysbus_get_default());
- object_property_add_child(obj, "cuda", OBJECT(&s->cuda), NULL);
-
object_initialize(&s->dbdma, sizeof(s->dbdma), TYPE_MAC_DBDMA);
qdev_set_parent_bus(DEVICE(&s->dbdma), sysbus_get_default());
object_property_add_child(obj, "dbdma", OBJECT(&s->dbdma), NULL);
}
};
+static Property macio_newworld_properties[] = {
+ DEFINE_PROP_BOOL("has-pmu", NewWorldMacIOState, has_pmu, false),
+ DEFINE_PROP_BOOL("has-adb", NewWorldMacIOState, has_adb, false),
+ DEFINE_PROP_END_OF_LIST()
+};
+
static void macio_newworld_class_init(ObjectClass *oc, void *data)
{
PCIDeviceClass *pdc = PCI_DEVICE_CLASS(oc);
pdc->realize = macio_newworld_realize;
pdc->device_id = PCI_DEVICE_ID_APPLE_UNI_N_KEYL;
dc->vmsd = &vmstate_macio_newworld;
+ dc->props = macio_newworld_properties;
}
static Property macio_properties[] = {
--- /dev/null
+/*
+ * QEMU PowerMac PMU device support
+ *
+ * Copyright (c) 2016 Benjamin Herrenschmidt, IBM Corp.
+ * Copyright (c) 2018 Mark Cave-Ayland
+ *
+ * Based on the CUDA device by:
+ *
+ * Copyright (c) 2004-2007 Fabrice Bellard
+ * Copyright (c) 2007 Jocelyn Mayer
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/hw.h"
+#include "hw/ppc/mac.h"
+#include "hw/input/adb.h"
+#include "hw/misc/mos6522.h"
+#include "hw/misc/macio/gpio.h"
+#include "hw/misc/macio/pmu.h"
+#include "qemu/timer.h"
+#include "sysemu/sysemu.h"
+#include "qemu/cutils.h"
+#include "qemu/log.h"
+#include "trace.h"
+
+
+/* Bits in B data register: all active low */
+#define TACK 0x08 /* Transfer request (input) */
+#define TREQ 0x10 /* Transfer acknowledge (output) */
+
+/* PMU returns time_t's offset from Jan 1, 1904, not 1970 */
+#define RTC_OFFSET 2082844800
+
+#define VIA_TIMER_FREQ (4700000 / 6)
+
+static void via_update_irq(PMUState *s)
+{
+ MOS6522PMUState *mps = MOS6522_PMU(&s->mos6522_pmu);
+ MOS6522State *ms = MOS6522(mps);
+
+ bool new_state = !!(ms->ifr & ms->ier & (SR_INT | T1_INT | T2_INT));
+
+ if (new_state != s->via_irq_state) {
+ s->via_irq_state = new_state;
+ qemu_set_irq(s->via_irq, new_state);
+ }
+}
+
+static void via_set_sr_int(void *opaque)
+{
+ PMUState *s = opaque;
+ MOS6522PMUState *mps = MOS6522_PMU(&s->mos6522_pmu);
+ MOS6522State *ms = MOS6522(mps);
+ MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(ms);
+
+ mdc->set_sr_int(ms);
+}
+
+static void pmu_update_extirq(PMUState *s)
+{
+ if ((s->intbits & s->intmask) != 0) {
+ macio_set_gpio(s->gpio, 1, false);
+ } else {
+ macio_set_gpio(s->gpio, 1, true);
+ }
+}
+
+static void pmu_adb_poll(void *opaque)
+{
+ PMUState *s = opaque;
+ int olen;
+
+ if (!(s->intbits & PMU_INT_ADB)) {
+ olen = adb_poll(&s->adb_bus, s->adb_reply, s->adb_poll_mask);
+ trace_pmu_adb_poll(olen);
+
+ if (olen > 0) {
+ s->adb_reply_size = olen;
+ s->intbits |= PMU_INT_ADB | PMU_INT_ADB_AUTO;
+ pmu_update_extirq(s);
+ }
+ }
+
+ timer_mod(s->adb_poll_timer,
+ qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 30);
+}
+
+static void pmu_one_sec_timer(void *opaque)
+{
+ PMUState *s = opaque;
+
+ trace_pmu_one_sec_timer();
+
+ s->intbits |= PMU_INT_TICK;
+ pmu_update_extirq(s);
+ s->one_sec_target += 1000;
+
+ timer_mod(s->one_sec_timer, s->one_sec_target);
+}
+
+static void pmu_cmd_int_ack(PMUState *s,
+ const uint8_t *in_data, uint8_t in_len,
+ uint8_t *out_data, uint8_t *out_len)
+{
+ if (in_len != 0) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "PMU: INT_ACK command, invalid len: %d want: 0\n",
+ in_len);
+ return;
+ }
+
+ /* Make appropriate reply packet */
+ if (s->intbits & PMU_INT_ADB) {
+ if (!s->adb_reply_size) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Odd, PMU_INT_ADB set with no reply in buffer\n");
+ }
+
+ memcpy(out_data + 1, s->adb_reply, s->adb_reply_size);
+ out_data[0] = s->intbits & (PMU_INT_ADB | PMU_INT_ADB_AUTO);
+ *out_len = s->adb_reply_size + 1;
+ s->intbits &= ~(PMU_INT_ADB | PMU_INT_ADB_AUTO);
+ s->adb_reply_size = 0;
+ } else {
+ out_data[0] = s->intbits;
+ s->intbits = 0;
+ *out_len = 1;
+ }
+
+ pmu_update_extirq(s);
+}
+
+static void pmu_cmd_set_int_mask(PMUState *s,
+ const uint8_t *in_data, uint8_t in_len,
+ uint8_t *out_data, uint8_t *out_len)
+{
+ if (in_len != 1) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "PMU: SET_INT_MASK command, invalid len: %d want: 1\n",
+ in_len);
+ return;
+ }
+
+ trace_pmu_cmd_set_int_mask(s->intmask);
+ s->intmask = in_data[0];
+
+ pmu_update_extirq(s);
+}
+
+static void pmu_cmd_set_adb_autopoll(PMUState *s, uint16_t mask)
+{
+ trace_pmu_cmd_set_adb_autopoll(mask);
+
+ if (s->autopoll_mask == mask) {
+ return;
+ }
+
+ s->autopoll_mask = mask;
+ if (mask) {
+ timer_mod(s->adb_poll_timer,
+ qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 30);
+ } else {
+ timer_del(s->adb_poll_timer);
+ }
+}
+
+static void pmu_cmd_adb(PMUState *s,
+ const uint8_t *in_data, uint8_t in_len,
+ uint8_t *out_data, uint8_t *out_len)
+{
+ int len, adblen;
+ uint8_t adb_cmd[255];
+
+ if (in_len < 2) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "PMU: ADB PACKET, invalid len: %d want at least 2\n",
+ in_len);
+ return;
+ }
+
+ *out_len = 0;
+
+ if (!s->has_adb) {
+ trace_pmu_cmd_adb_nobus();
+ return;
+ }
+
+ /* Set autopoll is a special form of the command */
+ if (in_data[0] == 0 && in_data[1] == 0x86) {
+ uint16_t mask = in_data[2];
+ mask = (mask << 8) | in_data[3];
+ if (in_len != 4) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "PMU: ADB Autopoll requires 4 bytes, got %d\n",
+ in_len);
+ return;
+ }
+
+ pmu_cmd_set_adb_autopoll(s, mask);
+ return;
+ }
+
+ trace_pmu_cmd_adb_request(in_len, in_data[0], in_data[1], in_data[2],
+ in_data[3], in_data[4]);
+
+ *out_len = 0;
+
+ /* Check ADB len */
+ adblen = in_data[2];
+ if (adblen > (in_len - 3)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "PMU: ADB len is %d > %d (in_len -3)...erroring\n",
+ adblen, in_len - 3);
+ len = -1;
+ } else if (adblen > 252) {
+ qemu_log_mask(LOG_GUEST_ERROR, "PMU: ADB command too big!\n");
+ len = -1;
+ } else {
+ /* Format command */
+ adb_cmd[0] = in_data[0];
+ memcpy(&adb_cmd[1], &in_data[3], in_len - 3);
+ len = adb_request(&s->adb_bus, s->adb_reply + 2, adb_cmd, in_len - 2);
+
+ trace_pmu_cmd_adb_reply(len);
+ }
+
+ if (len > 0) {
+ /* XXX Check this */
+ s->adb_reply_size = len + 2;
+ s->adb_reply[0] = 0x01;
+ s->adb_reply[1] = len;
+ } else {
+ /* XXX Check this */
+ s->adb_reply_size = 1;
+ s->adb_reply[0] = 0x00;
+ }
+
+ s->intbits |= PMU_INT_ADB;
+ pmu_update_extirq(s);
+}
+
+static void pmu_cmd_adb_poll_off(PMUState *s,
+ const uint8_t *in_data, uint8_t in_len,
+ uint8_t *out_data, uint8_t *out_len)
+{
+ if (in_len != 0) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "PMU: ADB POLL OFF command, invalid len: %d want: 0\n",
+ in_len);
+ return;
+ }
+
+ if (s->has_adb && s->autopoll_mask) {
+ timer_del(s->adb_poll_timer);
+ s->autopoll_mask = false;
+ }
+}
+
+static void pmu_cmd_shutdown(PMUState *s,
+ const uint8_t *in_data, uint8_t in_len,
+ uint8_t *out_data, uint8_t *out_len)
+{
+ if (in_len != 4) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "PMU: SHUTDOWN command, invalid len: %d want: 4\n",
+ in_len);
+ return;
+ }
+
+ *out_len = 1;
+ out_data[0] = 0;
+
+ if (in_data[0] != 'M' || in_data[1] != 'A' || in_data[2] != 'T' ||
+ in_data[3] != 'T') {
+
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "PMU: SHUTDOWN command, Bad MATT signature\n");
+ return;
+ }
+
+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
+}
+
+static void pmu_cmd_reset(PMUState *s,
+ const uint8_t *in_data, uint8_t in_len,
+ uint8_t *out_data, uint8_t *out_len)
+{
+ if (in_len != 0) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "PMU: RESET command, invalid len: %d want: 0\n",
+ in_len);
+ return;
+ }
+
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+}
+
+static void pmu_cmd_get_rtc(PMUState *s,
+ const uint8_t *in_data, uint8_t in_len,
+ uint8_t *out_data, uint8_t *out_len)
+{
+ uint32_t ti;
+
+ if (in_len != 0) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "PMU: GET_RTC command, invalid len: %d want: 0\n",
+ in_len);
+ return;
+ }
+
+ ti = s->tick_offset + (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)
+ / NANOSECONDS_PER_SECOND);
+ out_data[0] = ti >> 24;
+ out_data[1] = ti >> 16;
+ out_data[2] = ti >> 8;
+ out_data[3] = ti;
+ *out_len = 4;
+}
+
+static void pmu_cmd_set_rtc(PMUState *s,
+ const uint8_t *in_data, uint8_t in_len,
+ uint8_t *out_data, uint8_t *out_len)
+{
+ uint32_t ti;
+
+ if (in_len != 4) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "PMU: SET_RTC command, invalid len: %d want: 4\n",
+ in_len);
+ return;
+ }
+
+ ti = (((uint32_t)in_data[0]) << 24) + (((uint32_t)in_data[1]) << 16)
+ + (((uint32_t)in_data[2]) << 8) + in_data[3];
+
+ s->tick_offset = ti - (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)
+ / NANOSECONDS_PER_SECOND);
+}
+
+static void pmu_cmd_system_ready(PMUState *s,
+ const uint8_t *in_data, uint8_t in_len,
+ uint8_t *out_data, uint8_t *out_len)
+{
+ /* Do nothing */
+}
+
+static void pmu_cmd_get_version(PMUState *s,
+ const uint8_t *in_data, uint8_t in_len,
+ uint8_t *out_data, uint8_t *out_len)
+{
+ *out_len = 1;
+ *out_data = 1; /* ??? Check what Apple does */
+}
+
+static void pmu_cmd_power_events(PMUState *s,
+ const uint8_t *in_data, uint8_t in_len,
+ uint8_t *out_data, uint8_t *out_len)
+{
+ if (in_len < 1) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "PMU: POWER EVENTS command, invalid len %d, want at least 1\n",
+ in_len);
+ return;
+ }
+
+ switch (in_data[0]) {
+ /* Dummies for now */
+ case PMU_PWR_GET_POWERUP_EVENTS:
+ *out_len = 2;
+ out_data[0] = 0;
+ out_data[1] = 0;
+ break;
+ case PMU_PWR_SET_POWERUP_EVENTS:
+ case PMU_PWR_CLR_POWERUP_EVENTS:
+ break;
+ case PMU_PWR_GET_WAKEUP_EVENTS:
+ *out_len = 2;
+ out_data[0] = 0;
+ out_data[1] = 0;
+ break;
+ case PMU_PWR_SET_WAKEUP_EVENTS:
+ case PMU_PWR_CLR_WAKEUP_EVENTS:
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "PMU: POWER EVENTS unknown subcommand 0x%02x\n",
+ in_data[0]);
+ }
+}
+
+static void pmu_cmd_get_cover(PMUState *s,
+ const uint8_t *in_data, uint8_t in_len,
+ uint8_t *out_data, uint8_t *out_len)
+{
+ /* Not 100% sure here, will have to check what a real Mac
+ * returns other than byte 0 bit 0 is LID closed on laptops
+ */
+ *out_len = 1;
+ *out_data = 0x00;
+}
+
+static void pmu_cmd_download_status(PMUState *s,
+ const uint8_t *in_data, uint8_t in_len,
+ uint8_t *out_data, uint8_t *out_len)
+{
+ /* This has to do with PMU firmware updates as far as I can tell.
+ *
+ * We return 0x62 which is what OpenPMU expects
+ */
+ *out_len = 1;
+ *out_data = 0x62;
+}
+
+static void pmu_cmd_read_pmu_ram(PMUState *s,
+ const uint8_t *in_data, uint8_t in_len,
+ uint8_t *out_data, uint8_t *out_len)
+{
+ if (in_len < 3) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "PMU: READ_PMU_RAM command, invalid len %d, expected 3\n",
+ in_len);
+ return;
+ }
+
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "PMU: Unsupported READ_PMU_RAM, args: %02x %02x %02x\n",
+ in_data[0], in_data[1], in_data[2]);
+
+ *out_len = 0;
+}
+
+/* description of commands */
+typedef struct PMUCmdHandler {
+ uint8_t command;
+ const char *name;
+ void (*handler)(PMUState *s,
+ const uint8_t *in_args, uint8_t in_len,
+ uint8_t *out_args, uint8_t *out_len);
+} PMUCmdHandler;
+
+static const PMUCmdHandler PMUCmdHandlers[] = {
+ { PMU_INT_ACK, "INT ACK", pmu_cmd_int_ack },
+ { PMU_SET_INTR_MASK, "SET INT MASK", pmu_cmd_set_int_mask },
+ { PMU_ADB_CMD, "ADB COMMAND", pmu_cmd_adb },
+ { PMU_ADB_POLL_OFF, "ADB POLL OFF", pmu_cmd_adb_poll_off },
+ { PMU_RESET, "REBOOT", pmu_cmd_reset },
+ { PMU_SHUTDOWN, "SHUTDOWN", pmu_cmd_shutdown },
+ { PMU_READ_RTC, "GET RTC", pmu_cmd_get_rtc },
+ { PMU_SET_RTC, "SET RTC", pmu_cmd_set_rtc },
+ { PMU_SYSTEM_READY, "SYSTEM READY", pmu_cmd_system_ready },
+ { PMU_GET_VERSION, "GET VERSION", pmu_cmd_get_version },
+ { PMU_POWER_EVENTS, "POWER EVENTS", pmu_cmd_power_events },
+ { PMU_GET_COVER, "GET_COVER", pmu_cmd_get_cover },
+ { PMU_DOWNLOAD_STATUS, "DOWNLOAD STATUS", pmu_cmd_download_status },
+ { PMU_READ_PMU_RAM, "READ PMGR RAM", pmu_cmd_read_pmu_ram },
+};
+
+static void pmu_dispatch_cmd(PMUState *s)
+{
+ unsigned int i;
+
+ /* No response by default */
+ s->cmd_rsp_sz = 0;
+
+ for (i = 0; i < ARRAY_SIZE(PMUCmdHandlers); i++) {
+ const PMUCmdHandler *desc = &PMUCmdHandlers[i];
+
+ if (desc->command != s->cmd) {
+ continue;
+ }
+
+ trace_pmu_dispatch_cmd(desc->name);
+ desc->handler(s, s->cmd_buf, s->cmd_buf_pos,
+ s->cmd_rsp, &s->cmd_rsp_sz);
+
+ if (s->rsplen != -1 && s->rsplen != s->cmd_rsp_sz) {
+ trace_pmu_debug_protocol_string("QEMU internal cmd resp mismatch!");
+ } else {
+ trace_pmu_debug_protocol_resp_size(s->cmd_rsp_sz);
+ }
+
+ return;
+ }
+
+ trace_pmu_dispatch_unknown_cmd(s->cmd);
+
+ /* Manufacture fake response with 0's */
+ if (s->rsplen == -1) {
+ s->cmd_rsp_sz = 0;
+ } else {
+ s->cmd_rsp_sz = s->rsplen;
+ memset(s->cmd_rsp, 0, s->rsplen);
+ }
+}
+
+static void pmu_update(PMUState *s)
+{
+ MOS6522PMUState *mps = &s->mos6522_pmu;
+ MOS6522State *ms = MOS6522(mps);
+
+ /* Only react to changes in reg B */
+ if (ms->b == s->last_b) {
+ return;
+ }
+ s->last_b = ms->b;
+
+ /* Check the TREQ / TACK state */
+ switch (ms->b & (TREQ | TACK)) {
+ case TREQ:
+ /* This is an ack release, handle it and bail out */
+ ms->b |= TACK;
+ s->last_b = ms->b;
+
+ trace_pmu_debug_protocol_string("handshake: TREQ high, setting TACK");
+ return;
+ case TACK:
+ /* This is a valid request, handle below */
+ break;
+ case TREQ | TACK:
+ /* This is an idle state */
+ return;
+ default:
+ /* Invalid state, log and ignore */
+ trace_pmu_debug_protocol_error(ms->b);
+ return;
+ }
+
+ /* If we wanted to handle commands asynchronously, this is where
+ * we would delay the clearing of TACK until we are ready to send
+ * the response
+ */
+
+ /* We have a request, handshake TACK so we don't stay in
+ * an invalid state. If we were concurrent with the OS we
+ * should only do this after we grabbed the SR but that isn't
+ * a problem here.
+ */
+
+ trace_pmu_debug_protocol_clear_treq(s->cmd_state);
+
+ ms->b &= ~TACK;
+ s->last_b = ms->b;
+
+ /* Act according to state */
+ switch (s->cmd_state) {
+ case pmu_state_idle:
+ if (!(ms->acr & SR_OUT)) {
+ trace_pmu_debug_protocol_string("protocol error! "
+ "state idle, ACR reading");
+ break;
+ }
+
+ s->cmd = ms->sr;
+ via_set_sr_int(s);
+ s->cmdlen = pmu_data_len[s->cmd][0];
+ s->rsplen = pmu_data_len[s->cmd][1];
+ s->cmd_buf_pos = 0;
+ s->cmd_rsp_pos = 0;
+ s->cmd_state = pmu_state_cmd;
+
+ trace_pmu_debug_protocol_cmd(s->cmd, s->cmdlen, s->rsplen);
+ break;
+
+ case pmu_state_cmd:
+ if (!(ms->acr & SR_OUT)) {
+ trace_pmu_debug_protocol_string("protocol error! "
+ "state cmd, ACR reading");
+ break;
+ }
+
+ if (s->cmdlen == -1) {
+ trace_pmu_debug_protocol_cmdlen(ms->sr);
+
+ s->cmdlen = ms->sr;
+ if (s->cmdlen > sizeof(s->cmd_buf)) {
+ trace_pmu_debug_protocol_cmd_toobig(s->cmdlen);
+ }
+ } else if (s->cmd_buf_pos < sizeof(s->cmd_buf)) {
+ s->cmd_buf[s->cmd_buf_pos++] = ms->sr;
+ }
+
+ via_set_sr_int(s);
+ break;
+
+ case pmu_state_rsp:
+ if (ms->acr & SR_OUT) {
+ trace_pmu_debug_protocol_string("protocol error! "
+ "state resp, ACR writing");
+ break;
+ }
+
+ if (s->rsplen == -1) {
+ trace_pmu_debug_protocol_cmd_send_resp_size(s->cmd_rsp_sz);
+
+ ms->sr = s->cmd_rsp_sz;
+ s->rsplen = s->cmd_rsp_sz;
+ } else if (s->cmd_rsp_pos < s->cmd_rsp_sz) {
+ trace_pmu_debug_protocol_cmd_send_resp(s->cmd_rsp_pos, s->rsplen);
+
+ ms->sr = s->cmd_rsp[s->cmd_rsp_pos++];
+ }
+
+ via_set_sr_int(s);
+ break;
+ }
+
+ /* Check for state completion */
+ if (s->cmd_state == pmu_state_cmd && s->cmdlen == s->cmd_buf_pos) {
+ trace_pmu_debug_protocol_string("Command reception complete, "
+ "dispatching...");
+
+ pmu_dispatch_cmd(s);
+ s->cmd_state = pmu_state_rsp;
+ }
+
+ if (s->cmd_state == pmu_state_rsp && s->rsplen == s->cmd_rsp_pos) {
+ trace_pmu_debug_protocol_cmd_resp_complete(ms->ier);
+
+ s->cmd_state = pmu_state_idle;
+ }
+}
+
+static uint64_t mos6522_pmu_read(void *opaque, hwaddr addr, unsigned size)
+{
+ PMUState *s = opaque;
+ MOS6522PMUState *mps = &s->mos6522_pmu;
+ MOS6522State *ms = MOS6522(mps);
+
+ addr = (addr >> 9) & 0xf;
+ return mos6522_read(ms, addr, size);
+}
+
+static void mos6522_pmu_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned size)
+{
+ PMUState *s = opaque;
+ MOS6522PMUState *mps = &s->mos6522_pmu;
+ MOS6522State *ms = MOS6522(mps);
+
+ addr = (addr >> 9) & 0xf;
+ mos6522_write(ms, addr, val, size);
+}
+
+static const MemoryRegionOps mos6522_pmu_ops = {
+ .read = mos6522_pmu_read,
+ .write = mos6522_pmu_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
+};
+
+static bool pmu_adb_state_needed(void *opaque)
+{
+ PMUState *s = opaque;
+
+ return s->has_adb;
+}
+
+static const VMStateDescription vmstate_pmu_adb = {
+ .name = "pmu/adb",
+ .version_id = 0,
+ .minimum_version_id = 0,
+ .needed = pmu_adb_state_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT16(adb_poll_mask, PMUState),
+ VMSTATE_TIMER_PTR(adb_poll_timer, PMUState),
+ VMSTATE_UINT8(adb_reply_size, PMUState),
+ VMSTATE_BUFFER(adb_reply, PMUState),
+ }
+};
+
+static const VMStateDescription vmstate_pmu = {
+ .name = "pmu",
+ .version_id = 0,
+ .minimum_version_id = 0,
+ .fields = (VMStateField[]) {
+ VMSTATE_STRUCT(mos6522_pmu.parent_obj, PMUState, 0, vmstate_mos6522,
+ MOS6522State),
+ VMSTATE_UINT8(last_b, PMUState),
+ VMSTATE_UINT8(cmd, PMUState),
+ VMSTATE_UINT32(cmdlen, PMUState),
+ VMSTATE_UINT32(rsplen, PMUState),
+ VMSTATE_UINT8(cmd_buf_pos, PMUState),
+ VMSTATE_BUFFER(cmd_buf, PMUState),
+ VMSTATE_UINT8(cmd_rsp_pos, PMUState),
+ VMSTATE_UINT8(cmd_rsp_sz, PMUState),
+ VMSTATE_BUFFER(cmd_rsp, PMUState),
+ VMSTATE_UINT8(intbits, PMUState),
+ VMSTATE_UINT8(intmask, PMUState),
+ VMSTATE_UINT8(autopoll_rate_ms, PMUState),
+ VMSTATE_UINT8(autopoll_mask, PMUState),
+ VMSTATE_UINT32(tick_offset, PMUState),
+ VMSTATE_TIMER_PTR(one_sec_timer, PMUState),
+ VMSTATE_INT64(one_sec_target, PMUState),
+ VMSTATE_END_OF_LIST()
+ },
+ .subsections = (const VMStateDescription * []) {
+ &vmstate_pmu_adb,
+ }
+};
+
+static void pmu_reset(DeviceState *dev)
+{
+ PMUState *s = VIA_PMU(dev);
+
+ /* OpenBIOS needs to do this? MacOS 9 needs it */
+ s->intmask = PMU_INT_ADB | PMU_INT_TICK;
+ s->intbits = 0;
+
+ s->cmd_state = pmu_state_idle;
+ s->autopoll_mask = 0;
+}
+
+static void pmu_realize(DeviceState *dev, Error **errp)
+{
+ PMUState *s = VIA_PMU(dev);
+ SysBusDevice *sbd;
+ MOS6522State *ms;
+ DeviceState *d;
+ struct tm tm;
+
+ /* Pass IRQ from 6522 */
+ d = DEVICE(&s->mos6522_pmu);
+ ms = MOS6522(d);
+ sbd = SYS_BUS_DEVICE(s);
+ sysbus_pass_irq(sbd, SYS_BUS_DEVICE(ms));
+
+ qemu_get_timedate(&tm, 0);
+ s->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET;
+ s->one_sec_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, pmu_one_sec_timer, s);
+ s->one_sec_target = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000;
+ timer_mod(s->one_sec_timer, s->one_sec_target);
+
+ if (s->has_adb) {
+ qbus_create_inplace(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS,
+ DEVICE(dev), "adb.0");
+ s->adb_poll_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, pmu_adb_poll, s);
+ s->adb_poll_mask = 0xffff;
+ s->autopoll_rate_ms = 20;
+ }
+}
+
+static void pmu_init(Object *obj)
+{
+ SysBusDevice *d = SYS_BUS_DEVICE(obj);
+ PMUState *s = VIA_PMU(obj);
+
+ object_property_add_link(obj, "gpio", TYPE_MACIO_GPIO,
+ (Object **) &s->gpio,
+ qdev_prop_allow_set_link_before_realize,
+ 0, NULL);
+
+ object_initialize(&s->mos6522_pmu, sizeof(s->mos6522_pmu),
+ TYPE_MOS6522_PMU);
+ qdev_set_parent_bus(DEVICE(&s->mos6522_pmu), sysbus_get_default());
+
+ memory_region_init_io(&s->mem, obj, &mos6522_pmu_ops, s, "via-pmu",
+ 0x2000);
+ sysbus_init_mmio(d, &s->mem);
+}
+
+static Property pmu_properties[] = {
+ DEFINE_PROP_BOOL("has-adb", PMUState, has_adb, true),
+ DEFINE_PROP_END_OF_LIST()
+};
+
+static void pmu_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = pmu_realize;
+ dc->reset = pmu_reset;
+ dc->vmsd = &vmstate_pmu;
+ dc->props = pmu_properties;
+ set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
+}
+
+static const TypeInfo pmu_type_info = {
+ .name = TYPE_VIA_PMU,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(PMUState),
+ .instance_init = pmu_init,
+ .class_init = pmu_class_init,
+};
+
+static void mos6522_pmu_portB_write(MOS6522State *s)
+{
+ MOS6522PMUState *mps = container_of(s, MOS6522PMUState, parent_obj);
+ PMUState *ps = container_of(mps, PMUState, mos6522_pmu);
+
+ if ((s->pcr & 0xe0) == 0x20 || (s->pcr & 0xe0) == 0x60) {
+ s->ifr &= ~CB2_INT;
+ }
+ s->ifr &= ~CB1_INT;
+
+ via_update_irq(ps);
+ pmu_update(ps);
+}
+
+static void mos6522_pmu_portA_write(MOS6522State *s)
+{
+ MOS6522PMUState *mps = container_of(s, MOS6522PMUState, parent_obj);
+ PMUState *ps = container_of(mps, PMUState, mos6522_pmu);
+
+ if ((s->pcr & 0x0e) == 0x02 || (s->pcr & 0x0e) == 0x06) {
+ s->ifr &= ~CA2_INT;
+ }
+ s->ifr &= ~CA1_INT;
+
+ via_update_irq(ps);
+}
+
+static void mos6522_pmu_reset(DeviceState *dev)
+{
+ MOS6522State *ms = MOS6522(dev);
+ MOS6522PMUState *mps = container_of(ms, MOS6522PMUState, parent_obj);
+ PMUState *s = container_of(mps, PMUState, mos6522_pmu);
+ MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(ms);
+
+ mdc->parent_reset(dev);
+
+ ms->timers[0].frequency = VIA_TIMER_FREQ;
+ ms->timers[1].frequency = (SCALE_US * 6000) / 4700;
+
+ s->last_b = ms->b = TACK | TREQ;
+}
+
+static void mos6522_pmu_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ MOS6522DeviceClass *mdc = MOS6522_DEVICE_CLASS(oc);
+
+ dc->reset = mos6522_pmu_reset;
+ mdc->portB_write = mos6522_pmu_portB_write;
+ mdc->portA_write = mos6522_pmu_portA_write;
+}
+
+static const TypeInfo mos6522_pmu_type_info = {
+ .name = TYPE_MOS6522_PMU,
+ .parent = TYPE_MOS6522,
+ .instance_size = sizeof(MOS6522PMUState),
+ .class_init = mos6522_pmu_class_init,
+};
+
+static void pmu_register_types(void)
+{
+ type_register_static(&pmu_type_info);
+ type_register_static(&mos6522_pmu_type_info);
+}
+
+type_init(pmu_register_types)
# hw/misc/macio/macio.c
macio_timer_write(uint64_t addr, unsigned len, uint64_t val) "write addr 0x%"PRIx64 " len %d val 0x%"PRIx64
macio_timer_read(uint64_t addr, unsigned len, uint32_t val) "read addr 0x%"PRIx64 " len %d val 0x%"PRIx32
+
+# hw/misc/macio/gpio.c
+macio_set_gpio(int gpio, bool state) "setting GPIO %d to %d"
+macio_gpio_irq_assert(int gpio) "asserting GPIO %d"
+macio_gpio_irq_deassert(int gpio) "deasserting GPIO %d"
+macio_gpio_write(uint64_t addr, uint64_t val) "addr: 0x%"PRIx64" value: 0x%"PRIx64
+macio_gpio_read(uint64_t addr, uint64_t val) "addr: 0x%"PRIx64" value: 0x%"PRIx64
+
+# hw/misc/macio/pmu.c
+pmu_adb_poll(int olen) "ADB autopoll, olen=%d"
+pmu_one_sec_timer(void) "PMU one sec..."
+pmu_cmd_set_int_mask(int intmask) "Setting PMU int mask to 0x%02x"
+pmu_cmd_set_adb_autopoll(int mask) "ADB set autopoll, mask=0x%04x"
+pmu_cmd_adb_nobus(void) "ADB PACKET with no ADB bus!"
+pmu_cmd_adb_request(int inlen, int indata0, int indata1, int indata2, int indata3, int indata4) "ADB request: len=%d, cmd=0x%02x, pflags=0x%02x, adblen=%d: 0x%02x 0x%02x..."
+pmu_cmd_adb_reply(int len) "ADB reply is %d bytes"
+pmu_dispatch_cmd(const char *name) "handling command %s"
+pmu_dispatch_unknown_cmd(int cmd) "Unknown PMU command 0x%02x"
+pmu_debug_protocol_string(const char *str) "%s"
+pmu_debug_protocol_resp_size(int size) "sending %d resp bytes"
+pmu_debug_protocol_error(int portB) "protocol error! portB=0x%02x"
+pmu_debug_protocol_clear_treq(int state) "TREQ cleared, clearing TACK, state: %d"
+pmu_debug_protocol_cmd(int cmd, int cmdlen, int rsplen) "Got command byte 0x%02x, clen=%d, rlen=%d"
+pmu_debug_protocol_cmdlen(int len) "got cmd length byte: %d"
+pmu_debug_protocol_cmd_toobig(int len) "command too big (%d bytes)"
+pmu_debug_protocol_cmd_send_resp_size(int len) "sending length byte: %d"
+pmu_debug_protocol_cmd_send_resp(int pos, int len) "sending byte: %d/%d"
+pmu_debug_protocol_cmd_resp_complete(int ier) "Response send complete. IER=0x%02x"
static void mos6522_update_irq(MOS6522State *s)
{
- if (s->ifr & s->ier & (SR_INT | T1_INT | T2_INT)) {
+ if (s->ifr & s->ier) {
qemu_irq_raise(s->irq);
} else {
qemu_irq_lower(s->irq);
break;
case VIA_REG_SR:
val = s->sr;
- s->ifr &= ~(SR_INT | CB1_INT | CB2_INT);
+ s->ifr &= ~SR_INT;
mos6522_update_irq(s);
break;
case VIA_REG_ACR:
mdc->set_sr_int = mos6522_set_sr_int;
mdc->portB_write = mos6522_portB_write;
mdc->portA_write = mos6522_portA_write;
+ mdc->update_irq = mos6522_update_irq;
mdc->get_timer1_counter_value = mos6522_get_counter_value;
mdc->get_timer2_counter_value = mos6522_get_counter_value;
mdc->get_timer1_load_time = mos6522_get_load_time;
#define PPC_MAC_H
#include "exec/memory.h"
+#include "hw/boards.h"
#include "hw/sysbus.h"
#include "hw/ide/internal.h"
#include "hw/input/adb.h"
/* New World IRQs */
#define NEWWORLD_CUDA_IRQ 0x19
+#define NEWWORLD_PMU_IRQ 0x19
#define NEWWORLD_ESCCB_IRQ 0x24
#define NEWWORLD_ESCCA_IRQ 0x25
#define NEWWORLD_IDE0_IRQ 0xd
#define NEWWORLD_IDE0_DMA_IRQ 0x2
#define NEWWORLD_IDE1_IRQ 0xe
#define NEWWORLD_IDE1_DMA_IRQ 0x3
+#define NEWWORLD_EXTING_GPIO1 0x2f
+#define NEWWORLD_EXTING_GPIO9 0x37
+
+/* Core99 machine */
+#define TYPE_CORE99_MACHINE MACHINE_TYPE_NAME("mac99")
+#define CORE99_MACHINE(obj) OBJECT_CHECK(Core99MachineState, (obj), \
+ TYPE_CORE99_MACHINE)
+
+#define CORE99_VIA_CONFIG_CUDA 0x0
+#define CORE99_VIA_CONFIG_PMU 0x1
+#define CORE99_VIA_CONFIG_PMU_ADB 0x2
+
+typedef struct Core99MachineState {
+ /*< private >*/
+ MachineState parent;
+
+ uint8_t via_config;
+} Core99MachineState;
/* MacIO */
#define TYPE_MACIO_IDE "macio-ide"
const char *kernel_cmdline = machine->kernel_cmdline;
const char *initrd_filename = machine->initrd_filename;
const char *boot_device = machine->boot_order;
+ Core99MachineState *core99_machine = CORE99_MACHINE(machine);
PowerPCCPU *cpu = NULL;
CPUPPCState *env = NULL;
char *filename;
UNINHostState *uninorth_pci;
PCIBus *pci_bus;
NewWorldMacIOState *macio;
+ bool has_pmu, has_adb;
MACIOIDEState *macio_ide;
BusState *adb_bus;
MacIONVRAMState *nvr;
}
machine->usb |= defaults_enabled() && !machine->usb_disabled;
+ has_pmu = (core99_machine->via_config != CORE99_VIA_CONFIG_CUDA);
+ has_adb = (core99_machine->via_config == CORE99_VIA_CONFIG_CUDA ||
+ core99_machine->via_config == CORE99_VIA_CONFIG_PMU_ADB);
/* Timebase Frequency */
if (kvm_enabled()) {
macio = NEWWORLD_MACIO(pci_create(pci_bus, -1, TYPE_NEWWORLD_MACIO));
dev = DEVICE(macio);
qdev_prop_set_uint64(dev, "frequency", tbfreq);
+ qdev_prop_set_bit(dev, "has-pmu", has_pmu);
+ qdev_prop_set_bit(dev, "has-adb", has_adb);
object_property_set_link(OBJECT(macio), OBJECT(pic_dev), "pic",
&error_abort);
qdev_init_nofail(dev);
"ide[1]"));
macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]);
- dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda"));
- adb_bus = qdev_get_child_bus(dev, "adb.0");
- dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD);
- qdev_init_nofail(dev);
- dev = qdev_create(adb_bus, TYPE_ADB_MOUSE);
- qdev_init_nofail(dev);
+ if (has_adb) {
+ if (has_pmu) {
+ dev = DEVICE(object_resolve_path_component(OBJECT(macio), "pmu"));
+ } else {
+ dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda"));
+ }
+
+ adb_bus = qdev_get_child_bus(dev, "adb.0");
+ dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD);
+ qdev_prop_set_bit(dev, "disable-direct-reg3-writes", has_pmu);
+ qdev_init_nofail(dev);
+
+ dev = qdev_create(adb_bus, TYPE_ADB_MOUSE);
+ qdev_prop_set_bit(dev, "disable-direct-reg3-writes", has_pmu);
+ qdev_init_nofail(dev);
+ }
if (machine->usb) {
pci_create_simple(pci_bus, -1, "pci-ohci");
/* U3 needs to use USB for input because Linux doesn't support via-cuda
on PPC64 */
- if (machine_arch == ARCH_MAC99_U3) {
+ if (!has_adb || machine_arch == ARCH_MAC99_U3) {
USBBus *usb_bus = usb_bus_find(-1);
usb_create_simple(usb_bus, "usb-kbd");
fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_VIACONFIG, core99_machine->via_config);
+
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
if (kvm_enabled()) {
#ifdef CONFIG_KVM
#endif
}
+static char *core99_get_via_config(Object *obj, Error **errp)
+{
+ Core99MachineState *cms = CORE99_MACHINE(obj);
+
+ switch (cms->via_config) {
+ default:
+ case CORE99_VIA_CONFIG_CUDA:
+ return g_strdup("cuda");
+
+ case CORE99_VIA_CONFIG_PMU:
+ return g_strdup("pmu");
+
+ case CORE99_VIA_CONFIG_PMU_ADB:
+ return g_strdup("pmu-adb");
+ }
+}
+
+static void core99_set_via_config(Object *obj, const char *value, Error **errp)
+{
+ Core99MachineState *cms = CORE99_MACHINE(obj);
+
+ if (!strcmp(value, "cuda")) {
+ cms->via_config = CORE99_VIA_CONFIG_CUDA;
+ } else if (!strcmp(value, "pmu")) {
+ cms->via_config = CORE99_VIA_CONFIG_PMU;
+ } else if (!strcmp(value, "pmu-adb")) {
+ cms->via_config = CORE99_VIA_CONFIG_PMU_ADB;
+ } else {
+ error_setg(errp, "Invalid via value");
+ error_append_hint(errp, "Valid values are cuda, pmu, pmu-adb.\n");
+ }
+}
+
+static void core99_instance_init(Object *obj)
+{
+ Core99MachineState *cms = CORE99_MACHINE(obj);
+
+ /* Default via_config is CORE99_VIA_CONFIG_CUDA */
+ cms->via_config = CORE99_VIA_CONFIG_CUDA;
+ object_property_add_str(obj, "via", core99_get_via_config,
+ core99_set_via_config, NULL);
+ object_property_set_description(obj, "via",
+ "Set VIA configuration. "
+ "Valid values are cuda, pmu and pmu-adb",
+ NULL);
+
+ return;
+}
+
static const TypeInfo core99_machine_info = {
.name = MACHINE_TYPE_NAME("mac99"),
.parent = TYPE_MACHINE,
.class_init = core99_machine_class_init,
+ .instance_init = core99_instance_init,
+ .instance_size = sizeof(Core99MachineState)
};
static void mac_machine_register_types(void)
*/
static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
{
- CPUState *cs = CPU(DEVICE(pc->threads));
+ PowerPCCPU *cpu = pc->threads[0];
+ CPUState *cs = CPU(cpu);
DeviceClass *dc = DEVICE_GET_CLASS(cs);
- PowerPCCPU *cpu = POWERPC_CPU(cs);
int smt_threads = CPU_CORE(pc)->nr_threads;
CPUPPCState *env = &cpu->env;
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
}
}
-static void pnv_chip_realize(DeviceState *dev, Error **errp)
+static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
{
- PnvChip *chip = PNV_CHIP(dev);
Error *error = NULL;
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
const char *typename = pnv_chip_core_typename(chip);
return;
}
- /* XSCOM bridge */
- pnv_xscom_realize(chip, &error);
- if (error) {
- error_propagate(errp, error);
- return;
- }
- sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
-
/* Cores */
pnv_chip_core_sanitize(chip, &error);
if (error) {
&PNV_CORE(pnv_core)->xscom_regs);
i++;
}
+}
+
+static void pnv_chip_realize(DeviceState *dev, Error **errp)
+{
+ PnvChip *chip = PNV_CHIP(dev);
+ Error *error = NULL;
+
+ /* XSCOM bridge */
+ pnv_xscom_realize(chip, &error);
+ if (error) {
+ error_propagate(errp, error);
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
+
+ /* Cores */
+ pnv_chip_core_realize(chip, &error);
+ if (error) {
+ error_propagate(errp, error);
+ return;
+ }
/* Create LPC controller */
object_property_set_bool(OBJECT(&chip->lpc), true, "realized",
env->msr |= MSR_HVB; /* Hypervisor mode */
}
-static void pnv_cpu_init(PowerPCCPU *cpu, Error **errp)
-{
- CPUPPCState *env = &cpu->env;
- int core_pir;
- int thread_index = 0; /* TODO: TCG supports only one thread */
- ppc_spr_t *pir = &env->spr_cb[SPR_PIR];
-
- core_pir = object_property_get_uint(OBJECT(cpu), "core-pir", &error_abort);
-
- /*
- * The PIR of a thread is the core PIR + the thread index. We will
- * need to find a way to get the thread index when TCG supports
- * more than 1. We could use the object name ?
- */
- pir->default_value = core_pir + thread_index;
-
- /* Set time-base frequency to 512 MHz */
- cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ);
-
- qemu_register_reset(pnv_cpu_reset, cpu);
-}
-
/*
* These values are read by the PowerNV HW monitors under Linux
*/
.endianness = DEVICE_BIG_ENDIAN,
};
-static void pnv_core_realize_child(Object *child, XICSFabric *xi, Error **errp)
+static void pnv_realize_vcpu(PowerPCCPU *cpu, XICSFabric *xi, Error **errp)
{
+ CPUPPCState *env = &cpu->env;
+ int core_pir;
+ int thread_index = 0; /* TODO: TCG supports only one thread */
+ ppc_spr_t *pir = &env->spr_cb[SPR_PIR];
Error *local_err = NULL;
- CPUState *cs = CPU(child);
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- object_property_set_bool(child, true, "realized", &local_err);
+ object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
- cpu->intc = icp_create(child, TYPE_PNV_ICP, xi, &local_err);
+ cpu->intc = icp_create(OBJECT(cpu), TYPE_PNV_ICP, xi, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
- pnv_cpu_init(cpu, &local_err);
- if (local_err) {
- error_propagate(errp, local_err);
- return;
- }
+ core_pir = object_property_get_uint(OBJECT(cpu), "core-pir", &error_abort);
+
+ /*
+ * The PIR of a thread is the core PIR + the thread index. We will
+ * need to find a way to get the thread index when TCG supports
+ * more than 1. We could use the object name ?
+ */
+ pir->default_value = core_pir + thread_index;
+
+ /* Set time-base frequency to 512 MHz */
+ cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ);
+
+ qemu_register_reset(pnv_cpu_reset, cpu);
}
static void pnv_core_realize(DeviceState *dev, Error **errp)
PnvCore *pc = PNV_CORE(OBJECT(dev));
CPUCore *cc = CPU_CORE(OBJECT(dev));
const char *typename = pnv_core_cpu_typename(pc);
- size_t size = object_type_get_instance_size(typename);
Error *local_err = NULL;
void *obj;
int i, j;
return;
}
- pc->threads = g_malloc0(size * cc->nr_threads);
+ pc->threads = g_new(PowerPCCPU *, cc->nr_threads);
for (i = 0; i < cc->nr_threads; i++) {
- obj = pc->threads + i * size;
+ obj = object_new(typename);
- object_initialize(obj, size, typename);
+ pc->threads[i] = POWERPC_CPU(obj);
snprintf(name, sizeof(name), "thread[%d]", i);
- object_property_add_child(OBJECT(pc), name, obj, &local_err);
+ object_property_add_child(OBJECT(pc), name, obj, &error_abort);
object_property_add_alias(obj, "core-pir", OBJECT(pc),
- "pir", &local_err);
- if (local_err) {
- goto err;
- }
+ "pir", &error_abort);
object_unref(obj);
}
for (j = 0; j < cc->nr_threads; j++) {
- obj = pc->threads + j * size;
-
- pnv_core_realize_child(obj, XICS_FABRIC(xi), &local_err);
+ pnv_realize_vcpu(pc->threads[j], XICS_FABRIC(xi), &local_err);
if (local_err) {
goto err;
}
err:
while (--i >= 0) {
- obj = pc->threads + i * size;
+ obj = OBJECT(pc->threads[i]);
object_unparent(obj);
}
g_free(pc->threads);
error_propagate(errp, local_err);
}
+static void pnv_unrealize_vcpu(PowerPCCPU *cpu)
+{
+ qemu_unregister_reset(pnv_cpu_reset, cpu);
+ object_unparent(cpu->intc);
+ cpu_remove_sync(CPU(cpu));
+ object_unparent(OBJECT(cpu));
+}
+
+static void pnv_core_unrealize(DeviceState *dev, Error **errp)
+{
+ PnvCore *pc = PNV_CORE(dev);
+ CPUCore *cc = CPU_CORE(dev);
+ int i;
+
+ for (i = 0; i < cc->nr_threads; i++) {
+ pnv_unrealize_vcpu(pc->threads[i]);
+ }
+ g_free(pc->threads);
+}
+
static Property pnv_core_properties[] = {
DEFINE_PROP_UINT32("pir", PnvCore, pir, 0),
DEFINE_PROP_END_OF_LIST(),
DeviceClass *dc = DEVICE_CLASS(oc);
dc->realize = pnv_core_realize;
+ dc->unrealize = pnv_core_unrealize;
dc->props = pnv_core_properties;
}
static void xics_system_init(MachineState *machine, int nr_irqs, Error **errp)
{
sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
+ Error *local_err = NULL;
if (kvm_enabled()) {
if (machine_kernel_irqchip_allowed(machine) &&
- !xics_kvm_init(spapr, errp)) {
+ !xics_kvm_init(spapr, &local_err)) {
spapr->icp_type = TYPE_KVM_ICP;
- spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs, errp);
+ spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs,
+ &local_err);
}
if (machine_kernel_irqchip_required(machine) && !spapr->ics) {
- error_prepend(errp, "kernel_irqchip requested but unavailable: ");
- return;
+ error_prepend(&local_err,
+ "kernel_irqchip requested but unavailable: ");
+ goto error;
}
+ error_free(local_err);
+ local_err = NULL;
}
if (!spapr->ics) {
xics_spapr_init(spapr);
spapr->icp_type = TYPE_ICP;
- spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs, errp);
- if (!spapr->ics) {
- return;
- }
+ spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs,
+ &local_err);
}
+
+error:
+ error_propagate(errp, local_err);
}
static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
caps = smc->default_caps;
- if (!ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00,
- 0, spapr->max_compat_pvr)) {
- caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN;
- }
-
if (!ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07,
0, spapr->max_compat_pvr)) {
caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF;
+ caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN;
}
if (!ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06_PLUS,
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
+ sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu);
target_ulong lpcr;
cpu_reset(cs);
/* Set a full AMOR so guest can use the AMR as it sees fit */
env->spr[SPR_AMOR] = 0xffffffffffffffffull;
+
+ spapr_cpu->vpa_addr = 0;
+ spapr_cpu->slb_shadow_addr = 0;
+ spapr_cpu->slb_shadow_size = 0;
+ spapr_cpu->dtl_addr = 0;
+ spapr_cpu->dtl_size = 0;
}
void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_ulong r3)
ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm);
}
-static void spapr_cpu_destroy(PowerPCCPU *cpu)
-{
- qemu_unregister_reset(spapr_cpu_reset, cpu);
-}
-
-static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu,
- Error **errp)
-{
- CPUPPCState *env = &cpu->env;
-
- /* Set time-base frequency to 512 MHz */
- cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);
-
- cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr));
- kvmppc_set_papr(cpu);
-
- qemu_register_reset(spapr_cpu_reset, cpu);
- spapr_cpu_reset(cpu);
-}
-
/*
* Return the sPAPR CPU core type for @model which essentially is the CPU
* model specified with -cpu cmdline option.
return object_class_get_name(oc);
}
-static void spapr_cpu_core_unrealizefn(DeviceState *dev, Error **errp)
+static void spapr_unrealize_vcpu(PowerPCCPU *cpu)
+{
+ qemu_unregister_reset(spapr_cpu_reset, cpu);
+ object_unparent(cpu->intc);
+ cpu_remove_sync(CPU(cpu));
+ object_unparent(OBJECT(cpu));
+}
+
+static void spapr_cpu_core_unrealize(DeviceState *dev, Error **errp)
{
sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
CPUCore *cc = CPU_CORE(dev);
int i;
for (i = 0; i < cc->nr_threads; i++) {
- Object *obj = OBJECT(sc->threads[i]);
- DeviceState *dev = DEVICE(obj);
- CPUState *cs = CPU(dev);
- PowerPCCPU *cpu = POWERPC_CPU(cs);
-
- spapr_cpu_destroy(cpu);
- object_unparent(cpu->intc);
- cpu_remove_sync(cs);
- object_unparent(obj);
+ spapr_unrealize_vcpu(sc->threads[i]);
}
g_free(sc->threads);
}
-static void spapr_cpu_core_realize_child(Object *child,
- sPAPRMachineState *spapr, Error **errp)
+static void spapr_realize_vcpu(PowerPCCPU *cpu, sPAPRMachineState *spapr,
+ Error **errp)
{
+ CPUPPCState *env = &cpu->env;
Error *local_err = NULL;
- CPUState *cs = CPU(child);
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- object_property_set_bool(child, true, "realized", &local_err);
+ object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
if (local_err) {
goto error;
}
- spapr_cpu_init(spapr, cpu, &local_err);
- if (local_err) {
- goto error;
- }
+ /* Set time-base frequency to 512 MHz */
+ cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);
+
+ cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr));
+ kvmppc_set_papr(cpu);
- cpu->intc = icp_create(child, spapr->icp_type, XICS_FABRIC(spapr),
+ qemu_register_reset(spapr_cpu_reset, cpu);
+ spapr_cpu_reset(cpu);
+
+ cpu->intc = icp_create(OBJECT(cpu), spapr->icp_type, XICS_FABRIC(spapr),
&local_err);
if (local_err) {
- goto error;
+ goto error_unregister;
}
return;
+error_unregister:
+ qemu_unregister_reset(spapr_cpu_reset, cpu);
+ cpu_remove_sync(CPU(cpu));
error:
error_propagate(errp, local_err);
}
+static PowerPCCPU *spapr_create_vcpu(sPAPRCPUCore *sc, int i, Error **errp)
+{
+ sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(sc);
+ CPUCore *cc = CPU_CORE(sc);
+ Object *obj;
+ char *id;
+ CPUState *cs;
+ PowerPCCPU *cpu;
+ Error *local_err = NULL;
+
+ obj = object_new(scc->cpu_type);
+
+ cs = CPU(obj);
+ cpu = POWERPC_CPU(obj);
+ cs->cpu_index = cc->core_id + i;
+ spapr_set_vcpu_id(cpu, cs->cpu_index, &local_err);
+ if (local_err) {
+ goto err;
+ }
+
+ cpu->node_id = sc->node_id;
+
+ id = g_strdup_printf("thread[%d]", i);
+ object_property_add_child(OBJECT(sc), id, obj, &local_err);
+ g_free(id);
+ if (local_err) {
+ goto err;
+ }
+
+ cpu->machine_data = g_new0(sPAPRCPUState, 1);
+
+ object_unref(obj);
+ return cpu;
+
+err:
+ object_unref(obj);
+ error_propagate(errp, local_err);
+ return NULL;
+}
+
+static void spapr_delete_vcpu(PowerPCCPU *cpu)
+{
+ sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu);
+
+ cpu->machine_data = NULL;
+ g_free(spapr_cpu);
+ object_unparent(OBJECT(cpu));
+}
+
static void spapr_cpu_core_realize(DeviceState *dev, Error **errp)
{
/* We don't use SPAPR_MACHINE() in order to exit gracefully if the user
(sPAPRMachineState *) object_dynamic_cast(qdev_get_machine(),
TYPE_SPAPR_MACHINE);
sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
- sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(dev));
CPUCore *cc = CPU_CORE(OBJECT(dev));
Error *local_err = NULL;
- Object *obj;
int i, j;
if (!spapr) {
sc->threads = g_new(PowerPCCPU *, cc->nr_threads);
for (i = 0; i < cc->nr_threads; i++) {
- char id[32];
- CPUState *cs;
- PowerPCCPU *cpu;
-
- obj = object_new(scc->cpu_type);
-
- cs = CPU(obj);
- cpu = sc->threads[i] = POWERPC_CPU(obj);
- cs->cpu_index = cc->core_id + i;
- spapr_set_vcpu_id(cpu, cs->cpu_index, &local_err);
+ sc->threads[i] = spapr_create_vcpu(sc, i, &local_err);
if (local_err) {
goto err;
}
-
-
- /* Set NUMA node for the threads belonged to core */
- cpu->node_id = sc->node_id;
-
- snprintf(id, sizeof(id), "thread[%d]", i);
- object_property_add_child(OBJECT(sc), id, obj, &local_err);
- if (local_err) {
- goto err;
- }
- object_unref(obj);
}
for (j = 0; j < cc->nr_threads; j++) {
- obj = OBJECT(sc->threads[j]);
-
- spapr_cpu_core_realize_child(obj, spapr, &local_err);
+ spapr_realize_vcpu(sc->threads[j], spapr, &local_err);
if (local_err) {
- goto err;
+ goto err_unrealize;
}
}
return;
+err_unrealize:
+ while (--j >= 0) {
+ spapr_unrealize_vcpu(sc->threads[j]);
+ }
err:
while (--i >= 0) {
- obj = OBJECT(sc->threads[i]);
- object_unparent(obj);
+ spapr_delete_vcpu(sc->threads[i]);
}
g_free(sc->threads);
error_propagate(errp, local_err);
sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc);
dc->realize = spapr_cpu_core_realize;
- dc->unrealize = spapr_cpu_core_unrealizefn;
+ dc->unrealize = spapr_cpu_core_unrealize;
dc->props = spapr_cpu_core_properties;
scc->cpu_type = data;
}
#include "exec/exec-all.h"
#include "helper_regs.h"
#include "hw/ppc/spapr.h"
+#include "hw/ppc/spapr_cpu_core.h"
#include "mmu-hash64.h"
#include "cpu-models.h"
#include "trace.h"
#define VPA_SHARED_PROC_OFFSET 0x9
#define VPA_SHARED_PROC_VAL 0x2
-static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa)
+static target_ulong register_vpa(PowerPCCPU *cpu, target_ulong vpa)
{
- CPUState *cs = CPU(ppc_env_get_cpu(env));
+ CPUState *cs = CPU(cpu);
+ CPUPPCState *env = &cpu->env;
+ sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu);
uint16_t size;
uint8_t tmp;
return H_PARAMETER;
}
- env->vpa_addr = vpa;
+ spapr_cpu->vpa_addr = vpa;
- tmp = ldub_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET);
+ tmp = ldub_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET);
tmp |= VPA_SHARED_PROC_VAL;
- stb_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp);
+ stb_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp);
return H_SUCCESS;
}
-static target_ulong deregister_vpa(CPUPPCState *env, target_ulong vpa)
+static target_ulong deregister_vpa(PowerPCCPU *cpu, target_ulong vpa)
{
- if (env->slb_shadow_addr) {
+ sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu);
+
+ if (spapr_cpu->slb_shadow_addr) {
return H_RESOURCE;
}
- if (env->dtl_addr) {
+ if (spapr_cpu->dtl_addr) {
return H_RESOURCE;
}
- env->vpa_addr = 0;
+ spapr_cpu->vpa_addr = 0;
return H_SUCCESS;
}
-static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr)
+static target_ulong register_slb_shadow(PowerPCCPU *cpu, target_ulong addr)
{
- CPUState *cs = CPU(ppc_env_get_cpu(env));
+ sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu);
uint32_t size;
if (addr == 0) {
return H_HARDWARE;
}
- size = ldl_be_phys(cs->as, addr + 0x4);
+ size = ldl_be_phys(CPU(cpu)->as, addr + 0x4);
if (size < 0x8) {
return H_PARAMETER;
}
return H_PARAMETER;
}
- if (!env->vpa_addr) {
+ if (!spapr_cpu->vpa_addr) {
return H_RESOURCE;
}
- env->slb_shadow_addr = addr;
- env->slb_shadow_size = size;
+ spapr_cpu->slb_shadow_addr = addr;
+ spapr_cpu->slb_shadow_size = size;
return H_SUCCESS;
}
-static target_ulong deregister_slb_shadow(CPUPPCState *env, target_ulong addr)
+static target_ulong deregister_slb_shadow(PowerPCCPU *cpu, target_ulong addr)
{
- env->slb_shadow_addr = 0;
- env->slb_shadow_size = 0;
+ sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu);
+
+ spapr_cpu->slb_shadow_addr = 0;
+ spapr_cpu->slb_shadow_size = 0;
return H_SUCCESS;
}
-static target_ulong register_dtl(CPUPPCState *env, target_ulong addr)
+static target_ulong register_dtl(PowerPCCPU *cpu, target_ulong addr)
{
- CPUState *cs = CPU(ppc_env_get_cpu(env));
+ sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu);
uint32_t size;
if (addr == 0) {
return H_HARDWARE;
}
- size = ldl_be_phys(cs->as, addr + 0x4);
+ size = ldl_be_phys(CPU(cpu)->as, addr + 0x4);
if (size < 48) {
return H_PARAMETER;
}
- if (!env->vpa_addr) {
+ if (!spapr_cpu->vpa_addr) {
return H_RESOURCE;
}
- env->dtl_addr = addr;
- env->dtl_size = size;
+ spapr_cpu->dtl_addr = addr;
+ spapr_cpu->dtl_size = size;
return H_SUCCESS;
}
-static target_ulong deregister_dtl(CPUPPCState *env, target_ulong addr)
+static target_ulong deregister_dtl(PowerPCCPU *cpu, target_ulong addr)
{
- env->dtl_addr = 0;
- env->dtl_size = 0;
+ sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu);
+
+ spapr_cpu->dtl_addr = 0;
+ spapr_cpu->dtl_size = 0;
return H_SUCCESS;
}
target_ulong procno = args[1];
target_ulong vpa = args[2];
target_ulong ret = H_PARAMETER;
- CPUPPCState *tenv;
PowerPCCPU *tcpu;
tcpu = spapr_find_cpu(procno);
if (!tcpu) {
return H_PARAMETER;
}
- tenv = &tcpu->env;
switch (flags) {
case FLAGS_REGISTER_VPA:
- ret = register_vpa(tenv, vpa);
+ ret = register_vpa(tcpu, vpa);
break;
case FLAGS_DEREGISTER_VPA:
- ret = deregister_vpa(tenv, vpa);
+ ret = deregister_vpa(tcpu, vpa);
break;
case FLAGS_REGISTER_SLBSHADOW:
- ret = register_slb_shadow(tenv, vpa);
+ ret = register_slb_shadow(tcpu, vpa);
break;
case FLAGS_DEREGISTER_SLBSHADOW:
- ret = deregister_slb_shadow(tenv, vpa);
+ ret = deregister_slb_shadow(tcpu, vpa);
break;
case FLAGS_REGISTER_DTL:
- ret = register_dtl(tenv, vpa);
+ ret = register_dtl(tcpu, vpa);
break;
case FLAGS_DEREGISTER_DTL:
- ret = deregister_dtl(tenv, vpa);
+ ret = deregister_dtl(tcpu, vpa);
break;
}
error_report_err(local_err);
return H_HARDWARE;
}
+ error_free(local_err);
local_err = NULL;
}
}
USBCCIDState *s = USB_CCID_DEV(dev);
ccid_bulk_in_clear(s);
- object_unref(OBJECT(&s->bus));
}
static void ccid_flush_pending_answers(USBCCIDState *s)
.load_request = usb_msd_load_request,
};
-static void usb_msd_unrealize_storage(USBDevice *dev, Error **errp)
-{
- MSDState *s = USB_STORAGE_DEV(dev);
-
- object_unref(OBJECT(&s->bus));
-}
-
static void usb_msd_storage_realize(USBDevice *dev, Error **errp)
{
MSDState *s = USB_STORAGE_DEV(dev);
s->scsi_dev = scsi_dev;
}
-static void usb_msd_bot_unrealize(USBDevice *dev, Error **errp)
-{
- MSDState *s = USB_STORAGE_DEV(dev);
-
- object_unref(OBJECT(&s->bus));
-}
-
static void usb_msd_bot_realize(USBDevice *dev, Error **errp)
{
MSDState *s = USB_STORAGE_DEV(dev);
USBDeviceClass *uc = USB_DEVICE_CLASS(klass);
uc->realize = usb_msd_storage_realize;
- uc->unrealize = usb_msd_unrealize_storage;
dc->props = msd_properties;
}
USBDeviceClass *uc = USB_DEVICE_CLASS(klass);
uc->realize = usb_msd_bot_realize;
- uc->unrealize = usb_msd_bot_unrealize;
uc->attached_settable = true;
}
UASDevice *uas = USB_UAS(dev);
qemu_bh_delete(uas->status_bh);
-
- object_unref(OBJECT(&uas->bus));
}
static void usb_uas_realize(USBDevice *dev, Error **errp)
--- /dev/null
+#ifndef RAMFB_H
+#define RAMFB_H
+
+/* ramfb.c */
+typedef struct RAMFBState RAMFBState;
+void ramfb_display_update(QemuConsole *con, RAMFBState *s);
+RAMFBState *ramfb_setup(Error **errp);
+
+/* ramfb-standalone.c */
+#define TYPE_RAMFB_DEVICE "ramfb"
+
+#endif /* RAMFB_H */
int devaddr;
int handler;
+ bool disable_direct_reg3_writes;
};
#define ADB_DEVICE_CLASS(cls) \
--- /dev/null
+/*
+ * PowerMac NewWorld MacIO GPIO emulation
+ *
+ * Copyright (c) 2016 Benjamin Herrenschmidt
+ * Copyright (c) 2018 Mark Cave-Ayland
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef MACIO_GPIO_H
+#define MACIO_GPIO_H
+
+#define TYPE_MACIO_GPIO "macio-gpio"
+#define MACIO_GPIO(obj) OBJECT_CHECK(MacIOGPIOState, (obj), TYPE_MACIO_GPIO)
+
+typedef struct MacIOGPIOState {
+ /*< private >*/
+ SysBusDevice parent;
+ /*< public >*/
+
+ OpenPICState *pic;
+
+ MemoryRegion gpiomem;
+ qemu_irq gpio_extirqs[10];
+ uint8_t gpio_levels[8];
+ uint8_t gpio_regs[36]; /* XXX Check count */
+} MacIOGPIOState;
+
+void macio_set_gpio(MacIOGPIOState *s, uint32_t gpio, bool state);
+
+#endif
#ifndef MACIO_H
#define MACIO_H
+#include "hw/char/escc.h"
#include "hw/intc/heathrow_pic.h"
#include "hw/misc/macio/cuda.h"
+#include "hw/misc/macio/gpio.h"
+#include "hw/misc/macio/pmu.h"
#include "hw/ppc/mac_dbdma.h"
#include "hw/ppc/openpic.h"
MemoryRegion bar;
CUDAState cuda;
+ PMUState pmu;
DBDMAState dbdma;
ESCCState escc;
uint64_t frequency;
MacIOState parent_obj;
/*< public >*/
+ bool has_pmu;
+ bool has_adb;
OpenPICState *pic;
MACIOIDEState ide[2];
+ MacIOGPIOState gpio;
} NewWorldMacIOState;
#endif /* MACIO_H */
--- /dev/null
+/*
+ * Definitions for talking to the PMU. The PMU is a microcontroller
+ * which controls battery charging and system power on PowerBook 3400
+ * and 2400 models as well as the RTC and various other things.
+ *
+ * Copyright (C) 1998 Paul Mackerras.
+ * Copyright (C) 2016 Ben Herrenschmidt
+ */
+
+#ifndef PMU_H
+#define PMU_H
+
+/*
+ * PMU commands
+ */
+
+#define PMU_POWER_CTRL0 0x10 /* control power of some devices */
+#define PMU_POWER_CTRL 0x11 /* control power of some devices */
+#define PMU_ADB_CMD 0x20 /* send ADB packet */
+#define PMU_ADB_POLL_OFF 0x21 /* disable ADB auto-poll */
+#define PMU_WRITE_NVRAM 0x33 /* write non-volatile RAM */
+#define PMU_READ_NVRAM 0x3b /* read non-volatile RAM */
+#define PMU_SET_RTC 0x30 /* set real-time clock */
+#define PMU_READ_RTC 0x38 /* read real-time clock */
+#define PMU_SET_VOLBUTTON 0x40 /* set volume up/down position */
+#define PMU_BACKLIGHT_BRIGHT 0x41 /* set backlight brightness */
+#define PMU_GET_VOLBUTTON 0x48 /* get volume up/down position */
+#define PMU_PCEJECT 0x4c /* eject PC-card from slot */
+#define PMU_BATTERY_STATE 0x6b /* report battery state etc. */
+#define PMU_SMART_BATTERY_STATE 0x6f /* report battery state (new way) */
+#define PMU_SET_INTR_MASK 0x70 /* set PMU interrupt mask */
+#define PMU_INT_ACK 0x78 /* read interrupt bits */
+#define PMU_SHUTDOWN 0x7e /* turn power off */
+#define PMU_CPU_SPEED 0x7d /* control CPU speed on some models */
+#define PMU_SLEEP 0x7f /* put CPU to sleep */
+#define PMU_POWER_EVENTS 0x8f /* Send power-event commands to PMU */
+#define PMU_I2C_CMD 0x9a /* I2C operations */
+#define PMU_RESET 0xd0 /* reset CPU */
+#define PMU_GET_BRIGHTBUTTON 0xd9 /* report brightness up/down pos */
+#define PMU_GET_COVER 0xdc /* report cover open/closed */
+#define PMU_SYSTEM_READY 0xdf /* tell PMU we are awake */
+#define PMU_DOWNLOAD_STATUS 0xe2 /* Called by MacOS during boot... */
+#define PMU_READ_PMU_RAM 0xe8 /* read the PMU RAM... ??? */
+#define PMU_GET_VERSION 0xea /* read the PMU version */
+
+/* Bits to use with the PMU_POWER_CTRL0 command */
+#define PMU_POW0_ON 0x80 /* OR this to power ON the device */
+#define PMU_POW0_OFF 0x00 /* leave bit 7 to 0 to power it OFF */
+#define PMU_POW0_HARD_DRIVE 0x04 /* Hard drive power
+ * (on wallstreet/lombard ?) */
+
+/* Bits to use with the PMU_POWER_CTRL command */
+#define PMU_POW_ON 0x80 /* OR this to power ON the device */
+#define PMU_POW_OFF 0x00 /* leave bit 7 to 0 to power it OFF */
+#define PMU_POW_BACKLIGHT 0x01 /* backlight power */
+#define PMU_POW_CHARGER 0x02 /* battery charger power */
+#define PMU_POW_IRLED 0x04 /* IR led power (on wallstreet) */
+#define PMU_POW_MEDIABAY 0x08 /* media bay power
+ * (wallstreet/lombard ?) */
+
+/* Bits in PMU interrupt and interrupt mask bytes */
+#define PMU_INT_PCEJECT 0x04 /* PC-card eject buttons */
+#define PMU_INT_SNDBRT 0x08 /* sound/brightness up/down buttons */
+#define PMU_INT_ADB 0x10 /* ADB autopoll or reply data */
+#define PMU_INT_BATTERY 0x20 /* Battery state change */
+#define PMU_INT_ENVIRONMENT 0x40 /* Environment interrupts */
+#define PMU_INT_TICK 0x80 /* 1-second tick interrupt */
+
+/* Other bits in PMU interrupt valid when PMU_INT_ADB is set */
+#define PMU_INT_ADB_AUTO 0x04 /* ADB autopoll, when PMU_INT_ADB */
+#define PMU_INT_WAITING_CHARGER 0x01 /* ??? */
+#define PMU_INT_AUTO_SRQ_POLL 0x02 /* ??? */
+
+/* Bits in the environement message (either obtained via PMU_GET_COVER,
+ * or via PMU_INT_ENVIRONMENT on core99 */
+#define PMU_ENV_LID_CLOSED 0x01 /* The lid is closed */
+
+/* I2C related definitions */
+#define PMU_I2C_MODE_SIMPLE 0
+#define PMU_I2C_MODE_STDSUB 1
+#define PMU_I2C_MODE_COMBINED 2
+
+#define PMU_I2C_BUS_STATUS 0
+#define PMU_I2C_BUS_SYSCLK 1
+#define PMU_I2C_BUS_POWER 2
+
+#define PMU_I2C_STATUS_OK 0
+#define PMU_I2C_STATUS_DATAREAD 1
+#define PMU_I2C_STATUS_BUSY 0xfe
+
+/* Kind of PMU (model) */
+enum {
+ PMU_UNKNOWN,
+ PMU_OHARE_BASED, /* 2400, 3400, 3500 (old G3 powerbook) */
+ PMU_HEATHROW_BASED, /* PowerBook G3 series */
+ PMU_PADDINGTON_BASED, /* 1999 PowerBook G3 */
+ PMU_KEYLARGO_BASED, /* Core99 motherboard (PMU99) */
+ PMU_68K_V1, /* 68K PMU, version 1 */
+ PMU_68K_V2, /* 68K PMU, version 2 */
+};
+
+/* PMU PMU_POWER_EVENTS commands */
+enum {
+ PMU_PWR_GET_POWERUP_EVENTS = 0x00,
+ PMU_PWR_SET_POWERUP_EVENTS = 0x01,
+ PMU_PWR_CLR_POWERUP_EVENTS = 0x02,
+ PMU_PWR_GET_WAKEUP_EVENTS = 0x03,
+ PMU_PWR_SET_WAKEUP_EVENTS = 0x04,
+ PMU_PWR_CLR_WAKEUP_EVENTS = 0x05,
+};
+
+/* Power events wakeup bits */
+enum {
+ PMU_PWR_WAKEUP_KEY = 0x01, /* Wake on key press */
+ PMU_PWR_WAKEUP_AC_INSERT = 0x02, /* Wake on AC adapter plug */
+ PMU_PWR_WAKEUP_AC_CHANGE = 0x04,
+ PMU_PWR_WAKEUP_LID_OPEN = 0x08,
+ PMU_PWR_WAKEUP_RING = 0x10,
+};
+
+/*
+ * This table indicates for each PMU opcode:
+ * - the number of data bytes to be sent with the command, or -1
+ * if a length byte should be sent,
+ * - the number of response bytes which the PMU will return, or
+ * -1 if it will send a length byte.
+ */
+
+static const int8_t pmu_data_len[256][2] = {
+/* 0 1 2 3 4 5 6 7 */
+ {-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
+ {-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},
+ { 1, 0},{ 1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
+ { 0, 1},{ 0, 1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{ 0, 0},
+ {-1, 0},{ 0, 0},{ 2, 0},{ 1, 0},{ 1, 0},{-1, 0},{-1, 0},{-1, 0},
+ { 0, -1},{ 0, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{ 0, -1},
+ { 4, 0},{20, 0},{-1, 0},{ 3, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
+ { 0, 4},{ 0, 20},{ 2, -1},{ 2, 1},{ 3, -1},{-1, -1},{-1, -1},{ 4, 0},
+ { 1, 0},{ 1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
+ { 0, 1},{ 0, 1},{-1, -1},{ 1, 0},{ 1, 0},{-1, -1},{-1, -1},{-1, -1},
+ { 1, 0},{ 0, 0},{ 2, 0},{ 2, 0},{-1, 0},{ 1, 0},{ 3, 0},{ 1, 0},
+ { 0, 1},{ 1, 0},{ 0, 2},{ 0, 2},{ 0, -1},{-1, -1},{-1, -1},{-1, -1},
+ { 2, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
+ { 0, 3},{ 0, 3},{ 0, 2},{ 0, 8},{ 0, -1},{ 0, -1},{-1, -1},{-1, -1},
+ { 1, 0},{ 1, 0},{ 1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
+ { 0, -1},{ 0, -1},{-1, -1},{-1, -1},{-1, -1},{ 5, 1},{ 4, 1},{ 4, 1},
+ { 4, 0},{-1, 0},{ 0, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
+ { 0, 5},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},
+ { 1, 0},{ 2, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
+ { 0, 1},{ 0, 1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},
+ { 2, 0},{ 2, 0},{ 2, 0},{ 4, 0},{-1, 0},{ 0, 0},{-1, 0},{-1, 0},
+ { 1, 1},{ 1, 0},{ 3, 0},{ 2, 0},{-1, -1},{-1, -1},{-1, -1},{-1, -1},
+ {-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
+ {-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},
+ {-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
+ {-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},
+ { 0, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
+ { 1, 1},{ 1, 1},{-1, -1},{-1, -1},{ 0, 1},{ 0, -1},{-1, -1},{-1, -1},
+ {-1, 0},{ 4, 0},{ 0, 1},{-1, 0},{-1, 0},{ 4, 0},{-1, 0},{-1, 0},
+ { 3, -1},{-1, -1},{ 0, 1},{-1, -1},{ 0, -1},{-1, -1},{-1, -1},{ 0, 0},
+ {-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
+ {-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},
+};
+
+/* Command protocol state machine */
+typedef enum {
+ pmu_state_idle, /* Waiting for command */
+ pmu_state_cmd, /* Receiving command */
+ pmu_state_rsp, /* Responding to command */
+} PMUCmdState;
+
+/* MOS6522 PMU */
+typedef struct MOS6522PMUState {
+ /*< private >*/
+ MOS6522State parent_obj;
+} MOS6522PMUState;
+
+#define TYPE_MOS6522_PMU "mos6522-pmu"
+#define MOS6522_PMU(obj) OBJECT_CHECK(MOS6522PMUState, (obj), \
+ TYPE_MOS6522_PMU)
+/**
+ * PMUState:
+ * @last_b: last value of B register
+ */
+
+typedef struct PMUState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+ /*< public >*/
+
+ MemoryRegion mem;
+ uint64_t frequency;
+ qemu_irq via_irq;
+ bool via_irq_state;
+
+ /* PMU state */
+ MOS6522PMUState mos6522_pmu;
+
+ /* PMU low level protocol state */
+ PMUCmdState cmd_state;
+ uint8_t last_b;
+ uint8_t cmd;
+ uint32_t cmdlen;
+ uint32_t rsplen;
+ uint8_t cmd_buf_pos;
+ uint8_t cmd_buf[128];
+ uint8_t cmd_rsp_pos;
+ uint8_t cmd_rsp_sz;
+ uint8_t cmd_rsp[128];
+
+ /* PMU events/interrupts */
+ uint8_t intbits;
+ uint8_t intmask;
+
+ /* ADB */
+ bool has_adb;
+ ADBBusState adb_bus;
+ uint16_t adb_poll_mask;
+ uint8_t autopoll_rate_ms;
+ uint8_t autopoll_mask;
+ QEMUTimer *adb_poll_timer;
+ uint8_t adb_reply_size;
+ uint8_t adb_reply[ADB_MAX_OUT_LEN];
+
+ /* RTC */
+ uint32_t tick_offset;
+ QEMUTimer *one_sec_timer;
+ int64_t one_sec_target;
+
+ /* GPIO */
+ MacIOGPIOState *gpio;
+} PMUState;
+
+#define TYPE_VIA_PMU "via-pmu"
+#define VIA_PMU(obj) OBJECT_CHECK(PMUState, (obj), TYPE_VIA_PMU)
+
+#endif /* PMU_H */
void (*set_sr_int)(MOS6522State *dev);
void (*portB_write)(MOS6522State *dev);
void (*portA_write)(MOS6522State *dev);
+ void (*update_irq)(MOS6522State *dev);
/* These are used to influence the CUDA MacOS timebase calibration */
uint64_t (*get_timer1_counter_value)(MOS6522State *dev, MOS6522Timer *ti);
uint64_t (*get_timer2_counter_value)(MOS6522State *dev, MOS6522Timer *ti);
CPUCore parent_obj;
/*< public >*/
- void *threads;
+ PowerPCCPU **threads;
uint32_t pir;
MemoryRegion xscom_regs;
#define FW_CFG_PPC_NVRAM_ADDR (FW_CFG_ARCH_LOCAL + 0x08)
#define FW_CFG_PPC_BUSFREQ (FW_CFG_ARCH_LOCAL + 0x09)
#define FW_CFG_PPC_NVRAM_FLAT (FW_CFG_ARCH_LOCAL + 0x0a)
+#define FW_CFG_PPC_VIACONFIG (FW_CFG_ARCH_LOCAL + 0x0b)
#define PPC_SERIAL_MM_BAUDBASE 399193
const char *spapr_get_cpu_core_type(const char *cpu_type);
void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_ulong r3);
+typedef struct sPAPRCPUState {
+ uint64_t vpa_addr;
+ uint64_t slb_shadow_addr, slb_shadow_size;
+ uint64_t dtl_addr, dtl_size;
+} sPAPRCPUState;
+
+static inline sPAPRCPUState *spapr_cpu_state(PowerPCCPU *cpu)
+{
+ return (sPAPRCPUState *)cpu->machine_data;
+}
+
#endif
import os
import subprocess
import qmp.qmp
+import re
import shutil
+import socket
import tempfile
LOG = logging.getLogger(__name__)
+#: Maps machine types to the preferred console device types
+CONSOLE_DEV_TYPES = {
+ r'^clipper$': 'isa-serial',
+ r'^malta': 'isa-serial',
+ r'^(pc.*|q35.*|isapc)$': 'isa-serial',
+ r'^(40p|powernv|prep)$': 'isa-serial',
+ r'^pseries.*': 'spapr-vty',
+ r'^s390-ccw-virtio.*': 'sclpconsole',
+ }
+
+
class QEMUMachineError(Exception):
"""
Exception called when an error in QEMUMachine happens.
"""
+class QEMUMachineAddDeviceError(QEMUMachineError):
+ """
+ Exception raised when a request to add a device can not be fulfilled
+
+ The failures are caused by limitations, lack of information or conflicting
+ requests on the QEMUMachine methods. This exception does not represent
+ failures reported by the QEMU binary itself.
+ """
+
class MonitorResponseError(qmp.qmp.QMPError):
'''
Represents erroneous QMP monitor reply
self._test_dir = test_dir
self._temp_dir = None
self._launched = False
+ self._machine = None
+ self._console_device_type = None
+ self._console_address = None
+ self._console_socket = None
# just in case logging wasn't configured by the main script:
logging.basicConfig()
self._monitor_address[1])
else:
moncdev = 'socket,id=mon,path=%s' % self._vm_monitor
- return ['-chardev', moncdev,
+ args = ['-chardev', moncdev,
'-mon', 'chardev=mon,mode=control',
'-display', 'none', '-vga', 'none']
+ if self._machine is not None:
+ args.extend(['-machine', self._machine])
+ if self._console_device_type is not None:
+ self._console_address = os.path.join(self._temp_dir,
+ self._name + "-console.sock")
+ chardev = ('socket,id=console,path=%s,server,nowait' %
+ self._console_address)
+ device = '%s,chardev=console' % self._console_device_type
+ args.extend(['-chardev', chardev, '-device', device])
+ return args
def _pre_launch(self):
self._temp_dir = tempfile.mkdtemp(dir=self._test_dir)
self._qemu_log_path = None
+ if self._console_socket is not None:
+ self._console_socket.close()
+ self._console_socket = None
+
if self._temp_dir is not None:
shutil.rmtree(self._temp_dir)
self._temp_dir = None
of the qemu process.
'''
return self._iolog
+
+ def add_args(self, *args):
+ '''
+ Adds to the list of extra arguments to be given to the QEMU binary
+ '''
+ self._args.extend(args)
+
+ def set_machine(self, machine_type):
+ '''
+ Sets the machine type
+
+ If set, the machine type will be added to the base arguments
+ of the resulting QEMU command line.
+ '''
+ self._machine = machine_type
+
+ def set_console(self, device_type=None):
+ '''
+ Sets the device type for a console device
+
+ If set, the console device and a backing character device will
+ be added to the base arguments of the resulting QEMU command
+ line.
+
+ This is a convenience method that will either use the provided
+ device type, of if not given, it will used the device type set
+ on CONSOLE_DEV_TYPES.
+
+ The actual setting of command line arguments will be be done at
+ machine launch time, as it depends on the temporary directory
+ to be created.
+
+ @param device_type: the device type, such as "isa-serial"
+ @raises: QEMUMachineAddDeviceError if the device type is not given
+ and can not be determined.
+ '''
+ if device_type is None:
+ if self._machine is None:
+ raise QEMUMachineAddDeviceError("Can not add a console device:"
+ " QEMU instance without a "
+ "defined machine type")
+ for regex, device in CONSOLE_DEV_TYPES.items():
+ if re.match(regex, self._machine):
+ device_type = device
+ break
+ if device_type is None:
+ raise QEMUMachineAddDeviceError("Can not add a console device:"
+ " no matching console device "
+ "type definition")
+ self._console_device_type = device_type
+
+ @property
+ def console_socket(self):
+ """
+ Returns a socket connected to the console
+ """
+ if self._console_socket is None:
+ self._console_socket = socket.socket(socket.AF_UNIX,
+ socket.SOCK_STREAM)
+ self._console_socket.connect(self._console_address)
+ return self._console_socket
target_ulong rmls;
#endif
-#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
- uint64_t vpa_addr;
- uint64_t slb_shadow_addr, slb_shadow_size;
- uint64_t dtl_addr, dtl_size;
-#endif /* TARGET_PPC64 */
-
int error_code;
uint32_t pending_interrupts;
#if !defined(CONFIG_USER_ONLY)
uint32_t compat_pvr;
PPCVirtualHypervisor *vhyp;
Object *intc;
+ void *machine_data;
int32_t node_id; /* NUMA node this CPU belongs to */
PPCHash64Options *hash64_opts;
void ppc_store_msr (CPUPPCState *env, target_ulong value);
void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
-#if defined(TARGET_PPC64)
-#endif
/* Time-base and decrementer management */
#ifndef NO_CPU_IO_DEFS
static int kvm_get_vpa(CPUState *cs)
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
+ sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu);
struct kvm_one_reg reg;
int ret;
reg.id = KVM_REG_PPC_VPA_ADDR;
- reg.addr = (uintptr_t)&env->vpa_addr;
+ reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
if (ret < 0) {
DPRINTF("Unable to get VPA address from KVM: %s\n", strerror(errno));
return ret;
}
- assert((uintptr_t)&env->slb_shadow_size
- == ((uintptr_t)&env->slb_shadow_addr + 8));
+ assert((uintptr_t)&spapr_cpu->slb_shadow_size
+ == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8));
reg.id = KVM_REG_PPC_VPA_SLB;
- reg.addr = (uintptr_t)&env->slb_shadow_addr;
+ reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr;
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
if (ret < 0) {
DPRINTF("Unable to get SLB shadow state from KVM: %s\n",
return ret;
}
- assert((uintptr_t)&env->dtl_size == ((uintptr_t)&env->dtl_addr + 8));
+ assert((uintptr_t)&spapr_cpu->dtl_size
+ == ((uintptr_t)&spapr_cpu->dtl_addr + 8));
reg.id = KVM_REG_PPC_VPA_DTL;
- reg.addr = (uintptr_t)&env->dtl_addr;
+ reg.addr = (uintptr_t)&spapr_cpu->dtl_addr;
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
if (ret < 0) {
DPRINTF("Unable to get dispatch trace log state from KVM: %s\n",
static int kvm_put_vpa(CPUState *cs)
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
+ sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu);
struct kvm_one_reg reg;
int ret;
* registered. That means when restoring state, if a VPA *is*
* registered, we need to set that up first. If not, we need to
* deregister the others before deregistering the master VPA */
- assert(env->vpa_addr || !(env->slb_shadow_addr || env->dtl_addr));
+ assert(spapr_cpu->vpa_addr
+ || !(spapr_cpu->slb_shadow_addr || spapr_cpu->dtl_addr));
- if (env->vpa_addr) {
+ if (spapr_cpu->vpa_addr) {
reg.id = KVM_REG_PPC_VPA_ADDR;
- reg.addr = (uintptr_t)&env->vpa_addr;
+ reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
if (ret < 0) {
DPRINTF("Unable to set VPA address to KVM: %s\n", strerror(errno));
}
}
- assert((uintptr_t)&env->slb_shadow_size
- == ((uintptr_t)&env->slb_shadow_addr + 8));
+ assert((uintptr_t)&spapr_cpu->slb_shadow_size
+ == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8));
reg.id = KVM_REG_PPC_VPA_SLB;
- reg.addr = (uintptr_t)&env->slb_shadow_addr;
+ reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr;
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
if (ret < 0) {
DPRINTF("Unable to set SLB shadow state to KVM: %s\n", strerror(errno));
return ret;
}
- assert((uintptr_t)&env->dtl_size == ((uintptr_t)&env->dtl_addr + 8));
+ assert((uintptr_t)&spapr_cpu->dtl_size
+ == ((uintptr_t)&spapr_cpu->dtl_addr + 8));
reg.id = KVM_REG_PPC_VPA_DTL;
- reg.addr = (uintptr_t)&env->dtl_addr;
+ reg.addr = (uintptr_t)&spapr_cpu->dtl_addr;
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
if (ret < 0) {
DPRINTF("Unable to set dispatch trace log state to KVM: %s\n",
return ret;
}
- if (!env->vpa_addr) {
+ if (!spapr_cpu->vpa_addr) {
reg.id = KVM_REG_PPC_VPA_ADDR;
- reg.addr = (uintptr_t)&env->vpa_addr;
+ reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
if (ret < 0) {
DPRINTF("Unable to set VPA address to KVM: %s\n", strerror(errno));
return cap_mmu_hash_v3;
}
+static bool kvmppc_power8_host(void)
+{
+ bool ret = false;
+#ifdef TARGET_PPC64
+ {
+ uint32_t base_pvr = CPU_POWERPC_POWER_SERVER_MASK & mfpvr();
+ ret = (base_pvr == CPU_POWERPC_POWER8E_BASE) ||
+ (base_pvr == CPU_POWERPC_POWER8NVL_BASE) ||
+ (base_pvr == CPU_POWERPC_POWER8_BASE);
+ }
+#endif /* TARGET_PPC64 */
+ return ret;
+}
+
static int parse_cap_ppc_safe_cache(struct kvm_ppc_cpu_char c)
{
+ bool l1d_thread_priv_req = !kvmppc_power8_host();
+
if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_L1D_FLUSH_PR) {
return 2;
- } else if ((c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) &&
+ } else if ((!l1d_thread_priv_req ||
+ c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) &&
(c.character & c.character_mask
& (H_CPU_CHAR_L1D_FLUSH_ORI30 | H_CPU_CHAR_L1D_FLUSH_TRIG2))) {
return 1;
s->exception_index = POWERPC_EXCP_NONE;
env->error_code = 0;
-#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
- env->vpa_addr = 0;
- env->slb_shadow_addr = 0;
- env->slb_shadow_size = 0;
- env->dtl_addr = 0;
- env->dtl_size = 0;
-#endif /* TARGET_PPC64 */
-
for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
ppc_spr_t *spr = &env->spr_cb[i];
--- /dev/null
+============================================
+Acceptance tests using the Avocado Framework
+============================================
+
+This directory contains functional tests, also known as acceptance
+level tests. They're usually higher level, and may interact with
+external resources and with various guest operating systems.
+
+For more information, please refer to ``docs/devel/testing.rst``,
+section "Acceptance tests using the Avocado Framework".
--- /dev/null
+# Test class and utilities for functional tests
+#
+# Copyright (c) 2018 Red Hat, Inc.
+#
+# Author:
+# Cleber Rosa <crosa@redhat.com>
+#
+# This work is licensed under the terms of the GNU GPL, version 2 or
+# later. See the COPYING file in the top-level directory.
+
+import os
+import sys
+
+import avocado
+
+SRC_ROOT_DIR = os.path.dirname(os.path.dirname(os.path.dirname(__file__)))
+SRC_ROOT_DIR = os.path.abspath(os.path.dirname(SRC_ROOT_DIR))
+sys.path.append(os.path.join(SRC_ROOT_DIR, 'scripts'))
+
+from qemu import QEMUMachine
+
+def is_readable_executable_file(path):
+ return os.path.isfile(path) and os.access(path, os.R_OK | os.X_OK)
+
+
+def pick_default_qemu_bin():
+ """
+ Picks the path of a QEMU binary, starting either in the current working
+ directory or in the source tree root directory.
+ """
+ arch = os.uname()[4]
+ qemu_bin_relative_path = os.path.join("%s-softmmu" % arch,
+ "qemu-system-%s" % arch)
+ if is_readable_executable_file(qemu_bin_relative_path):
+ return qemu_bin_relative_path
+
+ qemu_bin_from_src_dir_path = os.path.join(SRC_ROOT_DIR,
+ qemu_bin_relative_path)
+ if is_readable_executable_file(qemu_bin_from_src_dir_path):
+ return qemu_bin_from_src_dir_path
+
+
+class Test(avocado.Test):
+ def setUp(self):
+ self.vm = None
+ self.qemu_bin = self.params.get('qemu_bin',
+ default=pick_default_qemu_bin())
+ if self.qemu_bin is None:
+ self.cancel("No QEMU binary defined or found in the source tree")
+ self.vm = QEMUMachine(self.qemu_bin)
+
+ def tearDown(self):
+ if self.vm is not None:
+ self.vm.shutdown()
--- /dev/null
+# Functional test that boots a Linux kernel and checks the console
+#
+# Copyright (c) 2018 Red Hat, Inc.
+#
+# Author:
+# Cleber Rosa <crosa@redhat.com>
+#
+# This work is licensed under the terms of the GNU GPL, version 2 or
+# later. See the COPYING file in the top-level directory.
+
+import logging
+
+from avocado_qemu import Test
+
+
+class BootLinuxConsole(Test):
+ """
+ Boots a x86_64 Linux kernel and checks that the console is operational
+ and the kernel command line is properly passed from QEMU to the kernel
+
+ :avocado: enable
+ :avocado: tags=x86_64
+ """
+
+ timeout = 60
+
+ def test(self):
+ kernel_url = ('https://mirrors.kernel.org/fedora/releases/28/'
+ 'Everything/x86_64/os/images/pxeboot/vmlinuz')
+ kernel_hash = '238e083e114c48200f80d889f7e32eeb2793e02a'
+ kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
+
+ self.vm.set_machine('pc')
+ self.vm.set_console()
+ kernel_command_line = 'console=ttyS0'
+ self.vm.add_args('-kernel', kernel_path,
+ '-append', kernel_command_line)
+ self.vm.launch()
+ console = self.vm.console_socket.makefile()
+ console_logger = logging.getLogger('console')
+ while True:
+ msg = console.readline()
+ console_logger.debug(msg.strip())
+ if 'Kernel command line: %s' % kernel_command_line in msg:
+ break
+ if 'Kernel panic - not syncing' in msg:
+ self.fail("Kernel panic reached")
--- /dev/null
+# Version check example test
+#
+# Copyright (c) 2018 Red Hat, Inc.
+#
+# Author:
+# Cleber Rosa <crosa@redhat.com>
+#
+# This work is licensed under the terms of the GNU GPL, version 2 or
+# later. See the COPYING file in the top-level directory.
+
+
+from avocado_qemu import Test
+
+
+class Version(Test):
+ """
+ :avocado: enable
+ :avocado: tags=quick
+ """
+ def test_qmp_human_info_version(self):
+ self.vm.launch()
+ res = self.vm.command('human-monitor-command',
+ command_line='info version')
+ self.assertRegexpMatches(res, r'^(\d+\.\d+\.\d)')
--- /dev/null
+# Simple functional tests for VNC functionality
+#
+# Copyright (c) 2018 Red Hat, Inc.
+#
+# Author:
+# Cleber Rosa <crosa@redhat.com>
+#
+# This work is licensed under the terms of the GNU GPL, version 2 or
+# later. See the COPYING file in the top-level directory.
+
+from avocado_qemu import Test
+
+
+class Vnc(Test):
+ """
+ :avocado: enable
+ :avocado: tags=vnc,quick
+ """
+ def test_no_vnc(self):
+ self.vm.add_args('-nodefaults', '-S')
+ self.vm.launch()
+ self.assertFalse(self.vm.qmp('query-vnc')['return']['enabled'])
+
+ def test_no_vnc_change_password(self):
+ self.vm.add_args('-nodefaults', '-S')
+ self.vm.launch()
+ self.assertFalse(self.vm.qmp('query-vnc')['return']['enabled'])
+ set_password_response = self.vm.qmp('change',
+ device='vnc',
+ target='password',
+ arg='new_password')
+ self.assertIn('error', set_password_response)
+ self.assertEqual(set_password_response['error']['class'],
+ 'GenericError')
+ self.assertEqual(set_password_response['error']['desc'],
+ 'Could not set password')
+
+ def test_vnc_change_password_requires_a_password(self):
+ self.vm.add_args('-nodefaults', '-S', '-vnc', ':0')
+ self.vm.launch()
+ self.assertTrue(self.vm.qmp('query-vnc')['return']['enabled'])
+ set_password_response = self.vm.qmp('change',
+ device='vnc',
+ target='password',
+ arg='new_password')
+ self.assertIn('error', set_password_response)
+ self.assertEqual(set_password_response['error']['class'],
+ 'GenericError')
+ self.assertEqual(set_password_response['error']['desc'],
+ 'Could not set password')
+
+ def test_vnc_change_password(self):
+ self.vm.add_args('-nodefaults', '-S', '-vnc', ':0,password')
+ self.vm.launch()
+ self.assertTrue(self.vm.qmp('query-vnc')['return']['enabled'])
+ set_password_response = self.vm.qmp('change',
+ device='vnc',
+ target='password',
+ arg='new_password')
+ self.assertEqual(set_password_response['return'], {})
projects / mirror_qemu.git / commitdiff