]> git.proxmox.com Git - mirror_ubuntu-kernels.git/commitdiff
Merge tag 'armsoc-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/arm...
authorLinus Torvalds <torvalds@linux-foundation.org>
Mon, 11 Sep 2017 03:54:48 +0000 (20:54 -0700)
committerLinus Torvalds <torvalds@linux-foundation.org>
Mon, 11 Sep 2017 03:54:48 +0000 (20:54 -0700)
Pull ARM/arm64 Devicetree updates from Olof Johansson:
 "As usual, device tree updates is the bulk of our material in this
  merge window. This time around, 559 patches affecting both 32- and
  64-bit platforms.

  Changes are too many to list individually, but some of the larger
  ones:

  New platform/SoC support:

   - Automotive:
     + Renesas R-Car D3 (R8A77995)
     + TI DT76x
     + MediaTek mt2712e
   - Communication-oriented:
     + Qualcomm IPQ8074
     + Broadcom Stingray
     + Marvell Armada 8080
   - Set top box:
     + Uniphier PXs3

  Besides some vendor reference boards for the SoC above, there are also
  several new boards/machines:

   - TI AM335x Moxa UC-8100-ME-T open platform
   - TI AM57xx Beaglebone X15 Rev C
   - Microchip/Atmel sama5d27 SoM1 EK
   - Broadcom Raspberry Pi Zero W
   - Gemini-based D-Link DIR-685 router
   - Freescale i.MX6:
     + Toradex Apalis module + Apalis and Ixora carrier boards
     + Engicam GEAM6UL Starter Kit
   - Freescale i.MX53-based Beckhoff CX9020 Embedded PC
   - Mediatek mt7623-based BananaPi R2
   - Several Allwinner-based single-board computers:
  + Cubietruck plus
  + Bananapi M3, M2M and M64
  + NanoPi A64
  + A64-OLinuXino
  + Pine64
   - Rockchip RK3328 Pine64/Rock64 board support
   - Rockchip RK3399 boards:
  + RK3399 Sapphire module on Excavator carrier (RK3399 reference design)
  + Theobroma Systems RK3399-Q7 SoM
   - ZTE ZX296718 PCBOX Board"

* tag 'armsoc-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (559 commits)
  ARM: dts: at91: at91sam9g45: add AC97
  arm64: dts: marvell: mcbin: enable more networking ports
  arm64: dts: marvell: add a reference to the sysctrl syscon in the ppv2 node
  arm64: dts: marvell: add TX interrupts for PPv2.2
  arm64: dts: uniphier: add PXs3 SoC support
  ARM: dts: uniphier: add pinctrl groups of ethernet phy mode
  ARM: dts: uniphier: fix size of sdctrl nodes
  ARM: dts: uniphier: add AIDET nodes
  arm64: dts: uniphier: fix size of sdctrl node
  arm64: dts: uniphier: add AIDET nodes
  Revert "ARM: dts: sun8i: h3: Enable dwmac-sun8i on the Beelink X2"
  arm64: dts: uniphier: add reset controller node of analog amplifier
  arm64: dts: marvell: add Device Tree files for Armada-8KP
  arm64: dts: rockchip: add Haikou baseboard with RK3399-Q7 SoM
  arm64: dts: rockchip: add RK3399-Q7 (Puma) SoM
  dt-bindings: add rk3399-q7 SoM
  ARM: dts: rockchip: enable usb for rv1108-evb
  ARM: dts: rockchip: add usb nodes for rv1108 SoCs
  dt-bindings: update grf-binding for rv1108 SoCs
  ARM: dts: aspeed-g4: fix AHB window size of the SMC controllers
  ...

19 files changed:
1  2 
Documentation/devicetree/bindings/arm/amlogic.txt
Documentation/devicetree/bindings/arm/omap/omap.txt
Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt
Documentation/devicetree/bindings/dma/ti-edma.txt
Documentation/devicetree/bindings/net/mediatek-net.txt
Documentation/devicetree/bindings/pci/mvebu-pci.txt
Documentation/devicetree/bindings/vendor-prefixes.txt
arch/arm/boot/dts/dra71-evm.dts
arch/arm/boot/dts/dra72-evm-revc.dts
arch/arm/boot/dts/imx25.dtsi
arch/arm/boot/dts/imx7d-sdb.dts
arch/arm/boot/dts/sama5d2.dtsi
arch/arm64/Kconfig.platforms
arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
arch/arm64/boot/dts/renesas/salvator-common.dtsi
arch/arm64/boot/dts/rockchip/rk3328-evb.dts
arch/arm64/boot/dts/rockchip/rk3328.dtsi
arch/arm64/boot/dts/rockchip/rk3399.dtsi

index 1d1168b805cc8ab2e9607be5dd1068d391d89ff2,97ffae78df8f1bc7db40cacf95fdbd2eaf5d404f..214eaa9a6683861fd529d2af6fb84e361b27d80d
@@@ -16,15 -13,13 +16,17 @@@ Required properties
        order. These are fe_int0, fe_int1 and fe_int2.
  - clocks: the clock used by the core
  - clock-names: the names of the clock listed in the clocks property. These are
 -      "ethif", "esw", "gp2", "gp1"
 +      "ethif", "esw", "gp2", "gp1" : For MT2701 and MT7623 SoC
 +        "ethif", "esw", "gp0", "gp1", "gp2", "sgmii_tx250m", "sgmii_rx250m",
 +      "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", "eth2pll" : For MT7622 SoC
  - power-domains: phandle to the power domain that the ethernet is part of
- - resets: Should contain a phandle to the ethsys reset signal
- - reset-names: Should contain the reset signal name "eth"
+ - resets: Should contain phandles to the ethsys reset signals
+ - reset-names: Should contain the names of reset signal listed in the resets
+               property
+               These are "fe", "gmac" and "ppe"
  - mediatek,ethsys: phandle to the syscon node that handles the port setup
 +- mediatek,sgmiisys: phandle to the syscon node that handles the SGMII setup
 +      which is required for those SoCs equipped with SGMII such as MT7622 SoC.
  - mediatek,pctl: phandle to the syscon node that handles the ports slew rate
        and driver current
  
index 127ae1f53e5a2d5b4da6893efc7fba898a14fd27,e5af2e8461cff177c1750caa191c4430516ed58b..6173af6885f86731a9e81182737afc0a185cd212
@@@ -274,9 -283,10 +274,9 @@@ pcie-controller 
                marvell,pcie-port = <2>;
                marvell,pcie-lane = <0>;
                clocks = <&gateclk 26>;
 -              status = "disabled";
        };
  
-       pcie@10,0 {
+       pcie@a,0 {
                device_type = "pci";
                assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
                reg = <0x5000 0 0 0 0>;
Simple merge
index 6f9b6f31437efeb3009825cd205d06630e5c74b1,670c9c3e6cf0b618a64c2064a9ddc015fbe9abed..bf588d00728d1973c3426f09421dc5c2bbb5bbe0
                ti,min-output-impedance;
                interrupt-parent = <&gpio6>;
                interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
 +              ti,dp83867-rxctrl-strap-quirk;
        };
  };
+ &mmc1 {
+       pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
+       pinctrl-0 = <&mmc1_pins_default>;
+       pinctrl-1 = <&mmc1_pins_hs>;
+       pinctrl-2 = <&mmc1_pins_sdr12>;
+       pinctrl-3 = <&mmc1_pins_sdr25>;
+       pinctrl-4 = <&mmc1_pins_sdr50>;
+       pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>;
+       pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
+       vqmmc-supply = <&ldo1_reg>;
+ };
+ &mmc2 {
+       pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
+       pinctrl-0 = <&mmc2_pins_default>;
+       pinctrl-1 = <&mmc2_pins_hs>;
+       pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;
+       pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>;
+       vmmc-supply = <&evm_1v8_sw>;
+ };
Simple merge
index 0a24d1bf3c393463148919e685a879df39af58ef,0db7bda0ccb710f6d30fe4977e8c0fcdc64a1a4e..44637cabcc566d402847992607984f9736db5a27
                >;
        };
  
-       pinctrl_pwm1: pwm1grp {
+       pinctrl_backlight: backlightgrp {
                fsl,pins = <
-                       MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT              0x110b0
+                       MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1             0x110b0
                >;
 -
 -              pinctrl_spi4: spi4grp {
 -                      fsl,pins = <
 -                              MX7D_PAD_GPIO1_IO09__GPIO1_IO9  0x59
 -                              MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59
 -                              MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59
 -                      >;
 -              };
        };
  };
Simple merge
Simple merge
index b9f36dad17e6dda378c486e98e202aaac00234ab,86605ae7b6f5de536696ee23242cf64458462cf0..8e6a6543175673d6fd9e3d7e5d370b29ac7a2c50
                stdout-path = "serial2:1500000n8";
        };
  
+       dc_12v: dc-12v {
+               compatible = "regulator-fixed";
+               regulator-name = "dc_12v";
+               regulator-always-on;
+               regulator-boot-on;
+               regulator-min-microvolt = <12000000>;
+               regulator-max-microvolt = <12000000>;
+       };
+       vcc_sys: vcc-sys {
+               compatible = "regulator-fixed";
+               regulator-name = "vcc_sys";
+               regulator-always-on;
+               regulator-boot-on;
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               vin-supply = <&dc_12v>;
+       };
++
 +      vcc_phy: vcc-phy-regulator {
 +              compatible = "regulator-fixed";
 +              regulator-name = "vcc_phy";
 +              regulator-always-on;
 +              regulator-boot-on;
 +      };
 +};
 +
 +&gmac2phy {
 +      phy-supply = <&vcc_phy>;
 +      clock_in_out = "output";
 +      assigned-clocks = <&cru SCLK_MAC2PHY_SRC>;
 +      assigned-clock-rate = <50000000>;
 +      assigned-clocks = <&cru SCLK_MAC2PHY>;
 +      assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
 +      status = "okay";
  };
  
+ &i2c1 {
+       status = "okay";
+       rk805: rk805@18 {
+               compatible = "rockchip,rk805";
+               reg = <0x18>;
+               interrupt-parent = <&gpio2>;
+               interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+               #clock-cells = <1>;
+               clock-output-names = "xin32k", "rk805-clkout2";
+               gpio-controller;
+               #gpio-cells = <2>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pmic_int_l>;
+               rockchip,system-power-controller;
+               wakeup-source;
+               vcc1-supply = <&vcc_sys>;
+               vcc2-supply = <&vcc_sys>;
+               vcc3-supply = <&vcc_sys>;
+               vcc4-supply = <&vcc_sys>;
+               vcc5-supply = <&vcc_io>;
+               vcc6-supply = <&vcc_io>;
+               regulators {
+                       vdd_logic: DCDC_REG1 {
+                               regulator-name = "vdd_logic";
+                               regulator-min-microvolt = <712500>;
+                               regulator-max-microvolt = <1450000>;
+                               regulator-always-on;
+                               regulator-boot-on;
+                               regulator-state-mem {
+                                       regulator-on-in-suspend;
+                                       regulator-suspend-microvolt = <1000000>;
+                               };
+                       };
+                       vdd_arm: DCDC_REG2 {
+                               regulator-name = "vdd_arm";
+                               regulator-min-microvolt = <712500>;
+                               regulator-max-microvolt = <1450000>;
+                               regulator-always-on;
+                               regulator-boot-on;
+                               regulator-state-mem {
+                                       regulator-on-in-suspend;
+                                       regulator-suspend-microvolt = <950000>;
+                               };
+                       };
+                       vcc_ddr: DCDC_REG3 {
+                               regulator-name = "vcc_ddr";
+                               regulator-always-on;
+                               regulator-boot-on;
+                               regulator-state-mem {
+                                       regulator-on-in-suspend;
+                               };
+                       };
+                       vcc_io: DCDC_REG4 {
+                               regulator-name = "vcc_io";
+                               regulator-min-microvolt = <3300000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-always-on;
+                               regulator-boot-on;
+                               regulator-state-mem {
+                                       regulator-on-in-suspend;
+                                       regulator-suspend-microvolt = <3300000>;
+                               };
+                       };
+                       vcc_18: LDO_REG1 {
+                               regulator-name = "vcc_18";
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <1800000>;
+                               regulator-always-on;
+                               regulator-boot-on;
+                               regulator-state-mem {
+                                       regulator-on-in-suspend;
+                                       regulator-suspend-microvolt = <1800000>;
+                               };
+                       };
+                       vcc18_emmc: LDO_REG2 {
+                               regulator-name = "vcc18_emmc";
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <1800000>;
+                               regulator-always-on;
+                               regulator-boot-on;
+                               regulator-state-mem {
+                                       regulator-on-in-suspend;
+                                       regulator-suspend-microvolt = <1800000>;
+                               };
+                       };
+                       vdd_10: LDO_REG3 {
+                               regulator-name = "vdd_10";
+                               regulator-min-microvolt = <1000000>;
+                               regulator-max-microvolt = <1000000>;
+                               regulator-always-on;
+                               regulator-boot-on;
+                               regulator-state-mem {
+                                       regulator-on-in-suspend;
+                                       regulator-suspend-microvolt = <1000000>;
+                               };
+                       };
+               };
+       };
+ };
+ &pinctrl {
+       pmic {
+               pmic_int_l: pmic-int-l {
+                       rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
+               };
+       };
+ };
+ &tsadc {
+       status = "okay";
+ };
  &uart2 {
        status = "okay";
  };
index d48bf5d9f8bd04c03d21b9f2d7be42a654b0c15f,41c1ae0ff25f7b8d0e579fd5c359335ccb01c95f..6d615cb6e64d07cebcfa0a7ecebf04b8afb152b2
                status = "disabled";
        };
  
 +      gmac2phy: ethernet@ff550000 {
 +              compatible = "rockchip,rk3328-gmac";
 +              reg = <0x0 0xff550000 0x0 0x10000>;
 +              rockchip,grf = <&grf>;
 +              interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 +              interrupt-names = "macirq";
 +              clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
 +                       <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
 +                       <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
 +                       <&cru SCLK_MAC2PHY_OUT>;
 +              clock-names = "stmmaceth", "mac_clk_rx",
 +                            "mac_clk_tx", "clk_mac_ref",
 +                            "aclk_mac", "pclk_mac",
 +                            "clk_macphy";
 +              resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>;
 +              reset-names = "stmmaceth", "mac-phy";
 +              phy-mode = "rmii";
 +              phy-handle = <&phy>;
 +              status = "disabled";
 +
 +              mdio {
 +                      compatible = "snps,dwmac-mdio";
 +                      #address-cells = <1>;
 +                      #size-cells = <0>;
 +
 +                      phy: phy@0 {
 +                              compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
 +                              reg = <0>;
 +                              clocks = <&cru SCLK_MAC2PHY_OUT>;
 +                              resets = <&cru SRST_MACPHY>;
 +                              pinctrl-names = "default";
 +                              pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
 +                              phy-is-integrated;
 +                      };
 +              };
 +      };
 +
+       usb20_otg: usb@ff580000 {
+               compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
+                            "snps,dwc2";
+               reg = <0x0 0xff580000 0x0 0x40000>;
+               interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru HCLK_OTG>;
+               clock-names = "otg";
+               dr_mode = "otg";
+               g-np-tx-fifo-size = <16>;
+               g-rx-fifo-size = <280>;
+               g-tx-fifo-size = <256 128 128 64 32 16>;
+               g-use-dma;
+               phys = <&u2phy_otg>;
+               phy-names = "usb2-phy";
+               status = "disabled";
+       };
+       usb_host0_ehci: usb@ff5c0000 {
+               compatible = "generic-ehci";
+               reg = <0x0 0xff5c0000 0x0 0x10000>;
+               interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru HCLK_HOST0>, <&u2phy>;
+               clock-names = "usbhost", "utmi";
+               phys = <&u2phy_host>;
+               phy-names = "usb";
+               status = "disabled";
+       };
+       usb_host0_ohci: usb@ff5d0000 {
+               compatible = "generic-ohci";
+               reg = <0x0 0xff5d0000 0x0 0x10000>;
+               interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru HCLK_HOST0>, <&u2phy>;
+               clock-names = "usbhost", "utmi";
+               phys = <&u2phy_host>;
+               phy-names = "usb";
+               status = "disabled";
+       };
        gic: interrupt-controller@ff811000 {
                compatible = "arm,gic-400";
                #interrupt-cells = <3>;