arm64: dts: uniphier: add reset-names to NAND controller node

The Denali NAND controller IP has separate reset control for the
controller core and registers.

Add the reset-names, and one more phandle accordingly. This is the
approved DT-binding.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
index 8ec40a0b8b1ef05e1b4dc4ba142ecbfd0564c3fd..5b18bda9c5a6f4ba6ff5be111715124c8b85cd6f 100644 (file)
--- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
@@ -633,7 +633,8 @@
                        pinctrl-0 = <&pinctrl_nand>;
                        clock-names = "nand", "nand_x", "ecc";
                        clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
-                       resets = <&sys_rst 2>;
+                       reset-names = "nand", "reg";
+                       resets = <&sys_rst 2>, <&sys_rst 2>;
                };
        };
 };

diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
index b658f2b641e2933abb35ae19d5d8220b8b481371..f2dc5f695020124ff856da335f5756e94e3fb53f 100644 (file)
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
@@ -937,7 +937,8 @@
                        pinctrl-0 = <&pinctrl_nand>;
                        clock-names = "nand", "nand_x", "ecc";
                        clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
-                       resets = <&sys_rst 2>;
+                       reset-names = "nand", "reg";
+                       resets = <&sys_rst 2>, <&sys_rst 2>;
                };
        };
 };

diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
index d6f6cee4d549199481c6d030fc0f9e1db012c2c7..73e7e1203b098d10cb49536197382b07da2b2539 100644 (file)
--- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
@@ -795,7 +795,8 @@
                        pinctrl-0 = <&pinctrl_nand>;
                        clock-names = "nand", "nand_x", "ecc";
                        clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
-                       resets = <&sys_rst 2>;
+                       reset-names = "nand", "reg";
+                       resets = <&sys_rst 2>, <&sys_rst 2>;
                };
        };
 };