open_flags = flags & ~(BDRV_O_SNAPSHOT | BDRV_O_NO_BACKING);
/*
- * Snapshots should be writeable.
+ * Snapshots should be writable.
*/
if (bs->is_temporary) {
open_flags |= BDRV_O_RDWR;
return hval;
}
-static inline int is_data_obj_writeable(SheepdogInode *inode, unsigned int idx)
+static inline int is_data_obj_writable(SheepdogInode *inode, unsigned int idx)
{
return inode->vdi_id == inode->data_vdi_id[idx];
}
create = 1;
} else if (acb->aiocb_type == AIOCB_WRITE_UDATA
- && !is_data_obj_writeable(inode, idx)) {
+ && !is_data_obj_writable(inode, idx)) {
/* Copy-On-Write */
create = 1;
old_oid = oid;
{
TRACE(EEPROM, logout("val=0x%02x\n", val));
- /* mask unwriteable bits */
+ /* mask unwritable bits */
#if 0
val = SET_MASKED(val, 0x31, eeprom->value);
#endif
uint8_t tick;
uint8_t address;
uint8_t command;
- uint8_t writeable;
+ uint8_t writable;
uint8_t eecs;
uint8_t eesk;
VMSTATE_UINT8(tick, eeprom_t),
VMSTATE_UINT8(address, eeprom_t),
VMSTATE_UINT8(command, eeprom_t),
- VMSTATE_UINT8(writeable, eeprom_t),
+ VMSTATE_UINT8(writable, eeprom_t),
VMSTATE_UINT8(eecs, eeprom_t),
VMSTATE_UINT8(eesk, eeprom_t),
address = 0x0;
} else if (eeprom->eecs && ! eecs) {
/* End chip select cycle. This triggers write / erase. */
- if (eeprom->writeable) {
+ if (eeprom->writable) {
uint8_t subcommand = address >> (eeprom->addrbits - 2);
if (command == 0 && subcommand == 2) {
/* Erase all. */
switch (address >> (eeprom->addrbits - 2)) {
case 0:
logout("write disable command\n");
- eeprom->writeable = 0;
+ eeprom->writable = 0;
break;
case 1:
logout("write all command\n");
break;
case 3:
logout("write enable command\n");
- eeprom->writeable = 1;
+ eeprom->writable = 1;
break;
}
} else {
pci_set_word(dev->wmask + msi_data_off(dev, msi64bit), 0xffff);
if (msi_per_vector_mask) {
- /* Make mask bits 0 to nr_vectors - 1 writeable. */
+ /* Make mask bits 0 to nr_vectors - 1 writable. */
pci_set_long(dev->wmask + msi_mask_off(dev, msi64bit),
0xffffffff >> (PCI_MSI_VECTORS_MAX - nr_vectors));
}
pci_set_long(config + MSIX_PBA_OFFSET, (bar_size + MSIX_PAGE_PENDING) |
bar_nr);
pdev->msix_cap = config_offset;
- /* Make flags bit writeable. */
+ /* Make flags bit writable. */
pdev->wmask[config_offset + MSIX_CONTROL_OFFSET] |= MSIX_ENABLE_MASK |
MSIX_MASKALL_MASK;
return 0;
dev->irq_state = 0;
pci_update_irq_status(dev);
pci_device_deassert_intx(dev);
- /* Clear all writeable bits */
+ /* Clear all writable bits */
pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
pci_get_word(dev->wmask + PCI_COMMAND) |
pci_get_word(dev->w1cmask + PCI_COMMAND));
wmask = ~(size - 1);
addr = pci_bar(pci_dev, region_num);
if (region_num == PCI_ROM_SLOT) {
- /* ROM enable bit is writeable */
+ /* ROM enable bit is writable */
wmask |= PCI_ROM_ADDRESS_ENABLE;
}
pci_set_long(pci_dev->config + addr, type);
if (!offset)
return;
pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
- /* Make capability writeable again */
+ /* Make capability writable again */
memset(pdev->wmask + offset, 0xff, size);
memset(pdev->w1cmask + offset, 0, size);
/* Clear cmask as device-specific registers can't be checked */
/* PCI config space */
uint8_t *config;
- /* Used to enable config checks on load. Note that writeable bits are
+ /* Used to enable config checks on load. Note that writable bits are
* never checked even if set in cmask. */
uint8_t *cmask;
s->currCPlusTxDesc = 0;
}
- /* mask unwriteable bits */
+ /* mask unwritable bits */
val = SET_MASKED(val, 0xe3, s->bChipCmdState);
/* Deassert reset pin before next read */
s->cplus_enabled = 1;
- /* mask unwriteable bits */
+ /* mask unwritable bits */
val = SET_MASKED(val, 0xff84, s->CpCmd);
s->CpCmd = val;
return ret;
}
-static int rtl8139_config_writeable(RTL8139State *s)
+static int rtl8139_config_writable(RTL8139State *s)
{
if (s->Cfg9346 & Cfg9346_Unlock)
{
DPRINTF("BasicModeCtrl register write(w) val=0x%04x\n", val);
- /* mask unwriteable bits */
+ /* mask unwritable bits */
uint32_t mask = 0x4cff;
- if (1 || !rtl8139_config_writeable(s))
+ if (1 || !rtl8139_config_writable(s))
{
/* Speed setting and autonegotiation enable bits are read-only */
mask |= 0x3000;
DPRINTF("BasicModeStatus register write(w) val=0x%04x\n", val);
- /* mask unwriteable bits */
+ /* mask unwritable bits */
val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
s->BasicModeStatus = val;
DPRINTF("Cfg9346 write val=0x%02x\n", val);
- /* mask unwriteable bits */
+ /* mask unwritable bits */
val = SET_MASKED(val, 0x31, s->Cfg9346);
uint32_t opmode = val & 0xc0;
DPRINTF("Config0 write val=0x%02x\n", val);
- if (!rtl8139_config_writeable(s))
+ if (!rtl8139_config_writable(s)) {
return;
+ }
- /* mask unwriteable bits */
+ /* mask unwritable bits */
val = SET_MASKED(val, 0xf8, s->Config0);
s->Config0 = val;
DPRINTF("Config1 write val=0x%02x\n", val);
- if (!rtl8139_config_writeable(s))
+ if (!rtl8139_config_writable(s)) {
return;
+ }
- /* mask unwriteable bits */
+ /* mask unwritable bits */
val = SET_MASKED(val, 0xC, s->Config1);
s->Config1 = val;
DPRINTF("Config3 write val=0x%02x\n", val);
- if (!rtl8139_config_writeable(s))
+ if (!rtl8139_config_writable(s)) {
return;
+ }
- /* mask unwriteable bits */
+ /* mask unwritable bits */
val = SET_MASKED(val, 0x8F, s->Config3);
s->Config3 = val;
DPRINTF("Config4 write val=0x%02x\n", val);
- if (!rtl8139_config_writeable(s))
+ if (!rtl8139_config_writable(s)) {
return;
+ }
- /* mask unwriteable bits */
+ /* mask unwritable bits */
val = SET_MASKED(val, 0x0a, s->Config4);
s->Config4 = val;
DPRINTF("Config5 write val=0x%02x\n", val);
- /* mask unwriteable bits */
+ /* mask unwritable bits */
val = SET_MASKED(val, 0x80, s->Config5);
s->Config5 = val;
{
DPRINTF("RxConfig write val=0x%08x\n", val);
- /* mask unwriteable bits */
+ /* mask unwritable bits */
val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
s->RxConfig = val;
{
DPRINTF("IntrMask write(w) val=0x%04x\n", val);
- /* mask unwriteable bits */
+ /* mask unwritable bits */
val = SET_MASKED(val, 0x1e00, s->IntrMask);
s->IntrMask = val;
#else
uint16_t newStatus = s->IntrStatus & ~val;
- /* mask unwriteable bits */
+ /* mask unwritable bits */
newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
/* writing 1 to interrupt status register bit clears it */
{
DPRINTF("MultiIntr write(w) val=0x%04x\n", val);
- /* mask unwriteable bits */
+ /* mask unwritable bits */
val = SET_MASKED(val, 0xf000, s->MultiIntr);
s->MultiIntr = val;
#define IOPTE_PAGE 0xffffff00 /* Physical page number (PA[35:12]) */
#define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or
Viking/MXCC) */
-#define IOPTE_WRITE 0x00000004 /* Writeable */
+#define IOPTE_WRITE 0x00000004 /* Writable */
#define IOPTE_VALID 0x00000002 /* IOPTE is valid */
#define IOPTE_WAZ 0x00000001 /* Write as zeros */
.CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
.SYNCI_Step = 16,
.CCRes = 2,
- .CP0_Status_rw_bitmask = 0xF5D0FF1F, /*bit5:7 not writeable*/
+ .CP0_Status_rw_bitmask = 0xF5D0FF1F, /*bit5:7 not writable*/
.CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
.SEGBITS = 40,
.PABITS = 40,