drm/i915/cdclk: Reorder bxt_sanitize_cdclk()

Make the sequence of steps in bxt_sanitize_cdclk() more logical by
grouping things related to the check on the value of CDCLK_CTL into a
single "block". Also, this will make an upcoming change replacing that
block with a single function call easier to follow.

v2:
  - Improve body of commit message to be more self-contained.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240105140538.183553-4-gustavo.sousa@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index b9354ad46fee98be70d37bbae11c0fe3d7753145..fbe9aba41c35d3253ee1e04f2435ccb4fb41ff3a 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2060,13 +2060,23 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
            dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass)
                goto sanitize;
 
-       /* DPLL okay; verify the cdclock
-        *
+       /* Make sure this is a legal cdclk value for the platform */
+       cdclk = bxt_calc_cdclk(dev_priv, dev_priv->display.cdclk.hw.cdclk);
+       if (cdclk != dev_priv->display.cdclk.hw.cdclk)
+               goto sanitize;
+
+       /* Make sure the VCO is correct for the cdclk */
+       vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
+       if (vco != dev_priv->display.cdclk.hw.vco)
+               goto sanitize;
+
+       /*
         * Some BIOS versions leave an incorrect decimal frequency value and
         * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
         * so sanitize this register.
         */
        cdctl = intel_de_read(dev_priv, CDCLK_CTL);
+
        /*
         * Let's ignore the pipe field, since BIOS could have configured the
         * dividers both synching to an active pipe, or asynchronously
@@ -2074,16 +2084,6 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
         */
        cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE);
 
-       /* Make sure this is a legal cdclk value for the platform */
-       cdclk = bxt_calc_cdclk(dev_priv, dev_priv->display.cdclk.hw.cdclk);
-       if (cdclk != dev_priv->display.cdclk.hw.cdclk)
-               goto sanitize;
-
-       /* Make sure the VCO is correct for the cdclk */
-       vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
-       if (vco != dev_priv->display.cdclk.hw.vco)
-               goto sanitize;
-
        if (DISPLAY_VER(dev_priv) >= 20)
                expected = MDCLK_SOURCE_SEL_CDCLK_PLL;
        else