drm/i915/skl: Re-indent part of skl_ddi_calculate_wrpll()

A part of this function was indented with 2 tabs and 1 space instead of
just 2 tabs. We're going to touch that code, so start by re-indenting
it.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index ec5d2eaef43ca75dc6b61026ae3227f8e60d1084..807e15d41a1bd8eebd73f29a3f8ad43ef46f3398 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1189,69 +1189,69 @@ found:
        if (min_dco_index > 2) {
                WARN(1, "No valid values found for the given pixel clock\n");
        } else {
-                wrpll_params->central_freq = dco_central_freq[min_dco_index];
+               wrpll_params->central_freq = dco_central_freq[min_dco_index];
 
-                switch (dco_central_freq[min_dco_index]) {
-                case 9600000000ULL:
+               switch (dco_central_freq[min_dco_index]) {
+               case 9600000000ULL:
                        wrpll_params->central_freq = 0;
                        break;
-                case 9000000000ULL:
+               case 9000000000ULL:
                        wrpll_params->central_freq = 1;
                        break;
-                case 8400000000ULL:
+               case 8400000000ULL:
                        wrpll_params->central_freq = 3;
-                }
+               }
 
-                switch (candidate_p0[min_dco_index]) {
-                case 1:
+               switch (candidate_p0[min_dco_index]) {
+               case 1:
                        wrpll_params->pdiv = 0;
                        break;
-                case 2:
+               case 2:
                        wrpll_params->pdiv = 1;
                        break;
-                case 3:
+               case 3:
                        wrpll_params->pdiv = 2;
                        break;
-                case 7:
+               case 7:
                        wrpll_params->pdiv = 4;
                        break;
-                default:
+               default:
                        WARN(1, "Incorrect PDiv\n");
-                }
+               }
 
-                switch (candidate_p2[min_dco_index]) {
-                case 5:
+               switch (candidate_p2[min_dco_index]) {
+               case 5:
                        wrpll_params->kdiv = 0;
                        break;
-                case 2:
+               case 2:
                        wrpll_params->kdiv = 1;
                        break;
-                case 3:
+               case 3:
                        wrpll_params->kdiv = 2;
                        break;
-                case 1:
+               case 1:
                        wrpll_params->kdiv = 3;
                        break;
-                default:
+               default:
                        WARN(1, "Incorrect KDiv\n");
-                }
+               }
 
-                wrpll_params->qdiv_ratio = candidate_p1[min_dco_index];
-                wrpll_params->qdiv_mode =
+               wrpll_params->qdiv_ratio = candidate_p1[min_dco_index];
+               wrpll_params->qdiv_mode =
                        (wrpll_params->qdiv_ratio == 1) ? 0 : 1;
 
-                dco_freq = candidate_p0[min_dco_index] *
-                        candidate_p1[min_dco_index] *
-                        candidate_p2[min_dco_index] * afe_clock;
+               dco_freq = candidate_p0[min_dco_index] *
+                       candidate_p1[min_dco_index] *
+                       candidate_p2[min_dco_index] * afe_clock;
 
                /*
-               * Intermediate values are in Hz.
-               * Divide by MHz to match bsepc
-               */
-                wrpll_params->dco_integer = div_u64(dco_freq, (24 * MHz(1)));
-                wrpll_params->dco_fraction =
-                        div_u64(((div_u64(dco_freq, 24) -
-                                  wrpll_params->dco_integer * MHz(1)) * 0x8000), MHz(1));
+                * Intermediate values are in Hz.
+                * Divide by MHz to match bsepc
+                */
+               wrpll_params->dco_integer = div_u64(dco_freq, (24 * MHz(1)));
+               wrpll_params->dco_fraction =
+                       div_u64(((div_u64(dco_freq, 24) -
+                                 wrpll_params->dco_integer * MHz(1)) * 0x8000), MHz(1));
 
        }
 }