* Contributions after 2012-01-13 are licensed under the terms of the
* GNU GPL, version 2 or (at your option) any later version.
*/
+
#ifndef QEMU_RAW_AIO_H
#define QEMU_RAW_AIO_H
+#include "block/aio.h"
#include "qemu/coroutine.h"
#include "qemu/iov.h"
* This work is licensed under the terms of the GNU LGPL, version 2 or later.
* See the COPYING.LIB file in the top-level directory.
*/
+
#ifndef BLOCK_WRITE_THRESHOLD_H
#define BLOCK_WRITE_THRESHOLD_H
+#include "block/block_int.h"
/*
* bdrv_write_threshold_set:
#ifndef QEMU_DISAS_H
#define QEMU_DISAS_H
+#include "exec/hwaddr.h"
#ifdef NEED_CPU_H
#include "cpu.h"
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
+
#ifndef CPUTLB_H
#define CPUTLB_H
+#include "exec/cpu-common.h"
+
#if !defined(CONFIG_USER_ONLY)
/* cputlb.c */
void tlb_protect_code(ram_addr_t ram_addr);
#ifndef EXEC_ALL_H
#define EXEC_ALL_H
+#include "cpu.h"
#include "exec/tb-context.h"
#include "sysemu/cpus.h"
#ifndef IOPORT_H
#define IOPORT_H
+#include "exec/memory.h"
+
#define MAX_IOPORTS (64 * 1024)
#define IOPORTS_MASK (MAX_IOPORTS - 1)
#ifndef MEMORY_INTERNAL_H
#define MEMORY_INTERNAL_H
+#include "cpu.h"
+
#ifndef CONFIG_USER_ONLY
static inline AddressSpaceDispatch *flatview_to_dispatch(FlatView *fv)
{
#define RAM_ADDR_H
#ifndef CONFIG_USER_ONLY
+#include "cpu.h"
#include "hw/xen/xen.h"
#include "sysemu/tcg.h"
#include "exec/ramlist.h"
#ifndef SOFTMMU_SEMI_H
#define SOFTMMU_SEMI_H
+#include "cpu.h"
+
static inline uint64_t softmmu_tget64(CPUArchState *env, target_ulong addr)
{
uint64_t val;
#ifndef EXEC_TB_HASH_H
#define EXEC_TB_HASH_H
+#include "exec/cpu-defs.h"
+#include "exec/exec-all.h"
#include "qemu/xxhash.h"
#ifdef CONFIG_SOFTMMU
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
+
#ifndef THUNK_H
#define THUNK_H
#include "cpu.h"
+#include "exec/user/abitypes.h"
/* types enums definitions */
#ifndef FPU_SOFTFLOAT_MACROS_H
#define FPU_SOFTFLOAT_MACROS_H
+#include "fpu/softfloat.h"
+
/*----------------------------------------------------------------------------
| Shifts `a' right by the number of bits given in `count'. If any nonzero
| bits are shifted off, they are ``jammed'' into the least significant bit of
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
+
#ifndef HW_ACPI_PCI_H
#define HW_ACPI_PCI_H
+#include "hw/acpi/bios-linker-loader.h"
+
typedef struct AcpiMcfgInfo {
uint64_t base;
uint32_t size;
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
+
#ifndef HW_ACPI_TCO_H
#define HW_ACPI_TCO_H
+#include "exec/memory.h"
+#include "migration/vmstate.h"
/* As per ICH9 spec, the internal timer has an error of ~0.6s on every tick */
#define TCO_TICK_NSEC 600000000LL
#ifndef HW_STM32F2XX_ADC_H
#define HW_STM32F2XX_ADC_H
+#include "hw/sysbus.h"
+
#define ADC_SR 0x00
#define ADC_CR1 0x04
#define ADC_CR2 0x08
#include "hw/ide/ahci.h"
#include "sysemu/sysemu.h"
+#include "target/arm/cpu.h"
#define AW_A10_PIC_REG_BASE 0x01c20400
#include "hw/ssi/aspeed_smc.h"
#include "hw/watchdog/wdt_aspeed.h"
#include "hw/net/ftgmac100.h"
+#include "target/arm/cpu.h"
#define ASPEED_SPIS_NUM 2
#define ASPEED_WDTS_NUM 3
#include "hw/arm/bcm2835_peripherals.h"
#include "hw/intc/bcm2836_control.h"
+#include "target/arm/cpu.h"
#define TYPE_BCM283X "bcm283x"
#define BCM283X(obj) OBJECT_CHECK(BCM283XState, (obj), TYPE_BCM283X)
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
- *
*/
#ifndef EXYNOS4210_H
#define EXYNOS4210_H
-#include "exec/memory.h"
+#include "hw/sysbus.h"
#include "target/arm/cpu-qom.h"
#define EXYNOS4210_NCPUS 2
#include "hw/i2c/imx_i2c.h"
#include "hw/gpio/imx_gpio.h"
#include "exec/memory.h"
+#include "target/arm/cpu.h"
#define TYPE_FSL_IMX25 "fsl,imx25"
#define FSL_IMX25(obj) OBJECT_CHECK(FslIMX25State, (obj), TYPE_FSL_IMX25)
#include "hw/i2c/imx_i2c.h"
#include "hw/gpio/imx_gpio.h"
#include "exec/memory.h"
+#include "target/arm/cpu.h"
#define TYPE_FSL_IMX31 "fsl,imx31"
#define FSL_IMX31(obj) OBJECT_CHECK(FslIMX31State, (obj), TYPE_FSL_IMX31)
*
* This file is licensed under the GNU GPL.
*/
+
#ifndef QEMU_SHARPSL_H
#define QEMU_SHARPSL_H
+#include "exec/hwaddr.h"
+
#define zaurus_printf(format, ...) \
fprintf(stderr, "%s: " format, __func__, ##__VA_ARGS__)
#include "hw/intc/xlnx-zynqmp-ipi.h"
#include "hw/timer/xlnx-zynqmp-rtc.h"
#include "hw/cpu/cluster.h"
+#include "target/arm/cpu.h"
#define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
#define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
#ifndef HW_FDC_H
#define HW_FDC_H
+#include "exec/hwaddr.h"
+#include "hw/irq.h"
#include "qapi/qapi-types-block.h"
/* fdc.c */
/* NOR flash devices */
#include "exec/memory.h"
+#include "migration/vmstate.h"
/* pflash_cfi01.c */
#include "chardev/char-fe.h"
#include "chardev/char-serial.h"
+#include "hw/sysbus.h"
#include "ui/input.h"
/* escc.c */
#ifndef XILINX_UARTLITE_H
#define XILINX_UARTLITE_H
+#include "hw/sysbus.h"
+
static inline DeviceState *xilinx_uartlite_create(hwaddr addr,
qemu_irq irq,
Chardev *chr)
#define GENERIC_LOADER_H
#include "elf.h"
+#include "hw/qdev-core.h"
typedef struct GenericLoaderState {
/* <private> */
#include "net/net.h"
#include "hw/cris/etraxfs_dma.h"
+#include "hw/sysbus.h"
/* Instantiate an ETRAXFS Ethernet MAC. */
static inline DeviceState *
#ifndef HW_ETRAXFS_DMA_H
#define HW_ETRAXFS_DMA_H
+#include "exec/hwaddr.h"
+#include "hw/irq.h"
+
struct dma_context_metadata {
/* data descriptor md */
uint16_t metadata;
#define I2C_DDC_H
#include "hw/display/edid.h"
+#include "hw/i2c/i2c.h"
/* A simple I2C slave which just returns the contents of its EDID blob. */
struct I2CDDCState {
#ifndef HW_EMPTY_SLOT_H
#define HW_EMPTY_SLOT_H
+#include "exec/hwaddr.h"
+
/* empty_slot.c */
void empty_slot_init(hwaddr addr, uint64_t slot_size);
#define BCM2835_GPIO_H
#include "hw/sd/sd.h"
+#include "hw/sysbus.h"
typedef struct BCM2835GpioState {
SysBusDevice parent_obj;
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
+
#ifndef ASPEED_I2C_H
#define ASPEED_I2C_H
#include "hw/i2c/i2c.h"
+#include "hw/sysbus.h"
#define TYPE_ASPEED_I2C "aspeed.i2c"
#define ASPEED_I2C(obj) \
#include "cpu.h"
#include "exec/memory.h"
#include "qemu/timer.h"
+#include "target/i386/cpu-qom.h"
/* APIC Local Vector Table */
#define APIC_LVT_TIMER 0
#include "hw/hw.h"
#include "exec/memory.h"
+#include "hw/i386/ioapic.h"
#include "hw/sysbus.h"
#include "qemu/notify.h"
#ifndef ALLWINNER_A10_PIC_H
#define ALLWINNER_A10_PIC_H
+#include "hw/sysbus.h"
+
#define TYPE_AW_A10_PIC "allwinner-a10-pic"
#define AW_A10_PIC(obj) OBJECT_CHECK(AwA10PICState, (obj), TYPE_AW_A10_PIC)
#ifndef HW_INTC_HEATHROW_PIC_H
#define HW_INTC_HEATHROW_PIC_H
+#include "hw/sysbus.h"
+
#define TYPE_HEATHROW "heathrow"
#define HEATHROW(obj) OBJECT_CHECK(HeathrowState, (obj), TYPE_HEATHROW)
#include "qemu/units.h"
#include "hw/timer/mips_gictimer.h"
+#include "hw/sysbus.h"
#include "cpu.h"
/*
* GIC Specific definitions
#ifndef HW_VT82C686_H
#define HW_VT82C686_H
+#include "hw/irq.h"
+
#define TYPE_VT82C686B_SUPERIO "vt82c686b-superio"
/* vt82c686.c */
#include "hw/intc/mips_gic.h"
#include "hw/misc/mips_cpc.h"
#include "hw/misc/mips_itu.h"
+#include "target/mips/cpu.h"
#define TYPE_MIPS_CPS "mips-cps"
#define MIPS_CPS(obj) OBJECT_CHECK(MIPSCPSState, (obj), TYPE_MIPS_CPS)
#ifndef CUDA_H
#define CUDA_H
+#include "hw/misc/mos6522.h"
+
/* CUDA commands (2nd byte) */
#define CUDA_WARM_START 0x0
#define CUDA_AUTOPOLL 0x1
#ifndef MACIO_GPIO_H
#define MACIO_GPIO_H
+#include "hw/ppc/openpic.h"
+#include "hw/sysbus.h"
+
#define TYPE_MACIO_GPIO "macio-gpio"
#define MACIO_GPIO(obj) OBJECT_CHECK(MacIOGPIOState, (obj), TYPE_MACIO_GPIO)
#define MACIO_H
#include "hw/char/escc.h"
+#include "hw/ide/internal.h"
#include "hw/intc/heathrow_pic.h"
#include "hw/misc/macio/cuda.h"
#include "hw/misc/macio/gpio.h"
#include "hw/misc/macio/pmu.h"
+#include "hw/ppc/mac.h"
#include "hw/ppc/mac_dbdma.h"
#include "hw/ppc/openpic.h"
#ifndef PMU_H
#define PMU_H
+#include "hw/misc/mos6522.h"
+#include "hw/misc/macio/gpio.h"
+
/*
* PMU commands
*/
#ifndef MIPS_CMGCR_H
#define MIPS_CMGCR_H
+#include "hw/sysbus.h"
+
#define TYPE_MIPS_GCR "mips-gcr"
#define MIPS_GCR(obj) OBJECT_CHECK(MIPSGCRState, (obj), TYPE_MIPS_GCR)
#ifndef MIPS_CPC_H
#define MIPS_CPC_H
+#include "hw/sysbus.h"
+
#define CPC_ADDRSPACE_SZ 0x6000
/* CPC blocks offsets relative to base address */
* See the COPYING file in the top-level directory.
*
*/
+
#ifndef HW_MISC_PVPANIC_H
#define HW_MISC_PVPANIC_H
+#include "qom/object.h"
+
#define TYPE_PVPANIC "pvpanic"
#define PVPANIC_IOPORT_PROP "ioport"
#include "net/net.h"
#include "qemu/fifo8.h"
#include "hw/net/mii.h"
+#include "hw/sysbus.h"
#define TYPE_AW_EMAC "allwinner-emac"
#define AW_EMAC(obj) OBJECT_CHECK(AwEmacState, (obj), TYPE_AW_EMAC)
#include "net/net.h"
#include "hw/net/pcnet.h"
+#include "hw/sysbus.h"
#define TYPE_LANCE "lance"
#define SYSBUS_PCNET(obj) \
#ifndef CHRP_NVRAM_H
#define CHRP_NVRAM_H
+#include "qemu/bswap.h"
+
/* OpenBIOS NVRAM partition */
typedef struct {
uint8_t signature;
#ifndef HW_PCI_HOST_SABRE_H
#define HW_PCI_HOST_SABRE_H
+#include "hw/pci/pci.h"
+#include "hw/pci/pci_host.h"
#include "hw/sparc/sun4u_iommu.h"
#define MAX_IVEC 0x40
#define UNINORTH_H
#include "hw/hw.h"
-
+#include "hw/pci/pci_host.h"
#include "hw/ppc/openpic.h"
/* UniNorth version */
#define QEMU_PCIE_AER_H
#include "hw/hw.h"
+#include "hw/pci/pci_regs.h"
/* definitions which PCIExpressDevice uses */
#define PPC_PNV_CORE_H
#include "hw/cpu/core.h"
+#include "target/ppc/cpu.h"
#define TYPE_PNV_CORE "powernv-cpu-core"
#define PNV_CORE(obj) \
#ifndef PPC4XX_H
#define PPC4XX_H
+#include "hw/ppc/ppc.h"
+#include "exec/cpu-common.h"
+#include "exec/memory.h"
+
/* PowerPC 4xx core initialization */
PowerPCCPU *ppc4xx_init(const char *cpu_model,
clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
#ifndef HW_SPAPR_IRQ_H
#define HW_SPAPR_IRQ_H
+#include "hw/irq.h"
+#include "target/ppc/cpu-qom.h"
+
/*
* IRQ range offsets per device type
*/
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
+#include "hw/ppc/spapr.h"
#include "sysemu/dma.h"
#define TYPE_VIO_SPAPR_DEVICE "vio-spapr-device"
#ifndef PPC_SPAPR_XIVE_H
#define PPC_SPAPR_XIVE_H
+#include "hw/ppc/spapr_irq.h"
#include "hw/ppc/xive.h"
+#include "sysemu/sysemu.h"
#define TYPE_SPAPR_XIVE "spapr-xive"
#define SPAPR_XIVE(obj) OBJECT_CHECK(SpaprXive, (obj), TYPE_SPAPR_XIVE)
#ifndef PPC_XIVE_REGS_H
#define PPC_XIVE_REGS_H
+#include "qemu/bswap.h"
+#include "qemu/host-utils.h"
+
/*
* Interrupt source number encoding on PowerBUS
*/
#ifndef RISCV_BOOT_H
#define RISCV_BOOT_H
+#include "exec/cpu-defs.h"
+
void riscv_find_and_load_firmware(MachineState *machine,
const char *default_machine_firmware,
hwaddr firmware_load_addr);
#ifndef HW_RISCV_HART_H
#define HW_RISCV_HART_H
+#include "hw/sysbus.h"
+#include "target/riscv/cpu.h"
+
#define TYPE_RISCV_HART_ARRAY "riscv.hart_array"
#define RISCV_HART_ARRAY(obj) \
#ifndef HW_SIFIVE_CLINT_H
#define HW_SIFIVE_CLINT_H
+#include "hw/sysbus.h"
+
#define TYPE_SIFIVE_CLINT "riscv.sifive.clint"
#define SIFIVE_CLINT(obj) \
#ifndef HW_SIFIVE_E_H
#define HW_SIFIVE_E_H
+#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_gpio.h"
#define TYPE_RISCV_E_SOC "riscv.sifive.e.soc"
#ifndef HW_SIFIVE_PLIC_H
#define HW_SIFIVE_PLIC_H
-#include "hw/irq.h"
+#include "hw/sysbus.h"
#define TYPE_SIFIVE_PLIC "riscv.sifive.plic"
#ifndef HW_SIFIVE_PRCI_H
#define HW_SIFIVE_PRCI_H
+#include "hw/sysbus.h"
+
enum {
SIFIVE_PRCI_HFROSCCFG = 0x0,
SIFIVE_PRCI_HFXOSCCFG = 0x4,
#ifndef HW_SIFIVE_TEST_H
#define HW_SIFIVE_TEST_H
+#include "hw/sysbus.h"
+
#define TYPE_SIFIVE_TEST "riscv.sifive.test"
#define SIFIVE_TEST(obj) \
#define HW_SIFIVE_U_H
#include "hw/net/cadence_gem.h"
+#include "hw/riscv/riscv_hart.h"
#define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
#define RISCV_U_SOC(obj) \
#ifndef HW_SIFIVE_UART_H
#define HW_SIFIVE_UART_H
+#include "chardev/char-fe.h"
+#include "hw/sysbus.h"
+
enum {
SIFIVE_UART_TXFIFO = 0,
SIFIVE_UART_RXFIFO = 4,
#ifndef HW_RISCV_SPIKE_H
#define HW_RISCV_SPIKE_H
+#include "hw/riscv/riscv_hart.h"
+#include "hw/sysbus.h"
+
typedef struct {
/*< private >*/
SysBusDevice parent_obj;
#ifndef HW_RISCV_VIRT_H
#define HW_RISCV_VIRT_H
+#include "hw/riscv/riscv_hart.h"
+#include "hw/sysbus.h"
+
typedef struct {
/*< private >*/
SysBusDevice parent_obj;
* your option) any later version. See the COPYING file in the top-level
* directory.
*/
+
#ifndef HW_S390X_AP_DEVICE_H
#define HW_S390X_AP_DEVICE_H
+#include "hw/qdev-core.h"
+
#define AP_DEVICE_TYPE "ap-device"
typedef struct APDevice {
#ifndef HW_S390X_CSS_BRIDGE_H
#define HW_S390X_CSS_BRIDGE_H
+
#include "qom/object.h"
-#include "hw/qdev-core.h"
+#include "hw/sysbus.h"
/* virtual css bridge */
typedef struct VirtualCssBridge {
#include "hw/s390x/s390_flic.h"
#include "hw/s390x/ioinst.h"
#include "sysemu/kvm.h"
+#include "target/s390x/cpu-qom.h"
/* Channel subsystem constants. */
#define MAX_DEVNO 65535
#define HW_S390_TOD_H
#include "hw/qdev.h"
-#include "s390-tod.h"
+#include "target/s390x/s390-tod.h"
typedef struct S390TOD {
uint8_t high;
#ifndef SEMIHOST_CONSOLE_H
#define SEMIHOST_CONSOLE_H
+#include "cpu.h"
+
/**
* qemu_semihosting_console_outs:
* @env: CPUArchState
#ifndef SH_INTC_H
#define SH_INTC_H
+#include "exec/memory.h"
#include "hw/irq.h"
typedef unsigned char intc_enum;
#ifndef HW_SPARC_SPARC64_H
#define HW_SPARC_SPARC64_H
+#include "target/sparc/cpu-qom.h"
+
#define IVEC_MAX 0x40
SPARCCPU *sparc64_cpu_devinit(const char *cpu_type, uint64_t prom_addr);
#define ASPEED_SMC_H
#include "hw/ssi/ssi.h"
+#include "hw/sysbus.h"
typedef struct AspeedSegments {
hwaddr addr;
#include "hw/ssi/ssi.h"
#include "qemu/fifo32.h"
#include "hw/stream.h"
+#include "hw/sysbus.h"
typedef struct XilinxSPIPS XilinxSPIPS;
#define ALLWINNER_A10_PIT_H
#include "hw/ptimer.h"
+#include "hw/sysbus.h"
#define TYPE_AW_A10_PIT "allwinner-A10-timer"
#define AW_A10_PIT(obj) OBJECT_CHECK(AwA10PITState, (obj), TYPE_AW_A10_PIT)
#include "hw/hw.h"
#include "hw/isa/isa.h"
+#include "hw/timer/i8254.h"
#include "qemu/timer.h"
typedef struct PITChannelState {
#ifndef HW_M48T59_H
#define HW_M48T59_H
+#include "exec/hwaddr.h"
+#include "hw/irq.h"
#include "qom/object.h"
#define TYPE_NVRAM "nvram"
#ifndef MC146818RTC_REGS_H
#define MC146818RTC_REGS_H
+#include "qemu/timer.h"
+
#define RTC_ISA_IRQ 8
#define RTC_SECONDS 0
#define HW_TIMER_XLNX_ZYNQMP_RTC_H
#include "hw/register.h"
+#include "hw/sysbus.h"
#define TYPE_XLNX_ZYNQMP_RTC "xlnx-zynmp.rtc"
#ifndef QEMU_VIRTIO_ACCESS_H
#define QEMU_VIRTIO_ACCESS_H
+#include "exec/hwaddr.h"
#include "hw/virtio/virtio.h"
#include "hw/virtio/virtio-bus.h"
#define HW_VIRTIO_GPU_BSWAP_H
#include "qemu/bswap.h"
+#include "standard-headers/linux/virtio_gpu.h"
static inline void
virtio_gpu_ctrl_hdr_bswap(struct virtio_gpu_ctrl_hdr *hdr)
#ifndef QEMU_VIRTIO_RNG_H
#define QEMU_VIRTIO_RNG_H
+#include "hw/virtio/virtio.h"
#include "sysemu/rng.h"
#include "sysemu/rng-random.h"
#include "standard-headers/linux/virtio_rng.h"
#ifndef WDT_ASPEED_H
#define WDT_ASPEED_H
+#include "hw/misc/aspeed_scu.h"
#include "hw/sysbus.h"
#define TYPE_ASPEED_WDT "aspeed.wdt"
#define DECNLAUTHOR "Mike Cowlishaw" /* Who to blame */
#include "libdecnumber/dconfig.h"
+ #include "libdecnumber/decContext.h"
/* Conditional code flag -- set this to match hardware platform */
/* 1=little-endian, 0=big-endian */
/* Declarations for use for CPU state serialization. */
+
#ifndef MIGRATION_CPU_H
#define MIGRATION_CPU_H
+#include "exec/cpu-defs.h"
+
#if TARGET_LONG_BITS == 64
#define qemu_put_betl qemu_put_be64
#define qemu_get_betl qemu_get_be64
#ifndef MONITOR_HMP_TARGET_H
#define MONITOR_HMP_TARGET_H
+#include "cpu.h"
+
#define MD_TLONG 0
#define MD_I32 1
#ifndef QEMU_ATOMIC128_H
#define QEMU_ATOMIC128_H
+#include "qemu/int128.h"
+
/*
* GCC is a house divided about supporting large atomic operations.
*
#ifndef QEMU_RATELIMIT_H
#define QEMU_RATELIMIT_H
+#include "qemu/timer.h"
+
typedef struct {
int64_t slice_start_time;
int64_t slice_end_time;
};
/* Only valid for joinable threads. */
-HANDLE qemu_thread_get_handle(QemuThread *thread);
+HANDLE qemu_thread_get_handle(struct QemuThread *thread);
#endif
#ifndef QEMU_BALLOON_H
#define QEMU_BALLOON_H
+#include "exec/cpu-common.h"
#include "qapi/qapi-types-misc.h"
typedef void (QEMUBalloonEvent)(void *opaque, ram_addr_t target);
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*
*/
+
#ifndef CRYPTODEV_VHOST_USER_H
#define CRYPTODEV_VHOST_USER_H
+#include "sysemu/cryptodev-vhost.h"
+
#define VHOST_USER_MAX_AUTH_KEY_LEN 512
#define VHOST_USER_MAX_CIPHER_KEY_LEN 64
#ifndef HVF_H
#define HVF_H
+#include "cpu.h"
#include "qemu/bitops.h"
#include "exec/memory.h"
#include "sysemu/accel.h"
#include "block/aio.h"
#include "qemu/thread.h"
+#include "qom/object.h"
#define TYPE_IOTHREAD "iothread"
#ifndef QEMU_KVM_INT_H
#define QEMU_KVM_INT_H
+#include "exec/cpu-common.h"
+#include "exec/memory.h"
#include "sysemu/sysemu.h"
#include "sysemu/accel.h"
#include "sysemu/kvm.h"
#define MEMORY_MAPPING_H
#include "qemu/queue.h"
+#include "exec/cpu-common.h"
+#include "exec/cpu-defs.h"
#include "exec/memory.h"
typedef struct GuestPhysBlock {
#ifndef XEN_MAPCACHE_H
#define XEN_MAPCACHE_H
+#include "exec/cpu-common.h"
+
typedef hwaddr (*phys_offset_to_gaddr_t)(hwaddr phys_offset,
ram_addr_t size);
#ifdef CONFIG_XEN
#include <epoxy/gl.h>
#include <epoxy/egl.h>
#include <gbm.h>
+#include "qapi/qapi-types-ui.h"
+#include "ui/console.h"
+#include "ui/shader.h"
extern EGLDisplay *qemu_egl_display;
extern EGLConfig qemu_egl_config;
#define INPUT_H
#include "qapi/qapi-types-ui.h"
+#include "qemu/notify.h"
#define INPUT_EVENT_MASK_KEY (1<<INPUT_EVENT_KIND_KEY)
#define INPUT_EVENT_MASK_BTN (1<<INPUT_EVENT_KIND_BTN)
#ifndef UI_SPICE_DISPLAY_H
#define UI_SPICE_DISPLAY_H
+#include <spice.h>
#include <spice/ipc_ring.h>
#include <spice/enums.h>
#include <spice/qxl_dev.h>
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
-
+#include "exec/memory.h"
/* PA-RISC 1.x processors have a strong memory model. */
/* ??? While we do not yet implement PA-RISC 2.0, those processors have
projects / mirror_qemu.git / commitdiff