drm/i915/cnl: Remove spurious central_freq.

"Display software must leave this field at the default value.
It no longer needs to be configured as part of PLL programming."

We respect this already and we are setting up the default
one line below: "DPLL_CFGCR1_CENTRAL_FREQ".

Also we don't touch anywhere else this central_freq for cnl.
So let's remove from the final write.

No functional change. Only a clean-up patch.

Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171114194759.24541-2-rodrigo.vivi@intel.com

diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index be74d4767c8a4cd4ec29f8f82c26cc364ddd1b41..61c684ac47af4c85e95e3d36f88c12250c5ea6e7 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2265,7 +2265,6 @@ static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc *crtc,
                DPLL_CFGCR1_QDIV_MODE(wrpll_params.qdiv_mode) |
                DPLL_CFGCR1_KDIV(wrpll_params.kdiv) |
                DPLL_CFGCR1_PDIV(wrpll_params.pdiv) |
-               wrpll_params.central_freq |
                DPLL_CFGCR1_CENTRAL_FREQ;
 
        memset(&crtc_state->dpll_hw_state, 0,