iommu/amd: Fix performance counter initialization

BugLink: https://bugs.launchpad.net/bugs/1919492
[ Upstream commit 6778ff5b21bd8e78c8bd547fd66437cf2657fd9b ]

Certain AMD platforms enable power gating feature for IOMMU PMC,
which prevents the IOMMU driver from updating the counter while
trying to validate the PMC functionality in the init_iommu_perf_ctr().
This results in disabling PMC support and the following error message:

    "AMD-Vi: Unable to read/write to IOMMU perf counter"

To workaround this issue, disable power gating temporarily by programming
the counter source to non-zero value while validating the counter,
and restore the prior state afterward.

Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Tested-by: Tj (Elloe Linux) <ml.linux@elloe.vision>
Link: https://lore.kernel.org/r/20210208122712.5048-1-suravee.suthikulpanit@amd.com
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=201753
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Signed-off-by: Seth Forshee <seth.forshee@canonical.com>

diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c
index 83d8ab2aed9f45e32e505350a511ca10d7a41d80..01da76dc1caa84f5d2dd87b6eef4230f4a120310 100644 (file)
--- a/drivers/iommu/amd/init.c
+++ b/drivers/iommu/amd/init.c
@@ -12,6 +12,7 @@
 #include <linux/acpi.h>
 #include <linux/list.h>
 #include <linux/bitmap.h>
+#include <linux/delay.h>
 #include <linux/slab.h>
 #include <linux/syscore_ops.h>
 #include <linux/interrupt.h>
@@ -254,6 +255,8 @@ static enum iommu_init_state init_state = IOMMU_START_STATE;
 static int amd_iommu_enable_interrupts(void);
 static int __init iommu_go_to_state(enum iommu_init_state state);
 static void init_device_table_dma(void);
+static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
+                               u8 fxn, u64 *value, bool is_write);
 
 static bool amd_iommu_pre_enabled = true;
 
@@ -1712,13 +1715,11 @@ static int __init init_iommu_all(struct acpi_table_header *table)
        return 0;
 }
 
-static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
-                               u8 fxn, u64 *value, bool is_write);
-
-static void init_iommu_perf_ctr(struct amd_iommu *iommu)
+static void __init init_iommu_perf_ctr(struct amd_iommu *iommu)
 {
+       int retry;
        struct pci_dev *pdev = iommu->dev;
-       u64 val = 0xabcd, val2 = 0, save_reg = 0;
+       u64 val = 0xabcd, val2 = 0, save_reg, save_src;
 
        if (!iommu_feature(iommu, FEATURE_PC))
                return;
@@ -1726,17 +1727,39 @@ static void init_iommu_perf_ctr(struct amd_iommu *iommu)
        amd_iommu_pc_present = true;
 
        /* save the value to restore, if writable */
-       if (iommu_pc_get_set_reg(iommu, 0, 0, 0, &save_reg, false))
+       if (iommu_pc_get_set_reg(iommu, 0, 0, 0, &save_reg, false) ||
+           iommu_pc_get_set_reg(iommu, 0, 0, 8, &save_src, false))
                goto pc_false;
 
-       /* Check if the performance counters can be written to */
-       if ((iommu_pc_get_set_reg(iommu, 0, 0, 0, &val, true)) ||
-           (iommu_pc_get_set_reg(iommu, 0, 0, 0, &val2, false)) ||
-           (val != val2))
+       /*
+        * Disable power gating by programing the performance counter
+        * source to 20 (i.e. counts the reads and writes from/to IOMMU
+        * Reserved Register [MMIO Offset 1FF8h] that are ignored.),
+        * which never get incremented during this init phase.
+        * (Note: The event is also deprecated.)
+        */
+       val = 20;
+       if (iommu_pc_get_set_reg(iommu, 0, 0, 8, &val, true))
                goto pc_false;
 
+       /* Check if the performance counters can be written to */
+       val = 0xabcd;
+       for (retry = 5; retry; retry--) {
+               if (iommu_pc_get_set_reg(iommu, 0, 0, 0, &val, true) ||
+                   iommu_pc_get_set_reg(iommu, 0, 0, 0, &val2, false) ||
+                   val2)
+                       break;
+
+               /* Wait about 20 msec for power gating to disable and retry. */
+               msleep(20);
+       }
+
        /* restore */
-       if (iommu_pc_get_set_reg(iommu, 0, 0, 0, &save_reg, true))
+       if (iommu_pc_get_set_reg(iommu, 0, 0, 0, &save_reg, true) ||
+           iommu_pc_get_set_reg(iommu, 0, 0, 8, &save_src, true))
+               goto pc_false;
+
+       if (val != val2)
                goto pc_false;
 
        pci_info(pdev, "IOMMU performance counters supported\n");