version 0.7.2:
- x86_64 fixes (Win2000 and Linux 2.6 boot in 32 bit)
- - merge self modifying code handling in dirty ram page mecanism.
+ - merge self modifying code handling in dirty ram page mechanism.
- MIPS fixes (Ralf Baechle)
- better user net performances
* use that value directly. Within cpu_restore_state_from_tb, we
* assume PC comes from GETPC(), as used by the helper functions,
* so we adjust the address by -GETPC_ADJ to form an address that
- * is within the call insn, so that the address does not accidentially
+ * is within the call insn, so that the address does not accidentally
* match the beginning of the next guest insn. However, when the
* pc comes from the signal frame it points to the actual faulting
* host memory insn and not the return from a call insn.
head = audio_handle_legacy_opts();
/*
* In case of legacy initialization, all Audiodevs in the list will have
- * the same configuration (except the driver), so it does't matter which
+ * the same configuration (except the driver), so it doesn't matter which
* one we chose. We need an Audiodev to set up AudioState before we can
* init a driver. Also note that dev at this point is still in the
* list.
.name = TYPE_QAUTHZ_LIST,
.instance_size = sizeof(QAuthZList),
.instance_finalize = qauthz_list_finalize,
- .class_size = sizeof(QAuthZListClass),
.class_init = qauthz_list_class_init,
.interfaces = (InterfaceInfo[]) {
{ TYPE_USER_CREATABLE },
.instance_init = qauthz_list_file_init,
.instance_size = sizeof(QAuthZListFile),
.instance_finalize = qauthz_list_file_finalize,
- .class_size = sizeof(QAuthZListFileClass),
.class_init = qauthz_list_file_class_init,
.interfaces = (InterfaceInfo[]) {
{ TYPE_USER_CREATABLE },
.name = TYPE_QAUTHZ_PAM,
.instance_size = sizeof(QAuthZPAM),
.instance_finalize = qauthz_pam_finalize,
- .class_size = sizeof(QAuthZPAMClass),
.class_init = qauthz_pam_class_init,
.interfaces = (InterfaceInfo[]) {
{ TYPE_USER_CREATABLE },
.name = TYPE_QAUTHZ_SIMPLE,
.instance_size = sizeof(QAuthZSimple),
.instance_finalize = qauthz_simple_finalize,
- .class_size = sizeof(QAuthZSimpleClass),
.class_init = qauthz_simple_class_init,
.interfaces = (InterfaceInfo[]) {
{ TYPE_USER_CREATABLE },
*/
#define TYPE_CRYPTODEV_BACKEND_BUILTIN "cryptodev-backend-builtin"
-typedef struct CryptoDevBackendBuiltin
- CryptoDevBackendBuiltin;
-DECLARE_INSTANCE_CHECKER(CryptoDevBackendBuiltin, CRYPTODEV_BACKEND_BUILTIN,
- TYPE_CRYPTODEV_BACKEND_BUILTIN)
+OBJECT_DECLARE_SIMPLE_TYPE(CryptoDevBackendBuiltin, CRYPTODEV_BACKEND_BUILTIN)
typedef struct CryptoDevBackendBuiltinSession {
*/
#define TYPE_CRYPTODEV_BACKEND_VHOST_USER "cryptodev-vhost-user"
-typedef struct CryptoDevBackendVhostUser CryptoDevBackendVhostUser;
-DECLARE_INSTANCE_CHECKER(CryptoDevBackendVhostUser, CRYPTODEV_BACKEND_VHOST_USER,
- TYPE_CRYPTODEV_BACKEND_VHOST_USER)
+OBJECT_DECLARE_SIMPLE_TYPE(CryptoDevBackendVhostUser, CRYPTODEV_BACKEND_VHOST_USER)
struct CryptoDevBackendVhostUser {
#define TYPE_DBUS_VMSTATE "dbus-vmstate"
-OBJECT_DECLARE_SIMPLE_TYPE(DBusVMState, dbus_vmstate,
- DBUS_VMSTATE, ObjectClass)
+OBJECT_DECLARE_SIMPLE_TYPE(DBusVMState,
+ DBUS_VMSTATE)
struct DBusVMState {
.parent = TYPE_OBJECT,
.instance_size = sizeof(DBusVMState),
.instance_finalize = dbus_vmstate_finalize,
- .class_size = sizeof(DBusVMStateClass),
.class_init = dbus_vmstate_class_init,
.interfaces = (InterfaceInfo[]) {
{ TYPE_USER_CREATABLE },
#include "qom/object_interfaces.h"
#include "qom/object.h"
-typedef struct HostMemoryBackendFile HostMemoryBackendFile;
-DECLARE_INSTANCE_CHECKER(HostMemoryBackendFile, MEMORY_BACKEND_FILE,
- TYPE_MEMORY_BACKEND_FILE)
+OBJECT_DECLARE_SIMPLE_TYPE(HostMemoryBackendFile, MEMORY_BACKEND_FILE)
struct HostMemoryBackendFile {
#define TYPE_MEMORY_BACKEND_MEMFD "memory-backend-memfd"
-typedef struct HostMemoryBackendMemfd HostMemoryBackendMemfd;
-DECLARE_INSTANCE_CHECKER(HostMemoryBackendMemfd, MEMORY_BACKEND_MEMFD,
- TYPE_MEMORY_BACKEND_MEMFD)
+OBJECT_DECLARE_SIMPLE_TYPE(HostMemoryBackendMemfd, MEMORY_BACKEND_MEMFD)
struct HostMemoryBackendMemfd {
#include "qemu/guest-random.h"
#include "qom/object.h"
-typedef struct RngBuiltin RngBuiltin;
-DECLARE_INSTANCE_CHECKER(RngBuiltin, RNG_BUILTIN,
- TYPE_RNG_BUILTIN)
+OBJECT_DECLARE_SIMPLE_TYPE(RngBuiltin, RNG_BUILTIN)
struct RngBuiltin {
RngBackend parent;
#include "qom/object.h"
#define TYPE_RNG_EGD "rng-egd"
-typedef struct RngEgd RngEgd;
-DECLARE_INSTANCE_CHECKER(RngEgd, RNG_EGD,
- TYPE_RNG_EGD)
+OBJECT_DECLARE_SIMPLE_TYPE(RngEgd, RNG_EGD)
struct RngEgd {
RngBackend parent;
#include "qom/object.h"
#define TYPE_TPM_EMULATOR "tpm-emulator"
-typedef struct TPMEmulator TPMEmulator;
-DECLARE_INSTANCE_CHECKER(TPMEmulator, TPM_EMULATOR,
- TYPE_TPM_EMULATOR)
+OBJECT_DECLARE_SIMPLE_TYPE(TPMEmulator, TPM_EMULATOR)
#define TPM_EMULATOR_IMPLEMENTS_ALL_CAPS(S, cap) (((S)->caps & (cap)) == (cap))
#include "qom/object.h"
#define TYPE_TPM_PASSTHROUGH "tpm-passthrough"
-typedef struct TPMPassthruState TPMPassthruState;
-DECLARE_INSTANCE_CHECKER(TPMPassthruState, TPM_PASSTHROUGH,
- TYPE_TPM_PASSTHROUGH)
+OBJECT_DECLARE_SIMPLE_TYPE(TPMPassthruState, TPM_PASSTHROUGH)
/* data structures */
struct TPMPassthruState {
.instance_size = sizeof(VhostUserBackend),
.instance_init = vhost_user_backend_init,
.instance_finalize = vhost_user_backend_finalize,
- .class_size = sizeof(VhostUserBackendClass),
};
static void register_types(void)
/*
* Updates @child to change its reference to point to @new_bs, including
- * checking and applying the necessary permisson updates both to the old node
+ * checking and applying the necessary permission updates both to the old node
* and to @new_bs.
*
* NULL is passed as @new_bs for removing the reference before freeing @child.
xfs="yes"
else
if test "$xfs" = "yes" ; then
- feature_not_found "xfs" "Instal xfsprogs/xfslibs devel"
+ feature_not_found "xfs" "Install xfsprogs/xfslibs devel"
fi
xfs=no
fi
# in the gitdm sample-config directory.
#
# This file contains associations parameters regarding filetypes
-# (documentation, develompent, multimedia, images...)
+# (documentation, development, multimedia, images...)
#
# format:
# filetype <type> <regex> [<comment>]
filetype code \.S$ # Assembly
filetype code \.asm$ # Assembly
filetype code \.awk$ # awk
-filetype code ^common$ # script fragements
-filetype code ^common.*$ # script fragements
+filetype code ^common$ # script fragments
+filetype code ^common.*$ # script fragments
filetype code (qom|qmp)-\w+$ # python script fragments
#
const IvshmemClientPeer *peer);
/**
- * Broadcat a notification to all vectors of all peers
+ * Broadcast a notification to all vectors of all peers
*
* @client: The ivshmem client
*
/*
* If we are in postcopy mode and we receive a u64 payload with a 0 value
- * we know all the postcopy client bases have been recieved, and we
+ * we know all the postcopy client bases have been received, and we
* should start generating faults.
*/
if (track_ramblocks &&
for (i = 0; i < dev->max_queues; i++) {
if (dev->vq[i].vring.desc) {
if (map_ring(dev, &dev->vq[i])) {
- vu_panic(dev, "remaping queue %d during setmemtable", i);
+ vu_panic(dev, "remapping queue %d during setmemtable", i);
}
}
}
* @remove_watch: a remove_watch callback
* @iface: a VuDevIface structure with vhost-user device callbacks
*
- * Intializes a VuDev vhost-user context.
+ * Initializes a VuDev vhost-user context.
*
* Returns: true on success, false on failure.
**/
.parent = TYPE_QCRYPTO_SECRET_COMMON,
.name = TYPE_QCRYPTO_SECRET_KEYRING,
.instance_size = sizeof(QCryptoSecretKeyring),
- .class_size = sizeof(QCryptoSecretKeyringClass),
.class_init = qcrypto_secret_keyring_class_init,
.interfaces = (InterfaceInfo[]) {
{ TYPE_USER_CREATABLE },
fput_fp_reg (GET_FIELD (insn, 6, 10), info);
break;
- /* 'fA' will not generate a space before the regsiter
+ /* 'fA' will not generate a space before the register
name. Normally that is fine. Except that it
causes problems with xmpyu which has no FP format
completer. */
unsigned int exp_start;
unsigned int exp_len;
/* Bias added to a "true" exponent to form the biased exponent. It
- is intentionally signed as, otherwize, -exp_bias can turn into a
+ is intentionally signed as, otherwise, -exp_bias can turn into a
very large number (e.g., given the exp_bias of 0x3fff and a 64
bit long, the equation (long)(1 - exp_bias) evaluates to
4294950914) instead of -16382). */
and remaining 3 bits of register shifted 9 bits in first word.
Indicate upper/lower in 1 bit shifted 7 bits in second word.
Use with `R' or `u' format.
- n `m' withouth upper/lower indication. (For M[S]ACx; 4 bits split
+ n `m' without upper/lower indication. (For M[S]ACx; 4 bits split
with MSB shifted 6 bits in first word and remaining 3 bits of
register shifted 9 bits in first word. No upper/lower
indication is done.) Use with `R' or `u' format.
/* Check if an EA is valid for a particular code. This is required
for the EMAC instructions since the type of source address determines
- if it is a EMAC-load instruciton if the EA is mode 2-5, otherwise it
+ if it is a EMAC-load instruction if the EA is mode 2-5, otherwise it
is a non-load EMAC instruction and the bits mean register Ry.
A similar case exists for the movem instructions where the register
mask is interpreted differently for different EAs. */
/* Returns number of bytes "eaten" by the operand, or
return -1 if an invalid operand was found, or -2 if
- an opcode tabe error was found.
+ an opcode table error was found.
ADDR is the pc for this arg to be relative to. */
static int
if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
{
/* BITM is always some number of zeros followed by some
- number of ones, followed by some numer of zeros. */
+ number of ones, followed by some number of zeros. */
unsigned long top = operand->bitm;
/* top & -top gives the rightmost 1 bit, so this
fills in any trailing zeros. */
as soon as it determines the absence.
COLO disk Manager:
-When primary VM writes data into image, the colo disk manger captures this data
+When primary VM writes data into image, the colo disk manager captures this data
and sends it to secondary VM's which makes sure the context of secondary VM's
image is consistent with the context of primary VM 's image.
For more details, please refer to docs/block-replication.txt.
== Test procedure ==
Note: Here we are running both instances on the same host for testing,
-change the IP Addresses if you want to run it on two hosts. Initally
+change the IP Addresses if you want to run it on two hosts. Initially
127.0.0.1 is the Primary Host and 127.0.0.2 is the Secondary Host.
== Startup qemu ==
1. Primary:
-Note: Initally, $imagefolder/primary.qcow2 needs to be copied to all hosts.
+Note: Initially, $imagefolder/primary.qcow2 needs to be copied to all hosts.
You don't need to change any IP's here, because 0.0.0.0 listens on any
interface. The chardev's with 127.0.0.1 IP's loopback to the local qemu
instance.
errno - the numeric errno value to return when a request matches this rule.
The errno values depend on the host since the numeric values are not
- standarized in the POSIX specification.
+ standardized in the POSIX specification.
sector - (optional) a sector number that the request must overlap in order to
match this rule
time later on. Issuing it after the end of a migration is harmless.
Blocktime is a postcopy live migration metric, intended to show how
-long the vCPU was in state of interruptable sleep due to pagefault.
+long the vCPU was in state of interruptible sleep due to pagefault.
That metric is calculated both for all vCPUs as overlapped value, and
separately for each vCPU. These values are calculated on destination
side. To enable postcopy blocktime calculation, enter following
A few important files for suppressing warnings are:
tests/tsan/suppressions.tsan - Has TSan warnings we wish to suppress at runtime.
-The comment on each supression will typically indicate why we are
+The comment on each suppression will typically indicate why we are
suppressing it. More information on the file format can be found here:
https://github.com/google/sanitizers/wiki/ThreadSanitizerSuppressions
#include "trace.h"
To access the 'io/trace.h' file. While it is possible to include a trace.h
-file from outside a source files' own sub-directory, this is discouraged in
+file from outside a source file's own sub-directory, this is discouraged in
general. It is strongly preferred that all events be declared directly in
the sub-directory that uses them. The only exception is where there are some
shared trace events defined in the top level directory trace-events file.
======================
Enables paravirtualized spinlocks. The parameter indicates how many times
spinlock acquisition should be attempted before indicating the situation to the
-hypervisor. A special value 0xffffffff indicates "never to retry".
+hypervisor. A special value 0xffffffff indicates "never notify".
3.4. hv-vpindex
================
only make sense when paired directly with other commands. When a VM is paused,
it's easy to ensure that no guest writes occur between individual QMP
commands. When a VM is running, this is difficult to accomplish with
-individual QMP commands that may allow guest writes to occur inbetween each
+individual QMP commands that may allow guest writes to occur between each
command.
For example, using only individual QMP commands, we could:
- Everything the same UID
- Convenient for developers
- - Improved reliability - crash of one part doens't take
+ - Improved reliability - crash of one part doesn't take
out entire VM
- No security benefit over traditional QEMU, unless additional
unless additional controls such as SELinux or AppArmor are
</policy>
-dbus-daemon can also perfom SELinux checks based on the security
+dbus-daemon can also perform SELinux checks based on the security
context of the source and the target. For example, ``virtiofs_t``
could be allowed to send a message to ``svirt_t``, but ``virtiofs_t``
wouldn't be allowed to send a message to ``virtiofs_t``.
* 2.12: NBD_CMD_BLOCK_STATUS for "base:allocation"
* 3.0: NBD_OPT_STARTTLS with TLS Pre-Shared Keys (PSK),
NBD_CMD_BLOCK_STATUS for "qemu:dirty-bitmap:", NBD_CMD_CACHE
-* 4.2: NBD_FLAG_CAN_MULTI_CONN for sharable read-only exports,
+* 4.2: NBD_FLAG_CAN_MULTI_CONN for shareable read-only exports,
NBD_CMD_FLAG_FAST_ZERO
:scanout-id: ``u32``, the scanout where the cursor is located
-:x/y: ``u32``, the cursor postion
+:x/y: ``u32``, the cursor position
VhostUserGpuCursorUpdate
^^^^^^^^^^^^^^^^^^^^^^^^
(3), the I/O virtual address and the size. On success, the slave is
expected to reply with a zero payload, non-zero otherwise.
-The slave relies on the slave communcation channel (see :ref:`Slave
+The slave relies on the slave communication channel (see :ref:`Slave
communication <slave_communication>` section below) to send IOTLB miss
and access failure events, by sending ``VHOST_USER_SLAVE_IOTLB_MSG``
requests to the master with a ``struct vhost_iotlb_msg`` as
need to be configured manually depending on the use case. However, it
is a good idea to follow the conventions listed here when
possible. Users, QEMU or libvirt, can then rely on some common
-behaviour to avoid heterogenous configuration and management of the
+behaviour to avoid heterogeneous configuration and management of the
backend programs and facilitate interoperability.
Each backend installed on a host system should come with at least one
of the connection (described below).
All of the remaining command types (not including 'ready')
-described above all use the aformentioned two functions to do the hard work:
+described above all use the aforementioned two functions to do the hard work:
1. After connection setup, RAMBlock information is exchanged using
this protocol before the actual migration begins. This information includes
This property describes the dynamically reconfigurable memory. It is a
property encoded array that has an integer N, the number of LMBs followed
-by N LMB list entires.
+by N LMB list entries.
Each LMB list entry consists of the following elements:
ibm,dynamic-memory-v2
This property describes the dynamically reconfigurable memory. This is
-an alternate and newer way to describe dyanamically reconfigurable memory.
+an alternate and newer way to describe dynamically reconfigurable memory.
It is a property encoded array that has an integer N (the number of
LMB set entries) followed by N LMB set entries. There is an LMB set entry
for each sequential group of LMBs that share common attributes.
supported and if the guest OS supports XIVE, this mode will be
selected.
-The choosen interrupt mode is activated after a reconfiguration done
+The chosen interrupt mode is activated after a reconfiguration done
in a machine reset.
KVM negotiation
---------------------------
The properties for the PAPR interrupt controller node when the *XIVE
-native exploitation mode* is selected shoud contain:
+native exploitation mode* is selected should contain:
- ``device_type``
------------
The Aspeed machines can be started using the -kernel option to load a
-Linux kernel or from a firmare image which can be downloaded from the
+Linux kernel or from a firmware image which can be downloaded from the
OpenPOWER jenkins :
https://openpower.xyz/
When not using the deprecated legacy audio config, each sound card
should specify an ``audiodev=`` property. Additionally, when using
-vnc, you should specify an ``audiodev=`` propery if you plan to
+vnc, you should specify an ``audiodev=`` property if you plan to
transmit audio through the VNC protocol.
Creating sound card devices using ``-soundhw`` (since 5.1)
parameter described above with the difference that the role of the user plays
QEMU using implicit generic or board specific splitting rule.
Use ``memdev`` with *memory-backend-ram* backend or ``mem`` (if
-it's supported by used machine type) to define mapping explictly instead.
+it's supported by used machine type) to define mapping explicitly instead.
``-mem-path`` fallback to RAM (since 4.1)
'''''''''''''''''''''''''''''''''''''''''
Guest Emulator ISAs
-------------------
-RISC-V ISA privledge specification version 1.09.1 (removed in 5.1)
+RISC-V ISA privilege specification version 1.09.1 (removed in 5.1)
''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
-The RISC-V ISA privledge specification version 1.09.1 has been removed.
+The RISC-V ISA privilege specification version 1.09.1 has been removed.
QEMU supports both the newer version 1.10.0 and the ratified version 1.11.0, these
should be used instead of the 1.09.1 version.
.. parsed-literal::
- |qemu_system| -iscsi initiator-name=iqn.2001-04.com.example:my-initiator \
- -cdrom iscsi://192.0.2.1/iqn.2001-04.com.example/2 \
+ |qemu_system| -iscsi initiator-name=iqn.2001-04.com.example:my-initiator \\
+ -cdrom iscsi://192.0.2.1/iqn.2001-04.com.example/2 \\
-drive file=iscsi://192.0.2.1/iqn.2001-04.com.example/1
Example (CHAP username/password via URL):
.. parsed-literal::
- LIBISCSI_CHAP_USERNAME="user" \
- LIBISCSI_CHAP_PASSWORD="password" \
+ LIBISCSI_CHAP_USERNAME="user" \\
+ LIBISCSI_CHAP_PASSWORD="password" \\
|qemu_system| -drive file=iscsi://192.0.2.1/iqn.2001-04.com.example/1
``NBD``
As for now it supports few Arduino boards for educational and testing purposes.
These boards use a ATmega controller, which model is limited to USART & 16-bit
-timer devices, enought to run FreeRTOS based applications (like
+timer devices, enough to run FreeRTOS based applications (like
https://github.com/seharris/qemu-avr-tests/blob/master/free-rtos/Demo/AVR_ATMega2560_GCC/demo.elf
).
telnet localhost 5678
-- Debugging wit GDB debugger::
+- Debugging with GDB debugger::
qemu-system-avr -machine mega2560 -bios demo.elf -s -S
I/O timeout in seconds. The default depends on cache= option.
* writeback|no_writeback -
- Enable/disable writeback cache. The cache alows the FUSE client to buffer
+ Enable/disable writeback cache. The cache allows the FUSE client to buffer
and merge write requests. The default is ``no_writeback``.
* xattr|no_xattr -
/*
* Gets stat/statfs information and packs in out_iovec structure
- * on success returns number of bytes packed in out_iovec struture
+ * on success returns number of bytes packed in out_iovec structure
* otherwise returns -errno
*/
static int do_stat(int type, struct iovec *iovec, struct iovec *out_iovec)
},
SRST
``drive_backup``
- Start a point-in-time copy of a block device to a specificed target.
+ Start a point-in-time copy of a block device to a specified target.
ERST
{
VirtQueueElement *elems[MAX_REQ];
V9fsState state;
};
-typedef struct V9fsVirtioState V9fsVirtioState;
#define TYPE_VIRTIO_9P "virtio-9p-device"
-DECLARE_INSTANCE_CHECKER(V9fsVirtioState, VIRTIO_9P,
- TYPE_VIRTIO_9P)
+OBJECT_DECLARE_SIMPLE_TYPE(V9fsVirtioState, VIRTIO_9P)
#endif
MemHotplugState acpi_memory_hotplug;
};
-typedef struct PIIX4PMState PIIX4PMState;
-DECLARE_INSTANCE_CHECKER(PIIX4PMState, PIIX4_PM,
- TYPE_PIIX4_PM)
+OBJECT_DECLARE_SIMPLE_TYPE(PIIX4PMState, PIIX4_PM)
static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
PCIBus *bus, PIIX4PMState *s);
TyphoonWindow win[4];
} TyphoonPchip;
-typedef struct TyphoonState TyphoonState;
-DECLARE_INSTANCE_CHECKER(TyphoonState, TYPHOON_PCI_HOST_BRIDGE,
- TYPE_TYPHOON_PCI_HOST_BRIDGE)
+OBJECT_DECLARE_SIMPLE_TYPE(TyphoonState, TYPHOON_PCI_HOST_BRIDGE)
struct TyphoonState {
PCIHostState parent_obj;
StrongARMState *sa1110;
};
-typedef struct CollieMachineState CollieMachineState;
#define TYPE_COLLIE_MACHINE MACHINE_TYPE_NAME("collie")
-DECLARE_INSTANCE_CHECKER(CollieMachineState, COLLIE_MACHINE,
- TYPE_COLLIE_MACHINE)
+OBJECT_DECLARE_SIMPLE_TYPE(CollieMachineState, COLLIE_MACHINE)
static struct arm_boot_info collie_binfo = {
.loader_start = SA_SDCS0,
};
#define TYPE_HIGHBANK_REGISTERS "highbank-regs"
-typedef struct HighbankRegsState HighbankRegsState;
-DECLARE_INSTANCE_CHECKER(HighbankRegsState, HIGHBANK_REGISTERS,
- TYPE_HIGHBANK_REGISTERS)
+OBJECT_DECLARE_SIMPLE_TYPE(HighbankRegsState, HIGHBANK_REGISTERS)
struct HighbankRegsState {
/*< private >*/
#include "qom/object.h"
#define TYPE_INTEGRATOR_CM "integrator_core"
-typedef struct IntegratorCMState IntegratorCMState;
-DECLARE_INSTANCE_CHECKER(IntegratorCMState, INTEGRATOR_CM,
- TYPE_INTEGRATOR_CM)
+OBJECT_DECLARE_SIMPLE_TYPE(IntegratorCMState, INTEGRATOR_CM)
struct IntegratorCMState {
/*< private >*/
/* Primary interrupt controller. */
#define TYPE_INTEGRATOR_PIC "integrator_pic"
-typedef struct icp_pic_state icp_pic_state;
-DECLARE_INSTANCE_CHECKER(icp_pic_state, INTEGRATOR_PIC,
- TYPE_INTEGRATOR_PIC)
+OBJECT_DECLARE_SIMPLE_TYPE(icp_pic_state, INTEGRATOR_PIC)
struct icp_pic_state {
/*< private >*/
/* CP control registers. */
#define TYPE_ICP_CONTROL_REGS "icp-ctrl-regs"
-typedef struct ICPCtrlRegsState ICPCtrlRegsState;
-DECLARE_INSTANCE_CHECKER(ICPCtrlRegsState, ICP_CONTROL_REGS,
- TYPE_ICP_CONTROL_REGS)
+OBJECT_DECLARE_SIMPLE_TYPE(ICPCtrlRegsState, ICP_CONTROL_REGS)
struct ICPCtrlRegsState {
/*< private >*/
NRF51State nrf51;
MicrobitI2CState i2c;
};
-typedef struct MicrobitMachineState MicrobitMachineState;
#define TYPE_MICROBIT_MACHINE MACHINE_TYPE_NAME("microbit")
-DECLARE_INSTANCE_CHECKER(MicrobitMachineState, MICROBIT_MACHINE,
- TYPE_MICROBIT_MACHINE)
+OBJECT_DECLARE_SIMPLE_TYPE(MicrobitMachineState, MICROBIT_MACHINE)
static void microbit_init(MachineState *machine)
{
uint32_t scc_id;
const char *armsse_type;
};
-typedef struct MPS2TZMachineClass MPS2TZMachineClass;
struct MPS2TZMachineState {
MachineState parent;
DeviceState *lan9118;
SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ];
};
-typedef struct MPS2TZMachineState MPS2TZMachineState;
#define TYPE_MPS2TZ_MACHINE "mps2tz"
#define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505")
#define TYPE_MPS2TZ_AN521_MACHINE MACHINE_TYPE_NAME("mps2-an521")
-DECLARE_OBJ_CHECKERS(MPS2TZMachineState, MPS2TZMachineClass,
- MPS2TZ_MACHINE, TYPE_MPS2TZ_MACHINE)
+OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE)
/* Main SYSCLK frequency in Hz */
#define SYSCLK_FRQ 20000000
hwaddr ethernet_base;
hwaddr psram_base;
};
-typedef struct MPS2MachineClass MPS2MachineClass;
struct MPS2MachineState {
MachineState parent;
CMSDKAPBDualTimer dualtimer;
CMSDKAPBWatchdog watchdog;
};
-typedef struct MPS2MachineState MPS2MachineState;
#define TYPE_MPS2_MACHINE "mps2"
#define TYPE_MPS2_AN385_MACHINE MACHINE_TYPE_NAME("mps2-an385")
#define TYPE_MPS2_AN500_MACHINE MACHINE_TYPE_NAME("mps2-an500")
#define TYPE_MPS2_AN511_MACHINE MACHINE_TYPE_NAME("mps2-an511")
-DECLARE_OBJ_CHECKERS(MPS2MachineState, MPS2MachineClass,
- MPS2_MACHINE, TYPE_MPS2_MACHINE)
+OBJECT_DECLARE_TYPE(MPS2MachineState, MPS2MachineClass, MPS2_MACHINE)
/* Main SYSCLK frequency in Hz */
#define SYSCLK_FRQ 25000000
const MPCInfo *mpc_info;
int num_mpcs;
};
-typedef struct MuscaMachineClass MuscaMachineClass;
struct MuscaMachineState {
MachineState parent;
UnimplementedDeviceState gpio;
UnimplementedDeviceState cryptoisland;
};
-typedef struct MuscaMachineState MuscaMachineState;
#define TYPE_MUSCA_MACHINE "musca"
#define TYPE_MUSCA_A_MACHINE MACHINE_TYPE_NAME("musca-a")
#define TYPE_MUSCA_B1_MACHINE MACHINE_TYPE_NAME("musca-b1")
-DECLARE_OBJ_CHECKERS(MuscaMachineState, MuscaMachineClass,
- MUSCA_MACHINE, TYPE_MUSCA_MACHINE)
+OBJECT_DECLARE_TYPE(MuscaMachineState, MuscaMachineClass, MUSCA_MACHINE)
/*
* Main SYSCLK frequency in Hz
} mv88w8618_rx_desc;
#define TYPE_MV88W8618_ETH "mv88w8618_eth"
-typedef struct mv88w8618_eth_state mv88w8618_eth_state;
-DECLARE_INSTANCE_CHECKER(mv88w8618_eth_state, MV88W8618_ETH,
- TYPE_MV88W8618_ETH)
+OBJECT_DECLARE_SIMPLE_TYPE(mv88w8618_eth_state, MV88W8618_ETH)
struct mv88w8618_eth_state {
/*< private >*/
#define MP_LCD_TEXTCOLOR 0xe0e0ff /* RRGGBB */
#define TYPE_MUSICPAL_LCD "musicpal_lcd"
-typedef struct musicpal_lcd_state musicpal_lcd_state;
-DECLARE_INSTANCE_CHECKER(musicpal_lcd_state, MUSICPAL_LCD,
- TYPE_MUSICPAL_LCD)
+OBJECT_DECLARE_SIMPLE_TYPE(musicpal_lcd_state, MUSICPAL_LCD)
struct musicpal_lcd_state {
/*< private >*/
#define MP_PIC_ENABLE_CLR 0x0C
#define TYPE_MV88W8618_PIC "mv88w8618_pic"
-typedef struct mv88w8618_pic_state mv88w8618_pic_state;
-DECLARE_INSTANCE_CHECKER(mv88w8618_pic_state, MV88W8618_PIC,
- TYPE_MV88W8618_PIC)
+OBJECT_DECLARE_SIMPLE_TYPE(mv88w8618_pic_state, MV88W8618_PIC)
struct mv88w8618_pic_state {
/*< private >*/
} mv88w8618_timer_state;
#define TYPE_MV88W8618_PIT "mv88w8618_pit"
-typedef struct mv88w8618_pit_state mv88w8618_pit_state;
-DECLARE_INSTANCE_CHECKER(mv88w8618_pit_state, MV88W8618_PIT,
- TYPE_MV88W8618_PIT)
+OBJECT_DECLARE_SIMPLE_TYPE(mv88w8618_pit_state, MV88W8618_PIT)
struct mv88w8618_pit_state {
/*< private >*/
#define MP_FLASHCFG_CFGR0 0x04
#define TYPE_MV88W8618_FLASHCFG "mv88w8618_flashcfg"
-typedef struct mv88w8618_flashcfg_state mv88w8618_flashcfg_state;
-DECLARE_INSTANCE_CHECKER(mv88w8618_flashcfg_state, MV88W8618_FLASHCFG,
- TYPE_MV88W8618_FLASHCFG)
+OBJECT_DECLARE_SIMPLE_TYPE(mv88w8618_flashcfg_state, MV88W8618_FLASHCFG)
struct mv88w8618_flashcfg_state {
/*< private >*/
SysBusDevice parent_obj;
MemoryRegion iomem;
};
-typedef struct MusicPalMiscState MusicPalMiscState;
#define TYPE_MUSICPAL_MISC "musicpal-misc"
-DECLARE_INSTANCE_CHECKER(MusicPalMiscState, MUSICPAL_MISC,
- TYPE_MUSICPAL_MISC)
+OBJECT_DECLARE_SIMPLE_TYPE(MusicPalMiscState, MUSICPAL_MISC)
static uint64_t musicpal_misc_read(void *opaque, hwaddr offset,
unsigned size)
#define MP_OE_LCD_BRIGHTNESS 0x0007
#define TYPE_MUSICPAL_GPIO "musicpal_gpio"
-typedef struct musicpal_gpio_state musicpal_gpio_state;
-DECLARE_INSTANCE_CHECKER(musicpal_gpio_state, MUSICPAL_GPIO,
- TYPE_MUSICPAL_GPIO)
+OBJECT_DECLARE_SIMPLE_TYPE(musicpal_gpio_state, MUSICPAL_GPIO)
struct musicpal_gpio_state {
/*< private >*/
#define MP_KEY_BTN_NAVIGATION (1 << 7)
#define TYPE_MUSICPAL_KEY "musicpal_key"
-typedef struct musicpal_key_state musicpal_key_state;
-DECLARE_INSTANCE_CHECKER(musicpal_key_state, MUSICPAL_KEY,
- TYPE_MUSICPAL_KEY)
+OBJECT_DECLARE_SIMPLE_TYPE(musicpal_key_state, MUSICPAL_KEY)
struct musicpal_key_state {
/*< private >*/
*/
#define TYPE_PALM_MISC_GPIO "palm-misc-gpio"
-typedef struct PalmMiscGPIOState PalmMiscGPIOState;
-DECLARE_INSTANCE_CHECKER(PalmMiscGPIOState, PALM_MISC_GPIO,
- TYPE_PALM_MISC_GPIO)
+OBJECT_DECLARE_SIMPLE_TYPE(PalmMiscGPIOState, PALM_MISC_GPIO)
struct PalmMiscGPIOState {
SysBusDevice parent_obj;
};
#define TYPE_PXA2XX_SSP "pxa2xx-ssp"
-typedef struct PXA2xxSSPState PXA2xxSSPState;
-DECLARE_INSTANCE_CHECKER(PXA2xxSSPState, PXA2XX_SSP,
- TYPE_PXA2XX_SSP)
+OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxSSPState, PXA2XX_SSP)
/* Synchronous Serial Ports */
struct PXA2xxSSPState {
#define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */
#define TYPE_PXA2XX_RTC "pxa2xx_rtc"
-typedef struct PXA2xxRTCState PXA2xxRTCState;
-DECLARE_INSTANCE_CHECKER(PXA2xxRTCState, PXA2XX_RTC,
- TYPE_PXA2XX_RTC)
+OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxRTCState, PXA2XX_RTC)
struct PXA2xxRTCState {
/*< private >*/
/* I2C Interface */
#define TYPE_PXA2XX_I2C_SLAVE "pxa2xx-i2c-slave"
-typedef struct PXA2xxI2CSlaveState PXA2xxI2CSlaveState;
-DECLARE_INSTANCE_CHECKER(PXA2xxI2CSlaveState, PXA2XX_I2C_SLAVE,
- TYPE_PXA2XX_I2C_SLAVE)
+OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxI2CSlaveState, PXA2XX_I2C_SLAVE)
struct PXA2xxI2CSlaveState {
I2CSlave parent_obj;
#define PXA2XX_GPIO_BANKS 4
#define TYPE_PXA2XX_GPIO "pxa2xx-gpio"
-typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo;
-DECLARE_INSTANCE_CHECKER(PXA2xxGPIOInfo, PXA2XX_GPIO,
- TYPE_PXA2XX_GPIO)
+OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxGPIOInfo, PXA2XX_GPIO)
struct PXA2xxGPIOInfo {
/*< private >*/
#define PXA2XX_PIC_SRCS 40
#define TYPE_PXA2XX_PIC "pxa2xx_pic"
-typedef struct PXA2xxPICState PXA2xxPICState;
-DECLARE_INSTANCE_CHECKER(PXA2xxPICState, PXA2XX_PIC,
- TYPE_PXA2XX_PIC)
+OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxPICState, PXA2XX_PIC)
struct PXA2xxPICState {
/*< private >*/
DeviceState *gic;
PFlashCFI01 *flash[2];
};
-typedef struct SBSAMachineState SBSAMachineState;
#define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref")
-DECLARE_INSTANCE_CHECKER(SBSAMachineState, SBSA_MACHINE,
- TYPE_SBSA_MACHINE)
+OBJECT_DECLARE_SIMPLE_TYPE(SBSAMachineState, SBSA_MACHINE)
static const MemMapEntry sbsa_ref_memmap[] = {
/* 512M boot ROM */
enum spitz_model_e model;
int arm_id;
};
-typedef struct SpitzMachineClass SpitzMachineClass;
struct SpitzMachineState {
MachineState parent;
DeviceState *scp1;
DeviceState *misc_gpio;
};
-typedef struct SpitzMachineState SpitzMachineState;
#define TYPE_SPITZ_MACHINE "spitz-common"
-DECLARE_OBJ_CHECKERS(SpitzMachineState, SpitzMachineClass,
- SPITZ_MACHINE, TYPE_SPITZ_MACHINE)
+OBJECT_DECLARE_TYPE(SpitzMachineState, SpitzMachineClass, SPITZ_MACHINE)
#define zaurus_printf(format, ...) \
fprintf(stderr, "%s: " format, __func__, ##__VA_ARGS__)
#define FLASHCTL_NCE (FLASHCTL_CE0 | FLASHCTL_CE1)
#define TYPE_SL_NAND "sl-nand"
-typedef struct SLNANDState SLNANDState;
-DECLARE_INSTANCE_CHECKER(SLNANDState, SL_NAND,
- TYPE_SL_NAND)
+OBJECT_DECLARE_SIMPLE_TYPE(SLNANDState, SL_NAND)
struct SLNANDState {
SysBusDevice parent_obj;
};
#define TYPE_SPITZ_KEYBOARD "spitz-keyboard"
-typedef struct SpitzKeyboardState SpitzKeyboardState;
-DECLARE_INSTANCE_CHECKER(SpitzKeyboardState, SPITZ_KEYBOARD,
- TYPE_SPITZ_KEYBOARD)
+OBJECT_DECLARE_SIMPLE_TYPE(SpitzKeyboardState, SPITZ_KEYBOARD)
struct SpitzKeyboardState {
SysBusDevice parent_obj;
#define LCDTG_POLCTRL 0x07
#define TYPE_SPITZ_LCDTG "spitz-lcdtg"
-typedef struct SpitzLCDTG SpitzLCDTG;
-DECLARE_INSTANCE_CHECKER(SpitzLCDTG, SPITZ_LCDTG,
- TYPE_SPITZ_LCDTG)
+OBJECT_DECLARE_SIMPLE_TYPE(SpitzLCDTG, SPITZ_LCDTG)
struct SpitzLCDTG {
SSISlave ssidev;
#define SPITZ_GPIO_TP_INT 11
#define TYPE_CORGI_SSP "corgi-ssp"
-typedef struct CorgiSSPState CorgiSSPState;
-DECLARE_INSTANCE_CHECKER(CorgiSSPState, CORGI_SSP,
- TYPE_CORGI_SSP)
+OBJECT_DECLARE_SIMPLE_TYPE(CorgiSSPState, CORGI_SSP)
/* "Demux" the signal based on current chipselect */
struct CorgiSSPState {
* + named GPIO output "adc-temp": the ADC value, to be wired up to the max111x
*/
#define TYPE_SPITZ_MISC_GPIO "spitz-misc-gpio"
-typedef struct SpitzMiscGPIOState SpitzMiscGPIOState;
-DECLARE_INSTANCE_CHECKER(SpitzMiscGPIOState, SPITZ_MISC_GPIO,
- TYPE_SPITZ_MISC_GPIO)
+OBJECT_DECLARE_SIMPLE_TYPE(SpitzMiscGPIOState, SPITZ_MISC_GPIO)
struct SpitzMiscGPIOState {
SysBusDevice parent_obj;
/* General purpose timer module. */
#define TYPE_STELLARIS_GPTM "stellaris-gptm"
-typedef struct gptm_state gptm_state;
-DECLARE_INSTANCE_CHECKER(gptm_state, STELLARIS_GPTM,
- TYPE_STELLARIS_GPTM)
+OBJECT_DECLARE_SIMPLE_TYPE(gptm_state, STELLARIS_GPTM)
struct gptm_state {
SysBusDevice parent_obj;
/* I2C controller. */
#define TYPE_STELLARIS_I2C "stellaris-i2c"
-typedef struct stellaris_i2c_state stellaris_i2c_state;
-DECLARE_INSTANCE_CHECKER(stellaris_i2c_state, STELLARIS_I2C,
- TYPE_STELLARIS_I2C)
+OBJECT_DECLARE_SIMPLE_TYPE(stellaris_i2c_state, STELLARIS_I2C)
struct stellaris_i2c_state {
SysBusDevice parent_obj;
/* Interrupt Controller */
#define TYPE_STRONGARM_PIC "strongarm_pic"
-typedef struct StrongARMPICState StrongARMPICState;
-DECLARE_INSTANCE_CHECKER(StrongARMPICState, STRONGARM_PIC,
- TYPE_STRONGARM_PIC)
+OBJECT_DECLARE_SIMPLE_TYPE(StrongARMPICState, STRONGARM_PIC)
struct StrongARMPICState {
SysBusDevice parent_obj;
* f = 32 768 / (RTTR_trim + 1) */
#define TYPE_STRONGARM_RTC "strongarm-rtc"
-typedef struct StrongARMRTCState StrongARMRTCState;
-DECLARE_INSTANCE_CHECKER(StrongARMRTCState, STRONGARM_RTC,
- TYPE_STRONGARM_RTC)
+OBJECT_DECLARE_SIMPLE_TYPE(StrongARMRTCState, STRONGARM_RTC)
struct StrongARMRTCState {
SysBusDevice parent_obj;
#define GAFR 0x1c
#define TYPE_STRONGARM_GPIO "strongarm-gpio"
-typedef struct StrongARMGPIOInfo StrongARMGPIOInfo;
-DECLARE_INSTANCE_CHECKER(StrongARMGPIOInfo, STRONGARM_GPIO,
- TYPE_STRONGARM_GPIO)
+OBJECT_DECLARE_SIMPLE_TYPE(StrongARMGPIOInfo, STRONGARM_GPIO)
struct StrongARMGPIOInfo {
SysBusDevice busdev;
#define PPFR 0x10
#define TYPE_STRONGARM_PPC "strongarm-ppc"
-typedef struct StrongARMPPCInfo StrongARMPPCInfo;
-DECLARE_INSTANCE_CHECKER(StrongARMPPCInfo, STRONGARM_PPC,
- TYPE_STRONGARM_PPC)
+OBJECT_DECLARE_SIMPLE_TYPE(StrongARMPPCInfo, STRONGARM_PPC)
struct StrongARMPPCInfo {
SysBusDevice parent_obj;
#define RX_FIFO_ROR (1 << 10)
#define TYPE_STRONGARM_UART "strongarm-uart"
-typedef struct StrongARMUARTState StrongARMUARTState;
-DECLARE_INSTANCE_CHECKER(StrongARMUARTState, STRONGARM_UART,
- TYPE_STRONGARM_UART)
+OBJECT_DECLARE_SIMPLE_TYPE(StrongARMUARTState, STRONGARM_UART)
struct StrongARMUARTState {
SysBusDevice parent_obj;
/* Synchronous Serial Ports */
#define TYPE_STRONGARM_SSP "strongarm-ssp"
-typedef struct StrongARMSSPState StrongARMSSPState;
-DECLARE_INSTANCE_CHECKER(StrongARMSSPState, STRONGARM_SSP,
- TYPE_STRONGARM_SSP)
+OBJECT_DECLARE_SIMPLE_TYPE(StrongARMSSPState, STRONGARM_SSP)
struct StrongARMSSPState {
SysBusDevice parent_obj;
*/
#define TYPE_TOSA_MISC_GPIO "tosa-misc-gpio"
-typedef struct TosaMiscGPIOState TosaMiscGPIOState;
-DECLARE_INSTANCE_CHECKER(TosaMiscGPIOState, TOSA_MISC_GPIO,
- TYPE_TOSA_MISC_GPIO)
+OBJECT_DECLARE_SIMPLE_TYPE(TosaMiscGPIOState, TOSA_MISC_GPIO)
struct TosaMiscGPIOState {
SysBusDevice parent_obj;
}
#define TYPE_TOSA_DAC "tosa_dac"
-typedef struct TosaDACState TosaDACState;
-DECLARE_INSTANCE_CHECKER(TosaDACState, TOSA_DAC,
- TYPE_TOSA_DAC)
+OBJECT_DECLARE_SIMPLE_TYPE(TosaDACState, TOSA_DAC)
struct TosaDACState {
I2CSlave parent_obj;
/* Primary interrupt controller. */
#define TYPE_VERSATILE_PB_SIC "versatilepb_sic"
-typedef struct vpb_sic_state vpb_sic_state;
-DECLARE_INSTANCE_CHECKER(vpb_sic_state, VERSATILE_PB_SIC,
- TYPE_VERSATILE_PB_SIC)
+OBJECT_DECLARE_SIMPLE_TYPE(vpb_sic_state, VERSATILE_PB_SIC)
struct vpb_sic_state {
SysBusDevice parent_obj;
MachineClass parent;
VEDBoardInfo *daughterboard;
};
-typedef struct VexpressMachineClass VexpressMachineClass;
struct VexpressMachineState {
MachineState parent;
bool secure;
bool virt;
};
-typedef struct VexpressMachineState VexpressMachineState;
#define TYPE_VEXPRESS_MACHINE "vexpress"
#define TYPE_VEXPRESS_A9_MACHINE MACHINE_TYPE_NAME("vexpress-a9")
#define TYPE_VEXPRESS_A15_MACHINE MACHINE_TYPE_NAME("vexpress-a15")
-DECLARE_OBJ_CHECKERS(VexpressMachineState, VexpressMachineClass,
- VEXPRESS_MACHINE, TYPE_VEXPRESS_MACHINE)
+OBJECT_DECLARE_TYPE(VexpressMachineState, VexpressMachineClass, VEXPRESS_MACHINE)
typedef void DBoardInitFn(const VexpressMachineState *machine,
ram_addr_t ram_size,
#include "qom/object.h"
#define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9")
-typedef struct ZynqMachineState ZynqMachineState;
-DECLARE_INSTANCE_CHECKER(ZynqMachineState, ZYNQ_MACHINE,
- TYPE_ZYNQ_MACHINE)
+OBJECT_DECLARE_SIMPLE_TYPE(ZynqMachineState, ZYNQ_MACHINE)
/* board base frequency: 33.333333 MHz */
#define PS_CLK_FREQUENCY (100 * 1000 * 1000 / 3)
#include "qom/object.h"
#define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt")
-typedef struct VersalVirt VersalVirt;
-DECLARE_INSTANCE_CHECKER(VersalVirt, XLNX_VERSAL_VIRT_MACHINE,
- TYPE_XLNX_VERSAL_VIRT_MACHINE)
+OBJECT_DECLARE_SIMPLE_TYPE(VersalVirt, XLNX_VERSAL_VIRT_MACHINE)
struct VersalVirt {
MachineState parent_obj;
struct arm_boot_info binfo;
};
-typedef struct XlnxZCU102 XlnxZCU102;
#define TYPE_ZCU102_MACHINE MACHINE_TYPE_NAME("xlnx-zcu102")
-DECLARE_INSTANCE_CHECKER(XlnxZCU102, ZCU102_MACHINE,
- TYPE_ZCU102_MACHINE)
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxZCU102, ZCU102_MACHINE)
static bool zcu102_get_secure(Object *obj, Error **errp)
uint32_t cur_reg;
int pos;
};
-typedef struct ZipitLCD ZipitLCD;
#define TYPE_ZIPIT_LCD "zipit-lcd"
-DECLARE_INSTANCE_CHECKER(ZipitLCD, ZIPIT_LCD,
- TYPE_ZIPIT_LCD)
+OBJECT_DECLARE_SIMPLE_TYPE(ZipitLCD, ZIPIT_LCD)
static uint32_t zipit_lcd_transfer(SSISlave *dev, uint32_t value)
{
};
#define TYPE_AER915 "aer915"
-typedef struct AER915State AER915State;
-DECLARE_INSTANCE_CHECKER(AER915State, AER915,
- TYPE_AER915)
+OBJECT_DECLARE_SIMPLE_TYPE(AER915State, AER915)
struct AER915State {
I2CSlave parent_obj;
#define MUTE_SHIFT 15
#define TYPE_AC97 "AC97"
-typedef struct AC97LinkState AC97LinkState;
-DECLARE_INSTANCE_CHECKER(AC97LinkState, AC97,
- TYPE_AC97)
+OBJECT_DECLARE_SIMPLE_TYPE(AC97LinkState, AC97)
#define REC_MASK 7
enum {
#define SHIFT 1
#define TYPE_ADLIB "adlib"
-typedef struct AdlibState AdlibState;
-DECLARE_INSTANCE_CHECKER(AdlibState, ADLIB,
- TYPE_ADLIB)
+OBJECT_DECLARE_SIMPLE_TYPE(AdlibState, ADLIB)
struct AdlibState {
ISADevice parent_obj;
};
#define TYPE_ES1370 "ES1370"
-DECLARE_INSTANCE_CHECKER(ES1370State, ES1370,
- TYPE_ES1370)
+OBJECT_DECLARE_SIMPLE_TYPE(ES1370State, ES1370)
static void es1370_dac1_calc_freq (ES1370State *s, uint32_t ctl,
uint32_t *old_freq, uint32_t *new_freq);
#endif
#define TYPE_GUS "gus"
-typedef struct GUSState GUSState;
-DECLARE_INSTANCE_CHECKER(GUSState, GUS,
- TYPE_GUS)
+OBJECT_DECLARE_SIMPLE_TYPE(GUSState, GUS)
struct GUSState {
ISADevice dev;
};
#define TYPE_HDA_AUDIO "hda-audio"
-DECLARE_INSTANCE_CHECKER(HDAAudioState, HDA_AUDIO,
- TYPE_HDA_AUDIO)
+OBJECT_DECLARE_SIMPLE_TYPE(HDAAudioState, HDA_AUDIO)
struct HDAAudioState {
HDACodecDevice hda;
#define TYPE_HDA_CODEC_DEVICE "hda-codec"
OBJECT_DECLARE_TYPE(HDACodecDevice, HDACodecDeviceClass,
- hda_codec_device, HDA_CODEC_DEVICE)
+ HDA_CODEC_DEVICE)
#define TYPE_HDA_BUS "HDA"
-typedef struct HDACodecBus HDACodecBus;
-DECLARE_INSTANCE_CHECKER(HDACodecBus, HDA_BUS,
- TYPE_HDA_BUS)
+OBJECT_DECLARE_SIMPLE_TYPE(HDACodecBus, HDA_BUS)
typedef void (*hda_codec_response_func)(HDACodecDevice *dev,
#define MP_AUDIO_CLOCK_24MHZ (1 << 9)
#define MP_AUDIO_MONO (1 << 14)
-typedef struct mv88w8618_audio_state mv88w8618_audio_state;
-DECLARE_INSTANCE_CHECKER(mv88w8618_audio_state, MV88W8618_AUDIO,
- TYPE_MV88W8618_AUDIO)
+OBJECT_DECLARE_SIMPLE_TYPE(mv88w8618_audio_state, MV88W8618_AUDIO)
struct mv88w8618_audio_state {
SysBusDevice parent_obj;
};
#define TYPE_MILKYMIST_AC97 "milkymist-ac97"
-typedef struct MilkymistAC97State MilkymistAC97State;
-DECLARE_INSTANCE_CHECKER(MilkymistAC97State, MILKYMIST_AC97,
- TYPE_MILKYMIST_AC97)
+OBJECT_DECLARE_SIMPLE_TYPE(MilkymistAC97State, MILKYMIST_AC97)
struct MilkymistAC97State {
SysBusDevice parent_obj;
#define PCSPK_MAX_FREQ (PCSPK_SAMPLE_RATE >> 1)
#define PCSPK_MIN_COUNT DIV_ROUND_UP(PIT_FREQ, PCSPK_MAX_FREQ)
-typedef struct PCSpkState PCSpkState;
-DECLARE_INSTANCE_CHECKER(PCSpkState, PC_SPEAKER,
- TYPE_PC_SPEAKER)
+OBJECT_DECLARE_SIMPLE_TYPE(PCSpkState, PC_SPEAKER)
struct PCSpkState {
ISADevice parent_obj;
} pl041_channel;
#define TYPE_PL041 "pl041"
-typedef struct PL041State PL041State;
-DECLARE_INSTANCE_CHECKER(PL041State, PL041,
- TYPE_PL041)
+OBJECT_DECLARE_SIMPLE_TYPE(PL041State, PL041)
struct PL041State {
SysBusDevice parent_obj;
static const char e3[] = "COPYRIGHT (C) CREATIVE TECHNOLOGY LTD, 1992.";
#define TYPE_SB16 "sb16"
-typedef struct SB16State SB16State;
-DECLARE_INSTANCE_CHECKER(SB16State, SB16,
- TYPE_SB16)
+OBJECT_DECLARE_SIMPLE_TYPE(SB16State, SB16)
struct SB16State {
ISADevice parent_obj;
int dac_hz;
} WMRate;
-typedef struct WM8750State WM8750State;
-DECLARE_INSTANCE_CHECKER(WM8750State, WM8750,
- TYPE_WM8750)
+OBJECT_DECLARE_SIMPLE_TYPE(WM8750State, WM8750)
struct WM8750State {
I2CSlave parent_obj;
/* qdev floppy bus */
#define TYPE_FLOPPY_BUS "floppy-bus"
-typedef struct FloppyBus FloppyBus;
-DECLARE_INSTANCE_CHECKER(FloppyBus, FLOPPY_BUS,
- TYPE_FLOPPY_BUS)
+OBJECT_DECLARE_SIMPLE_TYPE(FloppyBus, FLOPPY_BUS)
typedef struct FDCtrl FDCtrl;
typedef struct FDrive FDrive;
#define TYPE_FLOPPY_DRIVE "floppy"
-typedef struct FloppyDrive FloppyDrive;
-DECLARE_INSTANCE_CHECKER(FloppyDrive, FLOPPY_DRIVE,
- TYPE_FLOPPY_DRIVE)
+OBJECT_DECLARE_SIMPLE_TYPE(FloppyDrive, FLOPPY_DRIVE)
struct FloppyDrive {
DeviceState qdev;
}
#define TYPE_SYSBUS_FDC "base-sysbus-fdc"
-typedef struct FDCtrlSysBus FDCtrlSysBus;
-DECLARE_INSTANCE_CHECKER(FDCtrlSysBus, SYSBUS_FDC,
- TYPE_SYSBUS_FDC)
+OBJECT_DECLARE_SIMPLE_TYPE(FDCtrlSysBus, SYSBUS_FDC)
struct FDCtrlSysBus {
/*< private >*/
struct FDCtrl state;
};
-typedef struct FDCtrlISABus FDCtrlISABus;
-DECLARE_INSTANCE_CHECKER(FDCtrlISABus, ISA_FDC,
- TYPE_ISA_FDC)
+OBJECT_DECLARE_SIMPLE_TYPE(FDCtrlISABus, ISA_FDC)
struct FDCtrlISABus {
ISADevice parent_obj;
const FlashPartInfo *pi;
};
-typedef struct Flash Flash;
struct M25P80Class {
SSISlaveClass parent_class;
FlashPartInfo *pi;
};
-typedef struct M25P80Class M25P80Class;
#define TYPE_M25P80 "m25p80-generic"
-DECLARE_OBJ_CHECKERS(Flash, M25P80Class,
- M25P80, TYPE_M25P80)
+OBJECT_DECLARE_TYPE(Flash, M25P80Class, M25P80)
static inline Manufacturer get_man(Flash *s)
{
#define TYPE_NAND "nand"
-DECLARE_INSTANCE_CHECKER(NANDFlashState, NAND,
- TYPE_NAND)
+OBJECT_DECLARE_SIMPLE_TYPE(NANDFlashState, NAND)
static void mem_and(uint8_t *dest, const uint8_t *src, size_t n)
{
#define BLOCK_SHIFT (PAGE_SHIFT + 6)
#define TYPE_ONE_NAND "onenand"
-typedef struct OneNANDState OneNANDState;
-DECLARE_INSTANCE_CHECKER(OneNANDState, ONE_NAND,
- TYPE_ONE_NAND)
+OBJECT_DECLARE_SIMPLE_TYPE(OneNANDState, ONE_NAND)
struct OneNANDState {
SysBusDevice parent_obj;
#include "qom/object.h"
#define TYPE_ISA_DEBUGCON_DEVICE "isa-debugcon"
-typedef struct ISADebugconState ISADebugconState;
-DECLARE_INSTANCE_CHECKER(ISADebugconState, ISA_DEBUGCON_DEVICE,
- TYPE_ISA_DEBUGCON_DEVICE)
+OBJECT_DECLARE_SIMPLE_TYPE(ISADebugconState, ISA_DEBUGCON_DEVICE)
//#define DEBUG_DEBUGCON
} Exynos4210UartFIFO;
#define TYPE_EXYNOS4210_UART "exynos4210.uart"
-typedef struct Exynos4210UartState Exynos4210UartState;
-DECLARE_INSTANCE_CHECKER(Exynos4210UartState, EXYNOS4210_UART,
- TYPE_EXYNOS4210_UART)
+OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210UartState, EXYNOS4210_UART)
struct Exynos4210UartState {
SysBusDevice parent_obj;
#define FIFO_LENGTH 1024
-typedef struct UART UART;
-DECLARE_INSTANCE_CHECKER(UART, GRLIB_APB_UART,
- TYPE_GRLIB_APB_UART)
+OBJECT_DECLARE_SIMPLE_TYPE(UART, GRLIB_APB_UART)
struct UART {
SysBusDevice parent_obj;
#define TYPE_IPOCTAL "ipoctal232"
-DECLARE_INSTANCE_CHECKER(IPOctalState, IPOCTAL,
- TYPE_IPOCTAL)
+OBJECT_DECLARE_SIMPLE_TYPE(IPOctalState, IPOCTAL)
static const VMStateDescription vmstate_scc2698_channel = {
.name = "scc2698_channel",
JRX_FULL = (1<<8),
};
-typedef struct LM32JuartState LM32JuartState;
-DECLARE_INSTANCE_CHECKER(LM32JuartState, LM32_JUART,
- TYPE_LM32_JUART)
+OBJECT_DECLARE_SIMPLE_TYPE(LM32JuartState, LM32_JUART)
struct LM32JuartState {
SysBusDevice parent_obj;
};
#define TYPE_LM32_UART "lm32-uart"
-typedef struct LM32UartState LM32UartState;
-DECLARE_INSTANCE_CHECKER(LM32UartState, LM32_UART,
- TYPE_LM32_UART)
+OBJECT_DECLARE_SIMPLE_TYPE(LM32UartState, LM32_UART)
struct LM32UartState {
SysBusDevice parent_obj;
qemu_irq irq;
CharBackend chr;
};
-typedef struct mcf_uart_state mcf_uart_state;
#define TYPE_MCF_UART "mcf-uart"
-DECLARE_INSTANCE_CHECKER(mcf_uart_state, MCF_UART,
- TYPE_MCF_UART)
+OBJECT_DECLARE_SIMPLE_TYPE(mcf_uart_state, MCF_UART)
/* UART Status Register bits. */
#define MCF_UART_RxRDY 0x01
};
#define TYPE_MILKYMIST_UART "milkymist-uart"
-typedef struct MilkymistUartState MilkymistUartState;
-DECLARE_INSTANCE_CHECKER(MilkymistUartState, MILKYMIST_UART,
- TYPE_MILKYMIST_UART)
+OBJECT_DECLARE_SIMPLE_TYPE(MilkymistUartState, MILKYMIST_UART)
struct MilkymistUartState {
SysBusDevice parent_obj;
} ParallelState;
#define TYPE_ISA_PARALLEL "isa-parallel"
-typedef struct ISAParallelState ISAParallelState;
-DECLARE_INSTANCE_CHECKER(ISAParallelState, ISA_PARALLEL,
- TYPE_ISA_PARALLEL)
+OBJECT_DECLARE_SIMPLE_TYPE(ISAParallelState, ISA_PARALLEL)
struct ISAParallelState {
ISADevice parent_obj;
#include "migration/vmstate.h"
#include "qom/object.h"
-typedef struct ISASerialState ISASerialState;
-DECLARE_INSTANCE_CHECKER(ISASerialState, ISA_SERIAL,
- TYPE_ISA_SERIAL)
+OBJECT_DECLARE_SIMPLE_TYPE(ISASerialState, ISA_SERIAL)
struct ISASerialState {
ISADevice parent_obj;
SerialState state;
uint8_t prog_if;
};
-typedef struct PCISerialState PCISerialState;
#define TYPE_PCI_SERIAL "pci-serial"
-DECLARE_INSTANCE_CHECKER(PCISerialState, PCI_SERIAL,
- TYPE_PCI_SERIAL)
+OBJECT_DECLARE_SIMPLE_TYPE(PCISerialState, PCI_SERIAL)
static void serial_pci_realize(PCIDevice *dev, Error **errp)
{
uint32_t in, out;
uint8_t buf[VTERM_BUFSIZE];
};
-typedef struct SpaprVioVty SpaprVioVty;
#define TYPE_VIO_SPAPR_VTY_DEVICE "spapr-vty"
-DECLARE_INSTANCE_CHECKER(SpaprVioVty, VIO_SPAPR_VTY_DEVICE,
- TYPE_VIO_SPAPR_VTY_DEVICE)
+OBJECT_DECLARE_SIMPLE_TYPE(SpaprVioVty, VIO_SPAPR_VTY_DEVICE)
static int vty_can_receive(void *opaque)
{
#define CONTROL_IE 0x10
#define TYPE_XILINX_UARTLITE "xlnx.xps-uartlite"
-typedef struct XilinxUARTLite XilinxUARTLite;
-DECLARE_INSTANCE_CHECKER(XilinxUARTLite, XILINX_UARTLITE,
- TYPE_XILINX_UARTLITE)
+OBJECT_DECLARE_SIMPLE_TYPE(XilinxUARTLite, XILINX_UARTLITE)
struct XilinxUARTLite {
SysBusDevice parent_obj;
#include "qom/object.h"
#define TYPE_REALVIEW_MPCORE_RIRQ "realview_mpcore"
-typedef struct mpcore_rirq_state mpcore_rirq_state;
-DECLARE_INSTANCE_CHECKER(mpcore_rirq_state, REALVIEW_MPCORE_RIRQ,
- TYPE_REALVIEW_MPCORE_RIRQ)
+OBJECT_DECLARE_SIMPLE_TYPE(mpcore_rirq_state, REALVIEW_MPCORE_RIRQ)
/* Dummy PIC to route IRQ lines. The baseboard has 4 independent IRQ
controllers. The output of these, plus some of the raw input lines
int cycle;
int output;
};
-typedef struct ADS7846State ADS7846State;
#define TYPE_ADS7846 "ads7846"
-DECLARE_INSTANCE_CHECKER(ADS7846State, ADS7846,
- TYPE_ADS7846)
+OBJECT_DECLARE_SIMPLE_TYPE(ADS7846State, ADS7846)
/* Control-byte bitfields */
#define CB_PD0 (1 << 0)
#include "qom/object.h"
#define TYPE_ARTIST "artist"
-typedef struct ARTISTState ARTISTState;
-DECLARE_INSTANCE_CHECKER(ARTISTState, ARTIST,
- TYPE_ARTIST)
+OBJECT_DECLARE_SIMPLE_TYPE(ARTISTState, ARTIST)
#ifdef HOST_WORDS_BIGENDIAN
#define ROP8OFF(_i) (3 - (_i))
#define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159
#define TYPE_ATI_VGA "ati-vga"
-typedef struct ATIVGAState ATIVGAState;
-DECLARE_INSTANCE_CHECKER(ATIVGAState, ATI_VGA,
- TYPE_ATI_VGA)
+OBJECT_DECLARE_SIMPLE_TYPE(ATIVGAState, ATI_VGA)
typedef struct ATIVGARegs {
uint32_t mm_index;
/* device state */
BochsDisplayMode mode;
};
-typedef struct BochsDisplayState BochsDisplayState;
#define TYPE_BOCHS_DISPLAY "bochs-display"
-DECLARE_INSTANCE_CHECKER(BochsDisplayState, BOCHS_DISPLAY,
- TYPE_BOCHS_DISPLAY)
+OBJECT_DECLARE_SIMPLE_TYPE(BochsDisplayState, BOCHS_DISPLAY)
static const VMStateDescription vmstate_bochs_display = {
.name = "bochs-display",
#define CG3_VRAM_OFFSET 0x800000
#define TYPE_CG3 "cgthree"
-typedef struct CG3State CG3State;
-DECLARE_INSTANCE_CHECKER(CG3State, CG3,
- TYPE_CG3)
+OBJECT_DECLARE_SIMPLE_TYPE(CG3State, CG3)
struct CG3State {
SysBusDevice parent_obj;
PCIDevice dev;
CirrusVGAState cirrus_vga;
};
-typedef struct PCICirrusVGAState PCICirrusVGAState;
#define TYPE_PCI_CIRRUS_VGA "cirrus-vga"
-DECLARE_INSTANCE_CHECKER(PCICirrusVGAState, PCI_CIRRUS_VGA,
- TYPE_PCI_CIRRUS_VGA)
+OBJECT_DECLARE_SIMPLE_TYPE(PCICirrusVGAState, PCI_CIRRUS_VGA)
static uint8_t rop_to_index[256];
#include "qom/object.h"
#define TYPE_ISA_CIRRUS_VGA "isa-cirrus-vga"
-typedef struct ISACirrusVGAState ISACirrusVGAState;
-DECLARE_INSTANCE_CHECKER(ISACirrusVGAState, ISA_CIRRUS_VGA,
- TYPE_ISA_CIRRUS_VGA)
+OBJECT_DECLARE_SIMPLE_TYPE(ISACirrusVGAState, ISA_CIRRUS_VGA)
struct ISACirrusVGAState {
ISADevice parent_obj;
};
#define TYPE_EXYNOS4210_FIMD "exynos4210.fimd"
-typedef struct Exynos4210fimdState Exynos4210fimdState;
-DECLARE_INSTANCE_CHECKER(Exynos4210fimdState, EXYNOS4210_FIMD,
- TYPE_EXYNOS4210_FIMD)
+OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210fimdState, EXYNOS4210_FIMD)
struct Exynos4210fimdState {
SysBusDevice parent_obj;
}
#define TYPE_G364 "sysbus-g364"
-typedef struct G364SysBusState G364SysBusState;
-DECLARE_INSTANCE_CHECKER(G364SysBusState, G364,
- TYPE_G364)
+OBJECT_DECLARE_SIMPLE_TYPE(G364SysBusState, G364)
struct G364SysBusState {
SysBusDevice parent_obj;
} screen_state_t;
#define TYPE_JAZZ_LED "jazz-led"
-typedef struct LedState LedState;
-DECLARE_INSTANCE_CHECKER(LedState, JAZZ_LED,
- TYPE_JAZZ_LED)
+OBJECT_DECLARE_SIMPLE_TYPE(LedState, JAZZ_LED)
struct LedState {
SysBusDevice parent_obj;
} QEMU_PACKED;
#define TYPE_MILKYMIST_TMU2 "milkymist-tmu2"
-typedef struct MilkymistTMU2State MilkymistTMU2State;
-DECLARE_INSTANCE_CHECKER(MilkymistTMU2State, MILKYMIST_TMU2,
- TYPE_MILKYMIST_TMU2)
+OBJECT_DECLARE_SIMPLE_TYPE(MilkymistTMU2State, MILKYMIST_TMU2)
struct MilkymistTMU2State {
SysBusDevice parent_obj;
};
#define TYPE_MILKYMIST_VGAFB "milkymist-vgafb"
-typedef struct MilkymistVgafbState MilkymistVgafbState;
-DECLARE_INSTANCE_CHECKER(MilkymistVgafbState, MILKYMIST_VGAFB,
- TYPE_MILKYMIST_VGAFB)
+OBJECT_DECLARE_SIMPLE_TYPE(MilkymistVgafbState, MILKYMIST_VGAFB)
struct MilkymistVgafbState {
SysBusDevice parent_obj;
#include "hw/m68k/next-cube.h"
#include "qom/object.h"
-typedef struct NeXTFbState NeXTFbState;
-DECLARE_INSTANCE_CHECKER(NeXTFbState, NEXTFB,
- TYPE_NEXTFB)
+OBJECT_DECLARE_SIMPLE_TYPE(NeXTFbState, NEXTFB)
struct NeXTFbState {
SysBusDevice parent_obj;
};
#define TYPE_PL110 "pl110"
-typedef struct PL110State PL110State;
-DECLARE_INSTANCE_CHECKER(PL110State, PL110,
- TYPE_PL110)
+OBJECT_DECLARE_SIMPLE_TYPE(PL110State, PL110)
struct PL110State {
SysBusDevice parent_obj;
QXLRect dirty[QXL_NUM_DIRTY_RECTS];
QEMUBH *update_area_bh;
};
-typedef struct PCIQXLDevice PCIQXLDevice;
#define TYPE_PCI_QXL "pci-qxl"
-DECLARE_INSTANCE_CHECKER(PCIQXLDevice, PCI_QXL,
- TYPE_PCI_QXL)
+OBJECT_DECLARE_SIMPLE_TYPE(PCIQXLDevice, PCI_QXL)
#define PANIC_ON(x) if ((x)) { \
printf("%s: PANIC %s failed\n", __func__, #x); \
#define SII9022_INT_STATUS_PLUGGED 0x04;
#define TYPE_SII9022 "sii9022"
-typedef struct sii9022_state sii9022_state;
-DECLARE_INSTANCE_CHECKER(sii9022_state, SII9022,
- TYPE_SII9022)
+OBJECT_DECLARE_SIMPLE_TYPE(sii9022_state, SII9022)
struct sii9022_state {
I2CSlave parent_obj;
};
#define TYPE_SYSBUS_SM501 "sysbus-sm501"
-typedef struct SM501SysBusState SM501SysBusState;
-DECLARE_INSTANCE_CHECKER(SM501SysBusState, SYSBUS_SM501,
- TYPE_SYSBUS_SM501)
+OBJECT_DECLARE_SIMPLE_TYPE(SM501SysBusState, SYSBUS_SM501)
struct SM501SysBusState {
/*< private >*/
};
#define TYPE_PCI_SM501 "sm501"
-typedef struct SM501PCIState SM501PCIState;
-DECLARE_INSTANCE_CHECKER(SM501PCIState, PCI_SM501,
- TYPE_PCI_SM501)
+OBJECT_DECLARE_SIMPLE_TYPE(SM501PCIState, PCI_SM501)
struct SM501PCIState {
/*< private >*/
};
#define TYPE_SSD0303 "ssd0303"
-typedef struct ssd0303_state ssd0303_state;
-DECLARE_INSTANCE_CHECKER(ssd0303_state, SSD0303,
- TYPE_SSD0303)
+OBJECT_DECLARE_SIMPLE_TYPE(ssd0303_state, SSD0303)
struct ssd0303_state {
I2CSlave parent_obj;
uint32_t mode;
uint8_t framebuffer[128 * 80 / 2];
};
-typedef struct ssd0323_state ssd0323_state;
#define TYPE_SSD0323 "ssd0323"
-DECLARE_INSTANCE_CHECKER(ssd0323_state, SSD0323,
- TYPE_SSD0323)
+OBJECT_DECLARE_SIMPLE_TYPE(ssd0323_state, SSD0323)
static uint32_t ssd0323_transfer(SSISlave *dev, uint32_t data)
#define TCX_THC_CURSBITS 0x980
#define TYPE_TCX "SUNW,tcx"
-typedef struct TCXState TCXState;
-DECLARE_INSTANCE_CHECKER(TCXState, TCX,
- TYPE_TCX)
+OBJECT_DECLARE_SIMPLE_TYPE(TCXState, TCX)
struct TCXState {
SysBusDevice parent_obj;
#include "qom/object.h"
#define TYPE_ISA_VGA "isa-vga"
-typedef struct ISAVGAState ISAVGAState;
-DECLARE_INSTANCE_CHECKER(ISAVGAState, ISA_VGA,
- TYPE_ISA_VGA)
+OBJECT_DECLARE_SIMPLE_TYPE(ISAVGAState, ISA_VGA)
struct ISAVGAState {
ISADevice parent_obj;
MemoryRegion mrs[4];
uint8_t edid[256];
};
-typedef struct PCIVGAState PCIVGAState;
#define TYPE_PCI_VGA "pci-vga"
-DECLARE_INSTANCE_CHECKER(PCIVGAState, PCI_VGA,
- TYPE_PCI_VGA)
+OBJECT_DECLARE_SIMPLE_TYPE(PCIVGAState, PCI_VGA)
static const VMStateDescription vmstate_vga_pci = {
.name = "vga",
*/
#define TYPE_VIRTIO_VGA_BASE "virtio-vga-base"
OBJECT_DECLARE_TYPE(VirtIOVGABase, VirtIOVGABaseClass,
- virtio_vga_base, VIRTIO_VGA_BASE)
+ VIRTIO_VGA_BASE)
struct VirtIOVGABase {
VirtIOPCIProxy parent_obj;
#include "qom/object.h"
#define TYPE_I82374 "i82374"
-typedef struct I82374State I82374State;
-DECLARE_INSTANCE_CHECKER(I82374State, I82374,
- TYPE_I82374)
+OBJECT_DECLARE_SIMPLE_TYPE(I82374State, I82374)
//#define DEBUG_I82374
};
#define TYPE_PL330 "pl330"
-DECLARE_INSTANCE_CHECKER(PL330State, PL330,
- TYPE_PL330)
+OBJECT_DECLARE_SIMPLE_TYPE(PL330State, PL330)
static const VMStateDescription vmstate_pl330 = {
.name = "pl330",
#define PUV3_DMA_CH(offset) ((offset) >> 8)
#define TYPE_PUV3_DMA "puv3_dma"
-typedef struct PUV3DMAState PUV3DMAState;
-DECLARE_INSTANCE_CHECKER(PUV3DMAState, PUV3_DMA,
- TYPE_PUV3_DMA)
+OBJECT_DECLARE_SIMPLE_TYPE(PUV3DMAState, PUV3_DMA)
struct PUV3DMAState {
SysBusDevice parent_obj;
} PXA2xxDMAChannel;
#define TYPE_PXA2XX_DMA "pxa2xx-dma"
-typedef struct PXA2xxDMAState PXA2xxDMAState;
-DECLARE_INSTANCE_CHECKER(PXA2xxDMAState, PXA2XX_DMA,
- TYPE_PXA2XX_DMA)
+OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxDMAState, PXA2XX_DMA)
struct PXA2xxDMAState {
SysBusDevice parent_obj;
#define DMA_FLAG_ADDR_INTR 0x0400
#define TYPE_RC4030 "rc4030"
-typedef struct rc4030State rc4030State;
-DECLARE_INSTANCE_CHECKER(rc4030State, RC4030,
- TYPE_RC4030)
+OBJECT_DECLARE_SIMPLE_TYPE(rc4030State, RC4030)
#define TYPE_RC4030_IOMMU_MEMORY_REGION "rc4030-iommu-memory-region"
#define TYPE_XILINX_AXI_DMA_DATA_STREAM "xilinx-axi-dma-data-stream"
#define TYPE_XILINX_AXI_DMA_CONTROL_STREAM "xilinx-axi-dma-control-stream"
-typedef struct XilinxAXIDMA XilinxAXIDMA;
-DECLARE_INSTANCE_CHECKER(XilinxAXIDMA, XILINX_AXI_DMA,
- TYPE_XILINX_AXI_DMA)
+OBJECT_DECLARE_SIMPLE_TYPE(XilinxAXIDMA, XILINX_AXI_DMA)
typedef struct XilinxAXIDMAStreamSlave XilinxAXIDMAStreamSlave;
DECLARE_INSTANCE_CHECKER(XilinxAXIDMAStreamSlave, XILINX_AXI_DMA_DATA_STREAM,
#include "qom/object.h"
#define TYPE_GPIOKEY "gpio-key"
-typedef struct GPIOKEYState GPIOKEYState;
-DECLARE_INSTANCE_CHECKER(GPIOKEYState, GPIOKEY,
- TYPE_GPIOKEY)
+OBJECT_DECLARE_SIMPLE_TYPE(GPIOKEYState, GPIOKEY)
#define GPIO_KEY_LATENCY 100 /* 100ms */
struct GPIOKEYState {
*/
#include "qemu/osdep.h"
-#include "hw/hw.h"
#include "hw/i2c/i2c.h"
-#include "hw/hw.h"
#include "hw/irq.h"
#include "migration/vmstate.h"
#include "qemu/log.h"
#include "qom/object.h"
#define TYPE_MAX7310 "max7310"
-typedef struct MAX7310State MAX7310State;
-DECLARE_INSTANCE_CHECKER(MAX7310State, MAX7310,
- TYPE_MAX7310)
+OBJECT_DECLARE_SIMPLE_TYPE(MAX7310State, MAX7310)
struct MAX7310State {
I2CSlave parent_obj;
static void max7310_gpio_set(void *opaque, int line, int level)
{
MAX7310State *s = (MAX7310State *) opaque;
- if (line >= ARRAY_SIZE(s->handler) || line < 0)
- hw_error("bad GPIO line");
+ assert(line >= 0 && line < ARRAY_SIZE(s->handler));
if (level)
s->level |= s->direction & (1 << line);
#include "qom/object.h"
#define TYPE_MPC8XXX_GPIO "mpc8xxx_gpio"
-typedef struct MPC8XXXGPIOState MPC8XXXGPIOState;
-DECLARE_INSTANCE_CHECKER(MPC8XXXGPIOState, MPC8XXX_GPIO,
- TYPE_MPC8XXX_GPIO)
+OBJECT_DECLARE_SIMPLE_TYPE(MPC8XXXGPIOState, MPC8XXX_GPIO)
struct MPC8XXXGPIOState {
SysBusDevice parent_obj;
{ 0x00, 0x00, 0x00, 0x00, 0x61, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 };
#define TYPE_PL061 "pl061"
-typedef struct PL061State PL061State;
-DECLARE_INSTANCE_CHECKER(PL061State, PL061,
- TYPE_PL061)
+OBJECT_DECLARE_SIMPLE_TYPE(PL061State, PL061)
#define N_GPIOS 8
#include "qemu/log.h"
#define TYPE_PUV3_GPIO "puv3_gpio"
-typedef struct PUV3GPIOState PUV3GPIOState;
-DECLARE_INSTANCE_CHECKER(PUV3GPIOState, PUV3_GPIO,
- TYPE_PUV3_GPIO)
+OBJECT_DECLARE_SIMPLE_TYPE(PUV3GPIOState, PUV3_GPIO)
struct PUV3GPIOState {
SysBusDevice parent_obj;
/* SCOOP devices */
#define TYPE_SCOOP "scoop"
-typedef struct ScoopInfo ScoopInfo;
-DECLARE_INSTANCE_CHECKER(ScoopInfo, SCOOP,
- TYPE_SCOOP)
+OBJECT_DECLARE_SIMPLE_TYPE(ScoopInfo, SCOOP)
struct ScoopInfo {
SysBusDevice parent_obj;
#define DINO_MEM_CHUNK_SIZE (8 * MiB)
-typedef struct DinoState DinoState;
-DECLARE_INSTANCE_CHECKER(DinoState, DINO_PCI_HOST_BRIDGE,
- TYPE_DINO_PCI_HOST_BRIDGE)
+OBJECT_DECLARE_SIMPLE_TYPE(DinoState, DINO_PCI_HOST_BRIDGE)
#define DINO800_REGS (1 + (DINO_TLTIM - DINO_GMASK) / 4)
static const uint32_t reg800_keep_bits[DINO800_REGS] = {
#define ICR_BUS_ERROR_BIT LASI_BIT(8) /* bit 8 in ICR */
#define ICR_TOC_BIT LASI_BIT(1) /* bit 1 in ICR */
-typedef struct LasiState LasiState;
-DECLARE_INSTANCE_CHECKER(LasiState, LASI_CHIP,
- TYPE_LASI_CHIP)
+OBJECT_DECLARE_SIMPLE_TYPE(LasiState, LASI_CHIP)
struct LasiState {
PCIHostState parent_obj;
struct hyperv_message_page *msg_page;
struct hyperv_event_flags_page *event_page;
};
-typedef struct SynICState SynICState;
#define TYPE_SYNIC "hyperv-synic"
-DECLARE_INSTANCE_CHECKER(SynICState, SYNIC,
- TYPE_SYNIC)
+OBJECT_DECLARE_SIMPLE_TYPE(SynICState, SYNIC)
static bool synic_enabled;
QLIST_HEAD(, TestMsgConn) msg_conns;
QLIST_HEAD(, TestEvtConn) evt_conns;
};
-typedef struct HypervTestDev HypervTestDev;
#define TYPE_HYPERV_TEST_DEV "hyperv-testdev"
-DECLARE_INSTANCE_CHECKER(HypervTestDev, HYPERV_TEST_DEV,
- TYPE_HYPERV_TEST_DEV)
+OBJECT_DECLARE_SIMPLE_TYPE(HypervTestDev, HYPERV_TEST_DEV)
enum {
HV_TEST_DEV_SINT_ROUTE_CREATE = 1,
/* GPIO interface. */
#define TYPE_GPIO_I2C "gpio_i2c"
-typedef struct GPIOI2CState GPIOI2CState;
-DECLARE_INSTANCE_CHECKER(GPIOI2CState, GPIO_I2C,
- TYPE_GPIO_I2C)
+OBJECT_DECLARE_SIMPLE_TYPE(GPIOI2CState, GPIO_I2C)
struct GPIOI2CState {
SysBusDevice parent_obj;
#endif
#define TYPE_EXYNOS4_I2C "exynos4210.i2c"
-typedef struct Exynos4210I2CState Exynos4210I2CState;
-DECLARE_INSTANCE_CHECKER(Exynos4210I2CState, EXYNOS4_I2C,
- TYPE_EXYNOS4_I2C)
+OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210I2CState, EXYNOS4_I2C)
/* Exynos4210 I2C memory map */
#define EXYNOS4_I2C_MEM_SIZE 0x14
#endif
#define TYPE_MPC_I2C "mpc-i2c"
-typedef struct MPCI2CState MPCI2CState;
-DECLARE_INSTANCE_CHECKER(MPCI2CState, MPC_I2C,
- TYPE_MPC_I2C)
+OBJECT_DECLARE_SIMPLE_TYPE(MPCI2CState, MPC_I2C)
#define MPC_I2C_ADR 0x00
#define MPC_I2C_FDR 0x04
#define TYPE_SMBUS_EEPROM "smbus-eeprom"
-typedef struct SMBusEEPROMDevice SMBusEEPROMDevice;
-DECLARE_INSTANCE_CHECKER(SMBusEEPROMDevice, SMBUS_EEPROM,
- TYPE_SMBUS_EEPROM)
+OBJECT_DECLARE_SIMPLE_TYPE(SMBusEEPROMDevice, SMBUS_EEPROM)
#define SMBUS_EEPROM_SIZE 256
#include "hw/i386/ich9.h"
#include "qom/object.h"
-typedef struct ICH9SMBState ICH9SMBState;
-DECLARE_INSTANCE_CHECKER(ICH9SMBState, ICH9_SMB_DEVICE,
- TYPE_ICH9_SMB_DEVICE)
+OBJECT_DECLARE_SIMPLE_TYPE(ICH9SMBState, ICH9_SMB_DEVICE)
struct ICH9SMBState {
PCIDevice dev;
};
#define TYPE_AMD_IOMMU_DEVICE "amd-iommu"
-typedef struct AMDVIState AMDVIState;
-DECLARE_INSTANCE_CHECKER(AMDVIState, AMD_IOMMU_DEVICE,
- TYPE_AMD_IOMMU_DEVICE)
+OBJECT_DECLARE_SIMPLE_TYPE(AMDVIState, AMD_IOMMU_DEVICE)
#define TYPE_AMD_IOMMU_PCI "AMDVI-PCI"
#include "qom/object.h"
#define TYPE_KVM_CLOCK "kvmclock"
-typedef struct KVMClockState KVMClockState;
-DECLARE_INSTANCE_CHECKER(KVMClockState, KVM_CLOCK,
- TYPE_KVM_CLOCK)
+OBJECT_DECLARE_SIMPLE_TYPE(KVMClockState, KVM_CLOCK)
struct KVMClockState {
/*< private >*/
bool rom_mapped_writable;
VMChangeStateEntry *vmsentry;
};
-typedef struct VAPICROMState VAPICROMState;
#define TYPE_VAPIC "kvmvapic"
-DECLARE_INSTANCE_CHECKER(VAPICROMState, VAPIC,
- TYPE_VAPIC)
+OBJECT_DECLARE_SIMPLE_TYPE(VAPICROMState, VAPIC)
#define TPR_INSTR_ABS_MODRM 0x1
#define TPR_INSTR_MATCH_MODRM_REG 0x2
#include "trace.h"
#include "qom/object.h"
-typedef struct Port92State Port92State;
-DECLARE_INSTANCE_CHECKER(Port92State, PORT92,
- TYPE_PORT92)
+OBJECT_DECLARE_SIMPLE_TYPE(Port92State, PORT92)
struct Port92State {
ISADevice parent_obj;
#endif
#define TYPE_VMMOUSE "vmmouse"
-typedef struct VMMouseState VMMouseState;
-DECLARE_INSTANCE_CHECKER(VMMouseState, VMMOUSE,
- TYPE_VMMOUSE)
+OBJECT_DECLARE_SIMPLE_TYPE(VMMouseState, VMMOUSE)
struct VMMouseState {
ISADevice parent_obj;
#define VCPU_INFO_LEGACY_X2APIC_BIT 3
#define VCPU_INFO_RESERVED_BIT 31
-typedef struct VMPortState VMPortState;
-DECLARE_INSTANCE_CHECKER(VMPortState, VMPORT,
- TYPE_VMPORT)
+OBJECT_DECLARE_SIMPLE_TYPE(VMPortState, VMPORT)
struct VMPortState {
ISADevice parent_obj;
char log_buffer[4096];
int log_buffer_off;
};
-typedef struct PCIXenPlatformState PCIXenPlatformState;
#define TYPE_XEN_PLATFORM "xen-platform"
-DECLARE_INSTANCE_CHECKER(PCIXenPlatformState, XEN_PLATFORM,
- TYPE_XEN_PLATFORM)
+OBJECT_DECLARE_SIMPLE_TYPE(PCIXenPlatformState, XEN_PLATFORM)
#define XEN_PLATFORM_IOPORT 0x10
#define TYPE_XEN_PV_DEVICE "xen-pvdevice"
-typedef struct XenPVDevice XenPVDevice;
-DECLARE_INSTANCE_CHECKER(XenPVDevice, XEN_PV_DEVICE,
- TYPE_XEN_PV_DEVICE)
+OBJECT_DECLARE_SIMPLE_TYPE(XenPVDevice, XEN_PV_DEVICE)
struct XenPVDevice {
/*< private >*/
/* ISA IDE definitions */
#define TYPE_ISA_IDE "isa-ide"
-typedef struct ISAIDEState ISAIDEState;
-DECLARE_INSTANCE_CHECKER(ISAIDEState, ISA_IDE,
- TYPE_ISA_IDE)
+OBJECT_DECLARE_SIMPLE_TYPE(ISAIDEState, ISA_IDE)
struct ISAIDEState {
ISADevice parent_obj;
#include "qom/object.h"
#define TYPE_MICRODRIVE "microdrive"
-typedef struct MicroDriveState MicroDriveState;
-DECLARE_INSTANCE_CHECKER(MicroDriveState, MICRODRIVE,
- TYPE_MICRODRIVE)
+OBJECT_DECLARE_SIMPLE_TYPE(MicroDriveState, MICRODRIVE)
/***********************************************************/
/* CF-ATA Microdrive */
#include "qom/object.h"
#define TYPE_SII3112_PCI "sii3112"
-typedef struct SiI3112PCIState SiI3112PCIState;
-DECLARE_INSTANCE_CHECKER(SiI3112PCIState, SII3112_PCI,
- TYPE_SII3112_PCI)
+OBJECT_DECLARE_SIMPLE_TYPE(SiI3112PCIState, SII3112_PCI)
typedef struct SiI3112Regs {
uint32_t confstat;
#include "trace.h"
#include "qom/object.h"
-typedef struct ADBKeyboardClass ADBKeyboardClass;
-typedef struct KBDState KBDState;
-DECLARE_OBJ_CHECKERS(KBDState, ADBKeyboardClass,
- ADB_KEYBOARD, TYPE_ADB_KEYBOARD)
+OBJECT_DECLARE_TYPE(KBDState, ADBKeyboardClass, ADB_KEYBOARD)
struct KBDState {
/*< private >*/
#include "trace.h"
#include "qom/object.h"
-typedef struct ADBMouseClass ADBMouseClass;
-typedef struct MouseState MouseState;
-DECLARE_OBJ_CHECKERS(MouseState, ADBMouseClass,
- ADB_MOUSE, TYPE_ADB_MOUSE)
+OBJECT_DECLARE_TYPE(MouseState, ADBMouseClass, ADB_MOUSE)
struct MouseState {
/*< public >*/
#include "qom/object.h"
#define TYPE_LM8323 "lm8323"
-typedef struct LM823KbdState LM823KbdState;
-DECLARE_INSTANCE_CHECKER(LM823KbdState, LM8323,
- TYPE_LM8323)
+OBJECT_DECLARE_SIMPLE_TYPE(LM823KbdState, LM8323)
struct LM823KbdState {
I2CSlave parent_obj;
#define COMLOC_KEVT_BASE 0x1143
#define TYPE_MILKYMIST_SOFTUSB "milkymist-softusb"
-typedef struct MilkymistSoftUsbState MilkymistSoftUsbState;
-DECLARE_INSTANCE_CHECKER(MilkymistSoftUsbState, MILKYMIST_SOFTUSB,
- TYPE_MILKYMIST_SOFTUSB)
+OBJECT_DECLARE_SIMPLE_TYPE(MilkymistSoftUsbState, MILKYMIST_SOFTUSB)
struct MilkymistSoftUsbState {
SysBusDevice parent_obj;
#include "qom/object.h"
#define TYPE_PL050 "pl050"
-typedef struct PL050State PL050State;
-DECLARE_INSTANCE_CHECKER(PL050State, PL050,
- TYPE_PL050)
+OBJECT_DECLARE_SIMPLE_TYPE(PL050State, PL050)
struct PL050State {
SysBusDevice parent_obj;
#include "qom/object.h"
#define TYPE_ARM_GICV2M "arm-gicv2m"
-typedef struct ARMGICv2mState ARMGICv2mState;
-DECLARE_INSTANCE_CHECKER(ARMGICv2mState, ARM_GICV2M,
- TYPE_ARM_GICV2M)
+OBJECT_DECLARE_SIMPLE_TYPE(ARMGICv2mState, ARM_GICV2M)
#define GICV2M_NUM_SPI_MAX 128
} CombinerGroupState;
#define TYPE_EXYNOS4210_COMBINER "exynos4210.combiner"
-typedef struct Exynos4210CombinerState Exynos4210CombinerState;
-DECLARE_INSTANCE_CHECKER(Exynos4210CombinerState, EXYNOS4210_COMBINER,
- TYPE_EXYNOS4210_COMBINER)
+OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210CombinerState, EXYNOS4210_COMBINER)
struct Exynos4210CombinerState {
SysBusDevice parent_obj;
/********* GIC part *********/
#define TYPE_EXYNOS4210_GIC "exynos4210.gic"
-typedef struct Exynos4210GicState Exynos4210GicState;
-DECLARE_INSTANCE_CHECKER(Exynos4210GicState, EXYNOS4210_GIC,
- TYPE_EXYNOS4210_GIC)
+OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC)
struct Exynos4210GicState {
SysBusDevice parent_obj;
*/
#define TYPE_EXYNOS4210_IRQ_GATE "exynos4210.irq_gate"
-typedef struct Exynos4210IRQGateState Exynos4210IRQGateState;
-DECLARE_INSTANCE_CHECKER(Exynos4210IRQGateState, EXYNOS4210_IRQ_GATE,
- TYPE_EXYNOS4210_IRQ_GATE)
+OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210IRQGateState, EXYNOS4210_IRQ_GATE)
struct Exynos4210IRQGateState {
SysBusDevice parent_obj;
#define FORCE_OFFSET 0x80
#define EXTENDED_OFFSET 0xC0
-typedef struct IRQMP IRQMP;
-DECLARE_INSTANCE_CHECKER(IRQMP, GRLIB_IRQMP,
- TYPE_GRLIB_IRQMP)
+OBJECT_DECLARE_SIMPLE_TYPE(IRQMP, GRLIB_IRQMP)
typedef struct IRQMPState IRQMPState;
#include "qom/object.h"
#define TYPE_LM32_PIC "lm32-pic"
-typedef struct LM32PicState LM32PicState;
-DECLARE_INSTANCE_CHECKER(LM32PicState, LM32_PIC,
- TYPE_LM32_PIC)
+OBJECT_DECLARE_SIMPLE_TYPE(LM32PicState, LM32_PIC)
struct LM32PicState {
SysBusDevice parent_obj;
#include "qom/object.h"
#define TYPE_ALTERA_IIC "altera,iic"
-typedef struct AlteraIIC AlteraIIC;
-DECLARE_INSTANCE_CHECKER(AlteraIIC, ALTERA_IIC,
- TYPE_ALTERA_IIC)
+OBJECT_DECLARE_SIMPLE_TYPE(AlteraIIC, ALTERA_IIC)
struct AlteraIIC {
SysBusDevice parent_obj;
#include "qom/object.h"
#define TYPE_OR1K_OMPIC "or1k-ompic"
-typedef struct OR1KOMPICState OR1KOMPICState;
-DECLARE_INSTANCE_CHECKER(OR1KOMPICState, OR1K_OMPIC,
- TYPE_OR1K_OMPIC)
+OBJECT_DECLARE_SIMPLE_TYPE(OR1KOMPICState, OR1K_OMPIC)
#define OMPIC_CTRL_IRQ_ACK (1 << 31)
#define OMPIC_CTRL_IRQ_GEN (1 << 30)
#define GCR_RESET 0x80000000
-typedef struct KVMOpenPICState KVMOpenPICState;
-DECLARE_INSTANCE_CHECKER(KVMOpenPICState, KVM_OPENPIC,
- TYPE_KVM_OPENPIC)
+OBJECT_DECLARE_SIMPLE_TYPE(KVMOpenPICState, KVM_OPENPIC)
struct KVMOpenPICState {
/*< private >*/
#define PL190_NUM_PRIO 17
#define TYPE_PL190 "pl190"
-typedef struct PL190State PL190State;
-DECLARE_INSTANCE_CHECKER(PL190State, PL190,
- TYPE_PL190)
+OBJECT_DECLARE_SIMPLE_TYPE(PL190State, PL190)
struct PL190State {
SysBusDevice parent_obj;
#include "qemu/log.h"
#define TYPE_PUV3_INTC "puv3_intc"
-typedef struct PUV3INTCState PUV3INTCState;
-DECLARE_INSTANCE_CHECKER(PUV3INTCState, PUV3_INTC,
- TYPE_PUV3_INTC)
+OBJECT_DECLARE_SIMPLE_TYPE(PUV3INTCState, PUV3_INTC)
struct PUV3INTCState {
SysBusDevice parent_obj;
#define HW_SIFIVE_PLIC_H
#include "hw/sysbus.h"
+#include "qom/object.h"
#define TYPE_SIFIVE_PLIC "riscv.sifive.plic"
-#define SIFIVE_PLIC(obj) \
- OBJECT_CHECK(SiFivePLICState, (obj), TYPE_SIFIVE_PLIC)
+typedef struct SiFivePLICState SiFivePLICState;
+DECLARE_INSTANCE_CHECKER(SiFivePLICState, SIFIVE_PLIC,
+ TYPE_SIFIVE_PLIC)
typedef enum PLICMode {
PLICMode_U,
PLICMode mode;
} PLICAddr;
-typedef struct SiFivePLICState {
+struct SiFivePLICState {
/*< private >*/
SysBusDevice parent_obj;
uint32_t context_base;
uint32_t context_stride;
uint32_t aperture_size;
-} SiFivePLICState;
+};
DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
uint32_t hartid_base, uint32_t num_sources,
} SLAVIO_CPUINTCTLState;
#define TYPE_SLAVIO_INTCTL "slavio_intctl"
-typedef struct SLAVIO_INTCTLState SLAVIO_INTCTLState;
-DECLARE_INSTANCE_CHECKER(SLAVIO_INTCTLState, SLAVIO_INTCTL,
- TYPE_SLAVIO_INTCTL)
+OBJECT_DECLARE_SIMPLE_TYPE(SLAVIO_INTCTLState, SLAVIO_INTCTL)
struct SLAVIO_INTCTLState {
SysBusDevice parent_obj;
uint16_t status;
uint8_t int_set;
};
-typedef struct TPCI200State TPCI200State;
#define TYPE_TPCI200 "tpci200"
-DECLARE_INSTANCE_CHECKER(TPCI200State, TPCI200,
- TYPE_TPCI200)
+OBJECT_DECLARE_SIMPLE_TYPE(TPCI200State, TPCI200)
static const uint8_t local_config_regs[] = {
0x00, 0xFF, 0xFF, 0x0F, 0x00, 0xFC, 0xFF, 0x0F, 0x00, 0x00, 0x00,
#define VM_CMD_GRACEFUL_SHUTDOWN 0x09
#define TYPE_IPMI_BMC_EXTERN "ipmi-bmc-extern"
-typedef struct IPMIBmcExtern IPMIBmcExtern;
-DECLARE_INSTANCE_CHECKER(IPMIBmcExtern, IPMI_BMC_EXTERN,
- TYPE_IPMI_BMC_EXTERN)
+OBJECT_DECLARE_SIMPLE_TYPE(IPMIBmcExtern, IPMI_BMC_EXTERN)
struct IPMIBmcExtern {
IPMIBmc parent;
#include "qom/object.h"
#define TYPE_ISA_IPMI_BT "isa-ipmi-bt"
-typedef struct ISAIPMIBTDevice ISAIPMIBTDevice;
-DECLARE_INSTANCE_CHECKER(ISAIPMIBTDevice, ISA_IPMI_BT,
- TYPE_ISA_IPMI_BT)
+OBJECT_DECLARE_SIMPLE_TYPE(ISAIPMIBTDevice, ISA_IPMI_BT)
struct ISAIPMIBTDevice {
ISADevice dev;
#include "qom/object.h"
#define TYPE_ISA_IPMI_KCS "isa-ipmi-kcs"
-typedef struct ISAIPMIKCSDevice ISAIPMIKCSDevice;
-DECLARE_INSTANCE_CHECKER(ISAIPMIKCSDevice, ISA_IPMI_KCS,
- TYPE_ISA_IPMI_KCS)
+OBJECT_DECLARE_SIMPLE_TYPE(ISAIPMIKCSDevice, ISA_IPMI_KCS)
struct ISAIPMIKCSDevice {
ISADevice dev;
#include "qom/object.h"
#define TYPE_PCI_IPMI_BT "pci-ipmi-bt"
-typedef struct PCIIPMIBTDevice PCIIPMIBTDevice;
-DECLARE_INSTANCE_CHECKER(PCIIPMIBTDevice, PCI_IPMI_BT,
- TYPE_PCI_IPMI_BT)
+OBJECT_DECLARE_SIMPLE_TYPE(PCIIPMIBTDevice, PCI_IPMI_BT)
struct PCIIPMIBTDevice {
PCIDevice dev;
#include "qom/object.h"
#define TYPE_PCI_IPMI_KCS "pci-ipmi-kcs"
-typedef struct PCIIPMIKCSDevice PCIIPMIKCSDevice;
-DECLARE_INSTANCE_CHECKER(PCIIPMIKCSDevice, PCI_IPMI_KCS,
- TYPE_PCI_IPMI_KCS)
+OBJECT_DECLARE_SIMPLE_TYPE(PCIIPMIKCSDevice, PCI_IPMI_KCS)
struct PCIIPMIKCSDevice {
PCIDevice dev;
#include "qom/object.h"
#define TYPE_SMBUS_IPMI "smbus-ipmi"
-typedef struct SMBusIPMIDevice SMBusIPMIDevice;
-DECLARE_INSTANCE_CHECKER(SMBusIPMIDevice, SMBUS_IPMI,
- TYPE_SMBUS_IPMI)
+OBJECT_DECLARE_SIMPLE_TYPE(SMBusIPMIDevice, SMBUS_IPMI)
#define SSIF_IPMI_REQUEST 2
#define SSIF_IPMI_MULTI_PART_REQUEST_START 6
#include "qom/object.h"
#define TYPE_I82378 "i82378"
-typedef struct I82378State I82378State;
-DECLARE_INSTANCE_CHECKER(I82378State, I82378,
- TYPE_I82378)
+OBJECT_DECLARE_SIMPLE_TYPE(I82378State, I82378)
struct I82378State {
PCIDevice parent_obj;
MemoryRegion rcr_mem;
uint8_t rcr;
};
-typedef struct PIIX4State PIIX4State;
-DECLARE_INSTANCE_CHECKER(PIIX4State, PIIX4_PCI_DEVICE,
- TYPE_PIIX4_PCI_DEVICE)
+OBJECT_DECLARE_SIMPLE_TYPE(PIIX4State, PIIX4_PCI_DEVICE)
static void piix4_isa_reset(DeviceState *dev)
{
MemoryRegion superio;
SuperIOConfig superio_conf;
};
-typedef struct VT82C686BState VT82C686BState;
#define TYPE_VT82C686B_DEVICE "VT82C686B"
-DECLARE_INSTANCE_CHECKER(VT82C686BState, VT82C686B_DEVICE,
- TYPE_VT82C686B_DEVICE)
+OBJECT_DECLARE_SIMPLE_TYPE(VT82C686BState, VT82C686B_DEVICE)
static void superio_ioport_writeb(void *opaque, hwaddr addr, uint64_t data,
unsigned size)
PMSMBus smb;
uint32_t smb_io_base;
};
-typedef struct VT686PMState VT686PMState;
struct VT686AC97State {
PCIDevice dev;
};
-typedef struct VT686AC97State VT686AC97State;
struct VT686MC97State {
PCIDevice dev;
};
-typedef struct VT686MC97State VT686MC97State;
#define TYPE_VT82C686B_PM_DEVICE "VT82C686B_PM"
-DECLARE_INSTANCE_CHECKER(VT686PMState, VT82C686B_PM_DEVICE,
- TYPE_VT82C686B_PM_DEVICE)
+OBJECT_DECLARE_SIMPLE_TYPE(VT686PMState, VT82C686B_PM_DEVICE)
#define TYPE_VT82C686B_MC97_DEVICE "VT82C686B_MC97"
-DECLARE_INSTANCE_CHECKER(VT686MC97State, VT82C686B_MC97_DEVICE,
- TYPE_VT82C686B_MC97_DEVICE)
+OBJECT_DECLARE_SIMPLE_TYPE(VT686MC97State, VT82C686B_MC97_DEVICE)
#define TYPE_VT82C686B_AC97_DEVICE "VT82C686B_AC97"
-DECLARE_INSTANCE_CHECKER(VT686AC97State, VT82C686B_AC97_DEVICE,
- TYPE_VT82C686B_AC97_DEVICE)
+OBJECT_DECLARE_SIMPLE_TYPE(VT686AC97State, VT82C686B_AC97_DEVICE)
static void pm_update_sci(VT686PMState *s)
{
#include "qom/object.h"
#define TYPE_MCF_INTC "mcf-intc"
-typedef struct mcf_intc_state mcf_intc_state;
-DECLARE_INSTANCE_CHECKER(mcf_intc_state, MCF_INTC,
- TYPE_MCF_INTC)
+OBJECT_DECLARE_SIMPLE_TYPE(mcf_intc_state, MCF_INTC)
struct mcf_intc_state {
SysBusDevice parent_obj;
#endif
#define TYPE_NEXT_MACHINE MACHINE_TYPE_NAME("next-cube")
-typedef struct NeXTState NeXTState;
-DECLARE_INSTANCE_CHECKER(NeXTState, NEXT_MACHINE,
- TYPE_NEXT_MACHINE)
+OBJECT_DECLARE_SIMPLE_TYPE(NeXTState, NEXT_MACHINE)
#define ENTRY 0x0100001e
#define RAM_SIZE 0x4000000
#include "migration/vmstate.h"
#include "qom/object.h"
-typedef struct NextKBDState NextKBDState;
-DECLARE_INSTANCE_CHECKER(NextKBDState, NEXTKBD,
- TYPE_NEXTKBD)
+OBJECT_DECLARE_SIMPLE_TYPE(NextKBDState, NEXTKBD)
/* following defintions from next68k netbsd */
#define CSR_INT 0x00800000
/* Define the PMU device */
#define TYPE_XLNX_ZYNQMP_PMU_SOC "xlnx,zynqmp-pmu-soc"
-typedef struct XlnxZynqMPPMUSoCState XlnxZynqMPPMUSoCState;
-DECLARE_INSTANCE_CHECKER(XlnxZynqMPPMUSoCState, XLNX_ZYNQMP_PMU_SOC,
- TYPE_XLNX_ZYNQMP_PMU_SOC)
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPPMUSoCState, XLNX_ZYNQMP_PMU_SOC)
#define XLNX_ZYNQMP_PMU_ROM_SIZE 0x8000
#define XLNX_ZYNQMP_PMU_ROM_ADDR 0xFFD00000
#define TYPE_GT64120_PCI_HOST_BRIDGE "gt64120"
-typedef struct GT64120State GT64120State;
-DECLARE_INSTANCE_CHECKER(GT64120State, GT64120_PCI_HOST_BRIDGE,
- TYPE_GT64120_PCI_HOST_BRIDGE)
+OBJECT_DECLARE_SIMPLE_TYPE(GT64120State, GT64120_PCI_HOST_BRIDGE)
struct GT64120State {
PCIHostState parent_obj;
} MaltaFPGAState;
#define TYPE_MIPS_MALTA "mips-malta"
-typedef struct MaltaState MaltaState;
-DECLARE_INSTANCE_CHECKER(MaltaState, MIPS_MALTA,
- TYPE_MIPS_MALTA)
+OBJECT_DECLARE_SIMPLE_TYPE(MaltaState, MIPS_MALTA)
struct MaltaState {
SysBusDevice parent_obj;
QLIST_ENTRY(AppleSMCData) node;
};
-typedef struct AppleSMCState AppleSMCState;
-DECLARE_INSTANCE_CHECKER(AppleSMCState, APPLE_SMC,
- TYPE_APPLE_SMC)
+OBJECT_DECLARE_SIMPLE_TYPE(AppleSMCState, APPLE_SMC)
struct AppleSMCState {
ISADevice parent_obj;
#include "qemu/module.h"
#include "qom/object.h"
-typedef struct IntegratorDebugState IntegratorDebugState;
-DECLARE_INSTANCE_CHECKER(IntegratorDebugState, INTEGRATOR_DEBUG,
- TYPE_INTEGRATOR_DEBUG)
+OBJECT_DECLARE_SIMPLE_TYPE(IntegratorDebugState, INTEGRATOR_DEBUG)
struct IntegratorDebugState {
SysBusDevice parent_obj;
#define CACHE_ID 0x410000c8
#define TYPE_ARM_L2X0 "l2x0"
-typedef struct L2x0State L2x0State;
-DECLARE_INSTANCE_CHECKER(L2x0State, ARM_L2X0,
- TYPE_ARM_L2X0)
+OBJECT_DECLARE_SIMPLE_TYPE(L2x0State, ARM_L2X0)
struct L2x0State {
SysBusDevice parent_obj;
#define LOCK_VALUE 0xa05f
#define TYPE_ARM_SYSCTL "realview_sysctl"
-typedef struct arm_sysctl_state arm_sysctl_state;
-DECLARE_INSTANCE_CHECKER(arm_sysctl_state, ARM_SYSCTL,
- TYPE_ARM_SYSCTL)
+OBJECT_DECLARE_SIMPLE_TYPE(arm_sysctl_state, ARM_SYSCTL)
struct arm_sysctl_state {
SysBusDevice parent_obj;
#include "qom/object.h"
#define TYPE_ISA_DEBUG_EXIT_DEVICE "isa-debug-exit"
-typedef struct ISADebugExitState ISADebugExitState;
-DECLARE_INSTANCE_CHECKER(ISADebugExitState, ISA_DEBUG_EXIT_DEVICE,
- TYPE_ISA_DEBUG_EXIT_DEVICE)
+OBJECT_DECLARE_SIMPLE_TYPE(ISADebugExitState, ISA_DEBUG_EXIT_DEVICE)
struct ISADebugExitState {
ISADevice parent_obj;
#define ECC_DIAG_MASK (ECC_DIAG_SIZE - 1)
#define TYPE_ECC_MEMCTL "eccmemctl"
-typedef struct ECCState ECCState;
-DECLARE_INSTANCE_CHECKER(ECCState, ECC_MEMCTL,
- TYPE_ECC_MEMCTL)
+OBJECT_DECLARE_SIMPLE_TYPE(ECCState, ECC_MEMCTL)
struct ECCState {
SysBusDevice parent_obj;
#include "qom/object.h"
#define TYPE_EMPTY_SLOT "empty_slot"
-typedef struct EmptySlot EmptySlot;
-DECLARE_INSTANCE_CHECKER(EmptySlot, EMPTY_SLOT,
- TYPE_EMPTY_SLOT)
+OBJECT_DECLARE_SIMPLE_TYPE(EmptySlot, EMPTY_SLOT)
struct EmptySlot {
SysBusDevice parent_obj;
#include "qom/object.h"
#define TYPE_EXYNOS4210_CLK "exynos4210.clk"
-typedef struct Exynos4210ClkState Exynos4210ClkState;
-DECLARE_INSTANCE_CHECKER(Exynos4210ClkState, EXYNOS4210_CLK,
- TYPE_EXYNOS4210_CLK)
+OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210ClkState, EXYNOS4210_CLK)
#define CLK_PLL_LOCKED BIT(29)
#define PMU_NUM_OF_REGISTERS ARRAY_SIZE(exynos4210_pmu_regs)
#define TYPE_EXYNOS4210_PMU "exynos4210.pmu"
-typedef struct Exynos4210PmuState Exynos4210PmuState;
-DECLARE_INSTANCE_CHECKER(Exynos4210PmuState, EXYNOS4210_PMU,
- TYPE_EXYNOS4210_PMU)
+OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210PmuState, EXYNOS4210_PMU)
struct Exynos4210PmuState {
SysBusDevice parent_obj;
} while (0)
#define TYPE_EXYNOS4210_RNG "exynos4210.rng"
-typedef struct Exynos4210RngState Exynos4210RngState;
-DECLARE_INSTANCE_CHECKER(Exynos4210RngState, EXYNOS4210_RNG,
- TYPE_EXYNOS4210_RNG)
+OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210RngState, EXYNOS4210_RNG)
/*
* Exynos4220, PRNG, only polling mode is supported.
};
#define TYPE_MILKYMIST_HPDMC "milkymist-hpdmc"
-typedef struct MilkymistHpdmcState MilkymistHpdmcState;
-DECLARE_INSTANCE_CHECKER(MilkymistHpdmcState, MILKYMIST_HPDMC,
- TYPE_MILKYMIST_HPDMC)
+OBJECT_DECLARE_SIMPLE_TYPE(MilkymistHpdmcState, MILKYMIST_HPDMC)
struct MilkymistHpdmcState {
SysBusDevice parent_obj;
#endif
#define TYPE_MILKYMIST_PFPU "milkymist-pfpu"
-typedef struct MilkymistPFPUState MilkymistPFPUState;
-DECLARE_INSTANCE_CHECKER(MilkymistPFPUState, MILKYMIST_PFPU,
- TYPE_MILKYMIST_PFPU)
+OBJECT_DECLARE_SIMPLE_TYPE(MilkymistPFPUState, MILKYMIST_PFPU)
struct MilkymistPFPUState {
SysBusDevice parent_obj;
#define MST_PCMCIA_CD1_IRQ 13
#define TYPE_MAINSTONE_FPGA "mainstone-fpga"
-typedef struct mst_irq_state mst_irq_state;
-DECLARE_INSTANCE_CHECKER(mst_irq_state, MAINSTONE_FPGA,
- TYPE_MAINSTONE_FPGA)
+OBJECT_DECLARE_SIMPLE_TYPE(mst_irq_state, MAINSTONE_FPGA)
struct mst_irq_state {
SysBusDevice parent_obj;
uint32_t ioport_data;
char iomem_buf[IOMEM_LEN];
};
-typedef struct PCTestdev PCTestdev;
#define TYPE_TESTDEV "pc-testdev"
-DECLARE_INSTANCE_CHECKER(PCTestdev, TESTDEV,
- TYPE_TESTDEV)
+OBJECT_DECLARE_SIMPLE_TYPE(PCTestdev, TESTDEV)
static uint64_t test_irq_line_read(void *opaque, hwaddr addr, unsigned size)
{
uint64_t membar_size;
MemoryRegion membar;
};
-typedef struct PCITestDevState PCITestDevState;
#define TYPE_PCI_TEST_DEV "pci-testdev"
-DECLARE_INSTANCE_CHECKER(PCITestDevState, PCI_TEST_DEV,
- TYPE_PCI_TEST_DEV)
+OBJECT_DECLARE_SIMPLE_TYPE(PCITestDevState, PCI_TEST_DEV)
#define IOTEST_IS_MEM(i) (strcmp(IOTEST_TYPE(i), "portio"))
#define IOTEST_REGION(d, i) (IOTEST_IS_MEM(i) ? &(d)->mmio : &(d)->portio)
#include "qemu/log.h"
#define TYPE_PUV3_PM "puv3_pm"
-typedef struct PUV3PMState PUV3PMState;
-DECLARE_INSTANCE_CHECKER(PUV3PMState, PUV3_PM,
- TYPE_PUV3_PM)
+OBJECT_DECLARE_SIMPLE_TYPE(PUV3PMState, PUV3_PM)
struct PUV3PMState {
SysBusDevice parent_obj;
#define SGABIOS_FILENAME "sgabios.bin"
#define TYPE_SGA "sga"
-typedef struct ISASGAState ISASGAState;
-DECLARE_INSTANCE_CHECKER(ISASGAState, SGA,
- TYPE_SGA)
+OBJECT_DECLARE_SIMPLE_TYPE(ISASGAState, SGA)
struct ISASGAState {
ISADevice parent_obj;
*/
#define TYPE_SLAVIO_MISC "slavio_misc"
-typedef struct MiscState MiscState;
-DECLARE_INSTANCE_CHECKER(MiscState, SLAVIO_MISC,
- TYPE_SLAVIO_MISC)
+OBJECT_DECLARE_SIMPLE_TYPE(MiscState, SLAVIO_MISC)
struct MiscState {
SysBusDevice parent_obj;
#include "qom/object.h"
#define TYPE_TMP105 "tmp105"
-typedef struct TMP105State TMP105State;
-DECLARE_INSTANCE_CHECKER(TMP105State, TMP105,
- TYPE_TMP105)
+OBJECT_DECLARE_SIMPLE_TYPE(TMP105State, TMP105)
/**
* TMP105State:
uint8_t pointer;
};
-typedef struct TMP421State TMP421State;
struct TMP421Class {
I2CSlaveClass parent_class;
DeviceInfo *dev;
};
-typedef struct TMP421Class TMP421Class;
#define TYPE_TMP421 "tmp421-generic"
-DECLARE_OBJ_CHECKERS(TMP421State, TMP421Class,
- TMP421, TYPE_TMP421)
+OBJECT_DECLARE_TYPE(TMP421State, TMP421Class, TMP421)
/* the TMP421 registers */
#define ZYNQ_SLCR_NUM_REGS (ZYNQ_SLCR_MMIO_SIZE / 4)
#define TYPE_ZYNQ_SLCR "xilinx,zynq_slcr"
-typedef struct ZynqSLCRState ZynqSLCRState;
-DECLARE_INSTANCE_CHECKER(ZynqSLCRState, ZYNQ_SLCR,
- TYPE_ZYNQ_SLCR)
+OBJECT_DECLARE_SIMPLE_TYPE(ZynqSLCRState, ZYNQ_SLCR)
struct ZynqSLCRState {
SysBusDevice parent_obj;
#define SONIC_DESC_ADDR 0xFFFE
#define TYPE_DP8393X "dp8393x"
-typedef struct dp8393xState dp8393xState;
-DECLARE_INSTANCE_CHECKER(dp8393xState, DP8393X,
- TYPE_DP8393X)
+OBJECT_DECLARE_SIMPLE_TYPE(dp8393xState, DP8393X)
struct dp8393xState {
SysBusDevice parent_obj;
#include "qom/object.h"
#define TYPE_E1000E "e1000e"
-typedef struct E1000EState E1000EState;
-DECLARE_INSTANCE_CHECKER(E1000EState, E1000E,
- TYPE_E1000E)
+OBJECT_DECLARE_SIMPLE_TYPE(E1000EState, E1000E)
struct E1000EState {
PCIDevice parent_obj;
#define FS_ETH_MAX_REGS 0x17
#define TYPE_ETRAX_FS_ETH "etraxfs-eth"
-typedef struct ETRAXFSEthState ETRAXFSEthState;
-DECLARE_INSTANCE_CHECKER(ETRAXFSEthState, ETRAX_FS_ETH,
- TYPE_ETRAX_FS_ETH)
+OBJECT_DECLARE_SIMPLE_TYPE(ETRAXFSEthState, ETRAX_FS_ETH)
struct ETRAXFSEthState {
SysBusDevice parent_obj;
typedef struct eTSEC eTSEC;
#define TYPE_ETSEC_COMMON "eTSEC"
-DECLARE_INSTANCE_CHECKER(eTSEC, ETSEC_COMMON,
- TYPE_ETSEC_COMMON)
+OBJECT_DECLARE_SIMPLE_TYPE(eTSEC, ETSEC_COMMON)
#define eTSEC_TRANSMIT 1
#define eTSEC_RECEIVE 2
}
};
-typedef struct lan9118_state lan9118_state;
-DECLARE_INSTANCE_CHECKER(lan9118_state, LAN9118,
- TYPE_LAN9118)
+OBJECT_DECLARE_SIMPLE_TYPE(lan9118_state, LAN9118)
struct lan9118_state {
SysBusDevice parent_obj;
typedef struct MilkymistMinimac2MdioState MilkymistMinimac2MdioState;
#define TYPE_MILKYMIST_MINIMAC2 "milkymist-minimac2"
-typedef struct MilkymistMinimac2State MilkymistMinimac2State;
-DECLARE_INSTANCE_CHECKER(MilkymistMinimac2State, MILKYMIST_MINIMAC2,
- TYPE_MILKYMIST_MINIMAC2)
+OBJECT_DECLARE_SIMPLE_TYPE(MilkymistMinimac2State, MILKYMIST_MINIMAC2)
struct MilkymistMinimac2State {
SysBusDevice parent_obj;
#define MAX_ETH_FRAME_SIZE 1514
#define TYPE_MIPS_NET "mipsnet"
-typedef struct MIPSnetState MIPSnetState;
-DECLARE_INSTANCE_CHECKER(MIPSnetState, MIPS_NET,
- TYPE_MIPS_NET)
+OBJECT_DECLARE_SIMPLE_TYPE(MIPSnetState, MIPS_NET)
struct MIPSnetState {
SysBusDevice parent_obj;
#include "qemu/module.h"
#include "qom/object.h"
-typedef struct ISANE2000State ISANE2000State;
-DECLARE_INSTANCE_CHECKER(ISANE2000State, ISA_NE2000,
- TYPE_ISA_NE2000)
+OBJECT_DECLARE_SIMPLE_TYPE(ISANE2000State, ISA_NE2000)
struct ISANE2000State {
ISADevice parent_obj;
#define DEFAULT_PHY 1
#define TYPE_OPEN_ETH "open_eth"
-typedef struct OpenEthState OpenEthState;
-DECLARE_INSTANCE_CHECKER(OpenEthState, OPEN_ETH,
- TYPE_OPEN_ETH)
+OBJECT_DECLARE_SIMPLE_TYPE(OpenEthState, OPEN_ETH)
struct OpenEthState {
SysBusDevice parent_obj;
#define TYPE_PCI_PCNET "pcnet"
-typedef struct PCIPCNetState PCIPCNetState;
-DECLARE_INSTANCE_CHECKER(PCIPCNetState, PCI_PCNET,
- TYPE_PCI_PCNET)
+OBJECT_DECLARE_SIMPLE_TYPE(PCIPCNetState, PCI_PCNET)
struct PCIPCNetState {
/*< private >*/
#define TYPE_RTL8139 "rtl8139"
-typedef struct RTL8139State RTL8139State;
-DECLARE_INSTANCE_CHECKER(RTL8139State, RTL8139,
- TYPE_RTL8139)
+OBJECT_DECLARE_SIMPLE_TYPE(RTL8139State, RTL8139)
/* Symbolic offsets to registers. */
enum RTL8139_registers {
#define NUM_PACKETS 4
#define TYPE_SMC91C111 "smc91c111"
-typedef struct smc91c111_state smc91c111_state;
-DECLARE_INSTANCE_CHECKER(smc91c111_state, SMC91C111,
- TYPE_SMC91C111)
+OBJECT_DECLARE_SIMPLE_TYPE(smc91c111_state, SMC91C111)
struct smc91c111_state {
SysBusDevice parent_obj;
#define VLAN_MAX_BUFS (VLAN_RX_BDS_LEN / 8)
#define TYPE_VIO_SPAPR_VLAN_DEVICE "spapr-vlan"
-typedef struct SpaprVioVlan SpaprVioVlan;
-DECLARE_INSTANCE_CHECKER(SpaprVioVlan, VIO_SPAPR_VLAN_DEVICE,
- TYPE_VIO_SPAPR_VLAN_DEVICE)
+OBJECT_DECLARE_SIMPLE_TYPE(SpaprVioVlan, VIO_SPAPR_VLAN_DEVICE)
#define RX_POOL_MAX_BDS 4096
#define RX_MAX_POOLS 5
#define SE_TCTL_DUPLEX 0x08
#define TYPE_STELLARIS_ENET "stellaris_enet"
-typedef struct stellaris_enet_state stellaris_enet_state;
-DECLARE_INSTANCE_CHECKER(stellaris_enet_state, STELLARIS_ENET,
- TYPE_STELLARIS_ENET)
+OBJECT_DECLARE_SIMPLE_TYPE(stellaris_enet_state, STELLARIS_ENET)
typedef struct {
uint8_t data[2048];
#define TYPE_SUNGEM "sungem"
-typedef struct SunGEMState SunGEMState;
-DECLARE_INSTANCE_CHECKER(SunGEMState, SUNGEM,
- TYPE_SUNGEM)
+OBJECT_DECLARE_SIMPLE_TYPE(SunGEMState, SUNGEM)
#define MAX_PACKET_SIZE 9016
#define MII_COMMAND_WRITE 0x1
#define TYPE_SUNHME "sunhme"
-typedef struct SunHMEState SunHMEState;
-DECLARE_INSTANCE_CHECKER(SunHMEState, SUNHME,
- TYPE_SUNHME)
+OBJECT_DECLARE_SIMPLE_TYPE(SunHMEState, SUNHME)
/* Maximum size of buffer */
#define HME_FIFO_SIZE 0x800
#include "qom/object.h"
#define TYPE_TULIP "tulip"
-typedef struct TULIPState TULIPState;
-DECLARE_INSTANCE_CHECKER(TULIPState, TULIP,
- TYPE_TULIP)
+OBJECT_DECLARE_SIMPLE_TYPE(TULIPState, TULIP)
#define CSR(_x) ((_x) << 3)
} RxTxStats;
#define TYPE_XGMAC "xgmac"
-typedef struct XgmacState XgmacState;
-DECLARE_INSTANCE_CHECKER(XgmacState, XGMAC,
- TYPE_XGMAC)
+OBJECT_DECLARE_SIMPLE_TYPE(XgmacState, XGMAC)
struct XgmacState {
SysBusDevice parent_obj;
#define TYPE_XILINX_AXI_ENET_DATA_STREAM "xilinx-axienet-data-stream"
#define TYPE_XILINX_AXI_ENET_CONTROL_STREAM "xilinx-axienet-control-stream"
-typedef struct XilinxAXIEnet XilinxAXIEnet;
-DECLARE_INSTANCE_CHECKER(XilinxAXIEnet, XILINX_AXI_ENET,
- TYPE_XILINX_AXI_ENET)
+OBJECT_DECLARE_SIMPLE_TYPE(XilinxAXIEnet, XILINX_AXI_ENET)
typedef struct XilinxAXIEnetStreamSlave XilinxAXIEnetStreamSlave;
DECLARE_INSTANCE_CHECKER(XilinxAXIEnetStreamSlave, XILINX_AXI_ENET_DATA_STREAM,
};
#define TYPE_DS1225Y "ds1225y"
-typedef struct SysBusNvRamState SysBusNvRamState;
-DECLARE_INSTANCE_CHECKER(SysBusNvRamState, DS1225Y,
- TYPE_DS1225Y)
+OBJECT_DECLARE_SIMPLE_TYPE(SysBusNvRamState, DS1225Y)
struct SysBusNvRamState {
SysBusDevice parent_obj;
BlockBackend *blk;
VMChangeStateEntry *vmstate;
};
-typedef struct SpaprNvram SpaprNvram;
#define TYPE_VIO_SPAPR_NVRAM "spapr-nvram"
-DECLARE_INSTANCE_CHECKER(SpaprNvram, VIO_SPAPR_NVRAM,
- TYPE_VIO_SPAPR_NVRAM)
+OBJECT_DECLARE_SIMPLE_TYPE(SpaprNvram, VIO_SPAPR_NVRAM)
#define MIN_NVRAM_SIZE (8 * KiB)
#define DEFAULT_NVRAM_SIZE (64 * KiB)
#include "hw/pci/pci_bus.h"
#include "qom/object.h"
-typedef struct DECState DECState;
-DECLARE_INSTANCE_CHECKER(DECState, DEC_21154,
- TYPE_DEC_21154)
+OBJECT_DECLARE_SIMPLE_TYPE(DECState, DEC_21154)
struct DECState {
PCIHostState parent_obj;
#include "qom/object.h"
#define TYPE_GEN_PCIE_ROOT_PORT "pcie-root-port"
-typedef struct GenPCIERootPort GenPCIERootPort;
-DECLARE_INSTANCE_CHECKER(GenPCIERootPort, GEN_PCIE_ROOT_PORT,
- TYPE_GEN_PCIE_ROOT_PORT)
+OBJECT_DECLARE_SIMPLE_TYPE(GenPCIERootPort, GEN_PCIE_ROOT_PORT)
#define GEN_PCIE_ROOT_PORT_AER_OFFSET 0x100
#define GEN_PCIE_ROOT_PORT_ACS_OFFSET \
#define TYPE_PCI_BRIDGE_DEV "pci-bridge"
#define TYPE_PCI_BRIDGE_SEAT_DEV "pci-bridge-seat"
-typedef struct PCIBridgeDev PCIBridgeDev;
-DECLARE_INSTANCE_CHECKER(PCIBridgeDev, PCI_BRIDGE_DEV,
- TYPE_PCI_BRIDGE_DEV)
+OBJECT_DECLARE_SIMPLE_TYPE(PCIBridgeDev, PCI_BRIDGE_DEV)
struct PCIBridgeDev {
/*< private >*/
MemoryRegion shpc_bar;
/*< public >*/
};
-typedef struct PCIEPCIBridge PCIEPCIBridge;
#define TYPE_PCIE_PCI_BRIDGE_DEV "pcie-pci-bridge"
-DECLARE_INSTANCE_CHECKER(PCIEPCIBridge, PCIE_PCI_BRIDGE_DEV,
- TYPE_PCIE_PCI_BRIDGE_DEV)
+OBJECT_DECLARE_SIMPLE_TYPE(PCIEPCIBridge, PCIE_PCI_BRIDGE_DEV)
static void pcie_pci_bridge_realize(PCIDevice *d, Error **errp)
{
};
#define TYPE_BONITO_PCI_HOST_BRIDGE "Bonito-pcihost"
-DECLARE_INSTANCE_CHECKER(BonitoState, BONITO_PCI_HOST_BRIDGE,
- TYPE_BONITO_PCI_HOST_BRIDGE)
+OBJECT_DECLARE_SIMPLE_TYPE(BonitoState, BONITO_PCI_HOST_BRIDGE)
#define TYPE_PCI_BONITO "Bonito"
-DECLARE_INSTANCE_CHECKER(PCIBonitoState, PCI_BONITO,
- TYPE_PCI_BONITO)
+OBJECT_DECLARE_SIMPLE_TYPE(PCIBonitoState, PCI_BONITO)
static void bonito_writel(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
#include "trace.h"
#include "qom/object.h"
-typedef struct GrackleState GrackleState;
-DECLARE_INSTANCE_CHECKER(GrackleState, GRACKLE_PCI_HOST_BRIDGE,
- TYPE_GRACKLE_PCI_HOST_BRIDGE)
+OBJECT_DECLARE_SIMPLE_TYPE(GrackleState, GRACKLE_PCI_HOST_BRIDGE)
struct GrackleState {
PCIHostState parent_obj;
* https://wiki.qemu.org/File:29054901.pdf
*/
-typedef struct I440FXState I440FXState;
-DECLARE_INSTANCE_CHECKER(I440FXState, I440FX_PCI_HOST_BRIDGE,
- TYPE_I440FX_PCI_HOST_BRIDGE)
+OBJECT_DECLARE_SIMPLE_TYPE(I440FXState, I440FX_PCI_HOST_BRIDGE)
struct I440FXState {
PCIHostState parent_obj;
#define TYPE_PPC_E500_PCI_HOST_BRIDGE "e500-pcihost"
-typedef struct PPCE500PCIState PPCE500PCIState;
-DECLARE_INSTANCE_CHECKER(PPCE500PCIState, PPC_E500_PCI_HOST_BRIDGE,
- TYPE_PPC_E500_PCI_HOST_BRIDGE)
+OBJECT_DECLARE_SIMPLE_TYPE(PPCE500PCIState, PPC_E500_PCI_HOST_BRIDGE)
struct PPCE500PCIState {
PCIHostState parent_obj;
};
#define TYPE_PPC_E500_PCI_BRIDGE "e500-host-bridge"
-typedef struct PPCE500PCIBridgeState PPCE500PCIBridgeState;
-DECLARE_INSTANCE_CHECKER(PPCE500PCIBridgeState, PPC_E500_PCI_BRIDGE,
- TYPE_PPC_E500_PCI_BRIDGE)
+OBJECT_DECLARE_SIMPLE_TYPE(PPCE500PCIBridgeState, PPC_E500_PCI_BRIDGE)
struct PPCE500PCIBridgeState {
/*< private >*/
#define TYPE_RAVEN_PCI_DEVICE "raven"
#define TYPE_RAVEN_PCI_HOST_BRIDGE "raven-pcihost"
-typedef struct RavenPCIState RavenPCIState;
-DECLARE_INSTANCE_CHECKER(RavenPCIState, RAVEN_PCI_DEVICE,
- TYPE_RAVEN_PCI_DEVICE)
+OBJECT_DECLARE_SIMPLE_TYPE(RavenPCIState, RAVEN_PCI_DEVICE)
struct RavenPCIState {
PCIDevice dev;
MemoryRegion ccsr_space;
};
-typedef struct PPCE500CCSRState PPCE500CCSRState;
#define TYPE_CCSR "e500-ccsr"
-DECLARE_INSTANCE_CHECKER(PPCE500CCSRState, CCSR,
- TYPE_CCSR)
+OBJECT_DECLARE_SIMPLE_TYPE(PPCE500CCSRState, CCSR)
#endif /* E500_CCSR_H */
*/
PlatformBusDevice *pbus_dev;
};
-typedef struct PPCE500MachineState PPCE500MachineState;
struct PPCE500MachineClass {
/*< private >*/
hwaddr pci_mmio_bus_base;
hwaddr spin_base;
};
-typedef struct PPCE500MachineClass PPCE500MachineClass;
void ppce500_init(MachineState *machine);
hwaddr booke206_page_size_to_tlb(uint64_t size);
#define TYPE_PPCE500_MACHINE "ppce500-base-machine"
-DECLARE_OBJ_CHECKERS(PPCE500MachineState, PPCE500MachineClass,
- PPCE500_MACHINE, TYPE_PPCE500_MACHINE)
+OBJECT_DECLARE_TYPE(PPCE500MachineState, PPCE500MachineClass, PPCE500_MACHINE)
#endif
/* Mac NVRAM */
#define TYPE_MACIO_NVRAM "macio-nvram"
-typedef struct MacIONVRAMState MacIONVRAMState;
-DECLARE_INSTANCE_CHECKER(MacIONVRAMState, MACIO_NVRAM,
- TYPE_MACIO_NVRAM)
+OBJECT_DECLARE_SIMPLE_TYPE(MacIONVRAMState, MACIO_NVRAM)
struct MacIONVRAMState {
/*< private >*/
#define MPC8544_GUTS_ADDR_SRDS2CR3 0xF18
#define TYPE_MPC8544_GUTS "mpc8544-guts"
-typedef struct GutsState GutsState;
-DECLARE_INSTANCE_CHECKER(GutsState, MPC8544_GUTS,
- TYPE_MPC8544_GUTS)
+OBJECT_DECLARE_SIMPLE_TYPE(GutsState, MPC8544_GUTS)
struct GutsState {
/*< private >*/
};
#define TYPE_PPC440_PCIX_HOST_BRIDGE "ppc440-pcix-host"
-typedef struct PPC440PCIXState PPC440PCIXState;
-DECLARE_INSTANCE_CHECKER(PPC440PCIXState, PPC440_PCIX_HOST_BRIDGE,
- TYPE_PPC440_PCIX_HOST_BRIDGE)
+OBJECT_DECLARE_SIMPLE_TYPE(PPC440PCIXState, PPC440_PCIX_HOST_BRIDGE)
#define PPC440_PCIX_NR_POMS 3
#define PPC440_PCIX_NR_PIMS 3
#include "hw/pci/pcie_host.h"
#define TYPE_PPC460EX_PCIE_HOST "ppc460ex-pcie-host"
-typedef struct PPC460EXPCIEState PPC460EXPCIEState;
-DECLARE_INSTANCE_CHECKER(PPC460EXPCIEState, PPC460EX_PCIE_HOST,
- TYPE_PPC460EX_PCIE_HOST)
+OBJECT_DECLARE_SIMPLE_TYPE(PPC460EXPCIEState, PPC460EX_PCIE_HOST)
struct PPC460EXPCIEState {
PCIExpressHost host;
uint32_t la;
};
-typedef struct PPC4xxPCIState PPC4xxPCIState;
-DECLARE_INSTANCE_CHECKER(PPC4xxPCIState, PPC4xx_PCI_HOST_BRIDGE,
- TYPE_PPC4xx_PCI_HOST_BRIDGE)
+OBJECT_DECLARE_SIMPLE_TYPE(PPC4xxPCIState, PPC4xx_PCI_HOST_BRIDGE)
#define PPC4xx_PCI_NR_PMMS 3
#define PPC4xx_PCI_NR_PTMS 2
struct PCIMasterMap pmm[PPC4xx_PCI_NR_PMMS];
struct PCITargetMap ptm[PPC4xx_PCI_NR_PTMS];
- qemu_irq irq[4];
+ qemu_irq irq[PCI_NUM_PINS];
MemoryRegion container;
MemoryRegion iomem;
} QEMU_PACKED SpinInfo;
#define TYPE_E500_SPIN "e500-spin"
-typedef struct SpinState SpinState;
-DECLARE_INSTANCE_CHECKER(SpinState, E500_SPIN,
- TYPE_E500_SPIN)
+OBJECT_DECLARE_SIMPLE_TYPE(SpinState, E500_SPIN)
struct SpinState {
SysBusDevice parent_obj;
#include "trace.h"
#define TYPE_PREP_SYSTEMIO "prep-systemio"
-typedef struct PrepSystemIoState PrepSystemIoState;
-DECLARE_INSTANCE_CHECKER(PrepSystemIoState, PREP_SYSTEMIO,
- TYPE_PREP_SYSTEMIO)
+OBJECT_DECLARE_SIMPLE_TYPE(PrepSystemIoState, PREP_SYSTEMIO)
/* Bit as defined in PowerPC Reference Plaform v1.1, sect. 6.1.5, p. 132 */
#define PREP_BIT(n) (1 << (7 - (n)))
#include "qom/object.h"
#define TYPE_RS6000MC "rs6000-mc"
-typedef struct RS6000MCState RS6000MCState;
-DECLARE_INSTANCE_CHECKER(RS6000MCState, RS6000MC,
- TYPE_RS6000MC)
+OBJECT_DECLARE_SIMPLE_TYPE(RS6000MCState, RS6000MC)
struct RS6000MCState {
ISADevice parent_obj;
#include "kvm_ppc.h"
#include "qom/object.h"
-typedef struct SpaprRngState SpaprRngState;
-DECLARE_INSTANCE_CHECKER(SpaprRngState, SPAPR_RNG,
- TYPE_SPAPR_RNG)
+OBJECT_DECLARE_SIMPLE_TYPE(SpaprRngState, SPAPR_RNG)
struct SpaprRngState {
/*< private >*/
hwaddr base;
hwaddr size;
} sifive_e_memmap[] = {
- [SIFIVE_E_DEBUG] = { 0x0, 0x1000 },
- [SIFIVE_E_MROM] = { 0x1000, 0x2000 },
- [SIFIVE_E_OTP] = { 0x20000, 0x2000 },
- [SIFIVE_E_CLINT] = { 0x2000000, 0x10000 },
- [SIFIVE_E_PLIC] = { 0xc000000, 0x4000000 },
- [SIFIVE_E_AON] = { 0x10000000, 0x8000 },
- [SIFIVE_E_PRCI] = { 0x10008000, 0x8000 },
- [SIFIVE_E_OTP_CTRL] = { 0x10010000, 0x1000 },
- [SIFIVE_E_GPIO0] = { 0x10012000, 0x1000 },
- [SIFIVE_E_UART0] = { 0x10013000, 0x1000 },
- [SIFIVE_E_QSPI0] = { 0x10014000, 0x1000 },
- [SIFIVE_E_PWM0] = { 0x10015000, 0x1000 },
- [SIFIVE_E_UART1] = { 0x10023000, 0x1000 },
- [SIFIVE_E_QSPI1] = { 0x10024000, 0x1000 },
- [SIFIVE_E_PWM1] = { 0x10025000, 0x1000 },
- [SIFIVE_E_QSPI2] = { 0x10034000, 0x1000 },
- [SIFIVE_E_PWM2] = { 0x10035000, 0x1000 },
- [SIFIVE_E_XIP] = { 0x20000000, 0x20000000 },
- [SIFIVE_E_DTIM] = { 0x80000000, 0x4000 }
+ [SIFIVE_E_DEV_DEBUG] = { 0x0, 0x1000 },
+ [SIFIVE_E_DEV_MROM] = { 0x1000, 0x2000 },
+ [SIFIVE_E_DEV_OTP] = { 0x20000, 0x2000 },
+ [SIFIVE_E_DEV_CLINT] = { 0x2000000, 0x10000 },
+ [SIFIVE_E_DEV_PLIC] = { 0xc000000, 0x4000000 },
+ [SIFIVE_E_DEV_AON] = { 0x10000000, 0x8000 },
+ [SIFIVE_E_DEV_PRCI] = { 0x10008000, 0x8000 },
+ [SIFIVE_E_DEV_OTP_CTRL] = { 0x10010000, 0x1000 },
+ [SIFIVE_E_DEV_GPIO0] = { 0x10012000, 0x1000 },
+ [SIFIVE_E_DEV_UART0] = { 0x10013000, 0x1000 },
+ [SIFIVE_E_DEV_QSPI0] = { 0x10014000, 0x1000 },
+ [SIFIVE_E_DEV_PWM0] = { 0x10015000, 0x1000 },
+ [SIFIVE_E_DEV_UART1] = { 0x10023000, 0x1000 },
+ [SIFIVE_E_DEV_QSPI1] = { 0x10024000, 0x1000 },
+ [SIFIVE_E_DEV_PWM1] = { 0x10025000, 0x1000 },
+ [SIFIVE_E_DEV_QSPI2] = { 0x10034000, 0x1000 },
+ [SIFIVE_E_DEV_PWM2] = { 0x10035000, 0x1000 },
+ [SIFIVE_E_DEV_XIP] = { 0x20000000, 0x20000000 },
+ [SIFIVE_E_DEV_DTIM] = { 0x80000000, 0x4000 }
};
static void sifive_e_machine_init(MachineState *machine)
/* Data Tightly Integrated Memory */
memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram",
- memmap[SIFIVE_E_DTIM].size, &error_fatal);
+ memmap[SIFIVE_E_DEV_DTIM].size, &error_fatal);
memory_region_add_subregion(sys_mem,
- memmap[SIFIVE_E_DTIM].base, main_mem);
+ memmap[SIFIVE_E_DEV_DTIM].base, main_mem);
/* Mask ROM reset vector */
uint32_t reset_vec[4];
reset_vec[i] = cpu_to_le32(reset_vec[i]);
}
rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
- memmap[SIFIVE_E_MROM].base, &address_space_memory);
+ memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory);
if (machine->kernel_filename) {
riscv_load_kernel(machine->kernel_filename, NULL);
/* Mask ROM */
memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom",
- memmap[SIFIVE_E_MROM].size, &error_fatal);
+ memmap[SIFIVE_E_DEV_MROM].size, &error_fatal);
memory_region_add_subregion(sys_mem,
- memmap[SIFIVE_E_MROM].base, &s->mask_rom);
+ memmap[SIFIVE_E_DEV_MROM].base, &s->mask_rom);
/* MMIO */
- s->plic = sifive_plic_create(memmap[SIFIVE_E_PLIC].base,
+ s->plic = sifive_plic_create(memmap[SIFIVE_E_DEV_PLIC].base,
(char *)SIFIVE_E_PLIC_HART_CONFIG, 0,
SIFIVE_E_PLIC_NUM_SOURCES,
SIFIVE_E_PLIC_NUM_PRIORITIES,
SIFIVE_E_PLIC_ENABLE_STRIDE,
SIFIVE_E_PLIC_CONTEXT_BASE,
SIFIVE_E_PLIC_CONTEXT_STRIDE,
- memmap[SIFIVE_E_PLIC].size);
- sifive_clint_create(memmap[SIFIVE_E_CLINT].base,
- memmap[SIFIVE_E_CLINT].size, 0, ms->smp.cpus,
+ memmap[SIFIVE_E_DEV_PLIC].size);
+ sifive_clint_create(memmap[SIFIVE_E_DEV_CLINT].base,
+ memmap[SIFIVE_E_DEV_CLINT].size, 0, ms->smp.cpus,
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
SIFIVE_CLINT_TIMEBASE_FREQ, false);
create_unimplemented_device("riscv.sifive.e.aon",
- memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
- sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base);
+ memmap[SIFIVE_E_DEV_AON].base, memmap[SIFIVE_E_DEV_AON].size);
+ sifive_e_prci_create(memmap[SIFIVE_E_DEV_PRCI].base);
/* GPIO */
}
/* Map GPIO registers */
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_GPIO0].base);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_DEV_GPIO0].base);
/* Pass all GPIOs to the SOC layer so they are available to the board */
qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
SIFIVE_E_GPIO0_IRQ0 + i));
}
- sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART0].base,
+ sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART0].base,
serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ));
create_unimplemented_device("riscv.sifive.e.qspi0",
- memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size);
+ memmap[SIFIVE_E_DEV_QSPI0].base, memmap[SIFIVE_E_DEV_QSPI0].size);
create_unimplemented_device("riscv.sifive.e.pwm0",
- memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size);
- sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base,
+ memmap[SIFIVE_E_DEV_PWM0].base, memmap[SIFIVE_E_DEV_PWM0].size);
+ sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART1].base,
serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ));
create_unimplemented_device("riscv.sifive.e.qspi1",
- memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size);
+ memmap[SIFIVE_E_DEV_QSPI1].base, memmap[SIFIVE_E_DEV_QSPI1].size);
create_unimplemented_device("riscv.sifive.e.pwm1",
- memmap[SIFIVE_E_PWM1].base, memmap[SIFIVE_E_PWM1].size);
+ memmap[SIFIVE_E_DEV_PWM1].base, memmap[SIFIVE_E_DEV_PWM1].size);
create_unimplemented_device("riscv.sifive.e.qspi2",
- memmap[SIFIVE_E_QSPI2].base, memmap[SIFIVE_E_QSPI2].size);
+ memmap[SIFIVE_E_DEV_QSPI2].base, memmap[SIFIVE_E_DEV_QSPI2].size);
create_unimplemented_device("riscv.sifive.e.pwm2",
- memmap[SIFIVE_E_PWM2].base, memmap[SIFIVE_E_PWM2].size);
+ memmap[SIFIVE_E_DEV_PWM2].base, memmap[SIFIVE_E_DEV_PWM2].size);
/* Flash memory */
memory_region_init_rom(&s->xip_mem, OBJECT(dev), "riscv.sifive.e.xip",
- memmap[SIFIVE_E_XIP].size, &error_fatal);
- memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_XIP].base,
+ memmap[SIFIVE_E_DEV_XIP].size, &error_fatal);
+ memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_DEV_XIP].base,
&s->xip_mem);
}
hwaddr base;
hwaddr size;
} sifive_u_memmap[] = {
- [SIFIVE_U_DEBUG] = { 0x0, 0x100 },
- [SIFIVE_U_MROM] = { 0x1000, 0xf000 },
- [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 },
- [SIFIVE_U_L2CC] = { 0x2010000, 0x1000 },
- [SIFIVE_U_PDMA] = { 0x3000000, 0x100000 },
- [SIFIVE_U_L2LIM] = { 0x8000000, 0x2000000 },
- [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 },
- [SIFIVE_U_PRCI] = { 0x10000000, 0x1000 },
- [SIFIVE_U_UART0] = { 0x10010000, 0x1000 },
- [SIFIVE_U_UART1] = { 0x10011000, 0x1000 },
- [SIFIVE_U_GPIO] = { 0x10060000, 0x1000 },
- [SIFIVE_U_OTP] = { 0x10070000, 0x1000 },
- [SIFIVE_U_GEM] = { 0x10090000, 0x2000 },
- [SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 },
- [SIFIVE_U_DMC] = { 0x100b0000, 0x10000 },
- [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 },
- [SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
+ [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 },
+ [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 },
+ [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 },
+ [SIFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 },
+ [SIFIVE_U_DEV_PDMA] = { 0x3000000, 0x100000 },
+ [SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 },
+ [SIFIVE_U_DEV_PLIC] = { 0xc000000, 0x4000000 },
+ [SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 },
+ [SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 },
+ [SIFIVE_U_DEV_UART1] = { 0x10011000, 0x1000 },
+ [SIFIVE_U_DEV_GPIO] = { 0x10060000, 0x1000 },
+ [SIFIVE_U_DEV_OTP] = { 0x10070000, 0x1000 },
+ [SIFIVE_U_DEV_GEM] = { 0x10090000, 0x2000 },
+ [SIFIVE_U_DEV_GEM_MGMT] = { 0x100a0000, 0x1000 },
+ [SIFIVE_U_DEV_DMC] = { 0x100b0000, 0x10000 },
+ [SIFIVE_U_DEV_FLASH0] = { 0x20000000, 0x10000000 },
+ [SIFIVE_U_DEV_DRAM] = { 0x80000000, 0x0 },
};
#define OTP_SERIAL 1
g_free(nodename);
nodename = g_strdup_printf("/memory@%lx",
- (long)memmap[SIFIVE_U_DRAM].base);
+ (long)memmap[SIFIVE_U_DEV_DRAM].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base,
+ memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].base,
mem_size >> 32, mem_size);
qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
g_free(nodename);
g_free(nodename);
}
nodename = g_strdup_printf("/soc/clint@%lx",
- (long)memmap[SIFIVE_U_CLINT].base);
+ (long)memmap[SIFIVE_U_DEV_CLINT].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_CLINT].base,
- 0x0, memmap[SIFIVE_U_CLINT].size);
+ 0x0, memmap[SIFIVE_U_DEV_CLINT].base,
+ 0x0, memmap[SIFIVE_U_DEV_CLINT].size);
qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
cells, ms->smp.cpus * sizeof(uint32_t) * 4);
g_free(cells);
g_free(nodename);
nodename = g_strdup_printf("/soc/otp@%lx",
- (long)memmap[SIFIVE_U_OTP].base);
+ (long)memmap[SIFIVE_U_DEV_OTP].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE);
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_OTP].base,
- 0x0, memmap[SIFIVE_U_OTP].size);
+ 0x0, memmap[SIFIVE_U_DEV_OTP].base,
+ 0x0, memmap[SIFIVE_U_DEV_OTP].size);
qemu_fdt_setprop_string(fdt, nodename, "compatible",
"sifive,fu540-c000-otp");
g_free(nodename);
prci_phandle = phandle++;
nodename = g_strdup_printf("/soc/clock-controller@%lx",
- (long)memmap[SIFIVE_U_PRCI].base);
+ (long)memmap[SIFIVE_U_DEV_PRCI].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle);
qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1);
qemu_fdt_setprop_cells(fdt, nodename, "clocks",
hfclk_phandle, rtcclk_phandle);
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_PRCI].base,
- 0x0, memmap[SIFIVE_U_PRCI].size);
+ 0x0, memmap[SIFIVE_U_DEV_PRCI].base,
+ 0x0, memmap[SIFIVE_U_DEV_PRCI].size);
qemu_fdt_setprop_string(fdt, nodename, "compatible",
"sifive,fu540-c000-prci");
g_free(nodename);
g_free(nodename);
}
nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
- (long)memmap[SIFIVE_U_PLIC].base);
+ (long)memmap[SIFIVE_U_DEV_PLIC].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t));
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_PLIC].base,
- 0x0, memmap[SIFIVE_U_PLIC].size);
+ 0x0, memmap[SIFIVE_U_DEV_PLIC].base,
+ 0x0, memmap[SIFIVE_U_DEV_PLIC].size);
qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
gpio_phandle = phandle++;
nodename = g_strdup_printf("/soc/gpio@%lx",
- (long)memmap[SIFIVE_U_GPIO].base);
+ (long)memmap[SIFIVE_U_DEV_GPIO].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle);
qemu_fdt_setprop_cells(fdt, nodename, "clocks",
qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2);
qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0);
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_GPIO].base,
- 0x0, memmap[SIFIVE_U_GPIO].size);
+ 0x0, memmap[SIFIVE_U_DEV_GPIO].base,
+ 0x0, memmap[SIFIVE_U_DEV_GPIO].size);
qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0,
SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3,
SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6,
g_free(nodename);
nodename = g_strdup_printf("/soc/dma@%lx",
- (long)memmap[SIFIVE_U_PDMA].base);
+ (long)memmap[SIFIVE_U_DEV_PDMA].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1);
qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7);
qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_PDMA].base,
- 0x0, memmap[SIFIVE_U_PDMA].size);
+ 0x0, memmap[SIFIVE_U_DEV_PDMA].base,
+ 0x0, memmap[SIFIVE_U_DEV_PDMA].size);
qemu_fdt_setprop_string(fdt, nodename, "compatible",
"sifive,fu540-c000-pdma");
g_free(nodename);
nodename = g_strdup_printf("/soc/cache-controller@%lx",
- (long)memmap[SIFIVE_U_L2CC].base);
+ (long)memmap[SIFIVE_U_DEV_L2CC].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_L2CC].base,
- 0x0, memmap[SIFIVE_U_L2CC].size);
+ 0x0, memmap[SIFIVE_U_DEV_L2CC].base,
+ 0x0, memmap[SIFIVE_U_DEV_L2CC].size);
qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2);
qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
phy_phandle = phandle++;
nodename = g_strdup_printf("/soc/ethernet@%lx",
- (long)memmap[SIFIVE_U_GEM].base);
+ (long)memmap[SIFIVE_U_DEV_GEM].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_string(fdt, nodename, "compatible",
"sifive,fu540-c000-gem");
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_GEM].base,
- 0x0, memmap[SIFIVE_U_GEM].size,
- 0x0, memmap[SIFIVE_U_GEM_MGMT].base,
- 0x0, memmap[SIFIVE_U_GEM_MGMT].size);
+ 0x0, memmap[SIFIVE_U_DEV_GEM].base,
+ 0x0, memmap[SIFIVE_U_DEV_GEM].size,
+ 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].base,
+ 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle);
g_free(nodename);
nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
- (long)memmap[SIFIVE_U_GEM].base);
+ (long)memmap[SIFIVE_U_DEV_GEM].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle);
qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
g_free(nodename);
nodename = g_strdup_printf("/soc/serial@%lx",
- (long)memmap[SIFIVE_U_UART0].base);
+ (long)memmap[SIFIVE_U_DEV_UART0].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_UART0].base,
- 0x0, memmap[SIFIVE_U_UART0].size);
+ 0x0, memmap[SIFIVE_U_DEV_UART0].base,
+ 0x0, memmap[SIFIVE_U_DEV_UART0].size);
qemu_fdt_setprop_cells(fdt, nodename, "clocks",
prci_phandle, PRCI_CLK_TLCLK);
qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
MemoryRegion *flash0 = g_new(MemoryRegion, 1);
- target_ulong start_addr = memmap[SIFIVE_U_DRAM].base;
+ target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
uint32_t start_addr_hi32 = 0x00000000;
int i;
uint32_t fdt_load_addr;
/* register RAM */
memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
machine->ram_size, &error_fatal);
- memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base,
+ memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base,
main_mem);
/* register QSPI0 Flash */
memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0",
- memmap[SIFIVE_U_FLASH0].size, &error_fatal);
- memory_region_add_subregion(system_memory, memmap[SIFIVE_U_FLASH0].base,
+ memmap[SIFIVE_U_DEV_FLASH0].size, &error_fatal);
+ memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_FLASH0].base,
flash0);
/* register gpio-restart */
switch (s->msel) {
case MSEL_MEMMAP_QSPI0_FLASH:
- start_addr = memmap[SIFIVE_U_FLASH0].base;
+ start_addr = memmap[SIFIVE_U_DEV_FLASH0].base;
break;
case MSEL_L2LIM_QSPI0_FLASH:
case MSEL_L2LIM_QSPI2_SD:
- start_addr = memmap[SIFIVE_U_L2LIM].base;
+ start_addr = memmap[SIFIVE_U_DEV_L2LIM].base;
break;
default:
- start_addr = memmap[SIFIVE_U_DRAM].base;
+ start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
break;
}
}
/* Compute the fdt load address in dram */
- fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DRAM].base,
+ fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base,
machine->ram_size, s->fdt);
#if defined(TARGET_RISCV64)
start_addr_hi32 = start_addr >> 32;
reset_vec[i] = cpu_to_le32(reset_vec[i]);
}
rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
- memmap[SIFIVE_U_MROM].base, &address_space_memory);
+ memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory);
- riscv_rom_copy_firmware_info(memmap[SIFIVE_U_MROM].base,
- memmap[SIFIVE_U_MROM].size,
+ riscv_rom_copy_firmware_info(memmap[SIFIVE_U_DEV_MROM].base,
+ memmap[SIFIVE_U_DEV_MROM].size,
sizeof(reset_vec), kernel_entry);
}
/* boot rom */
memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom",
- memmap[SIFIVE_U_MROM].size, &error_fatal);
- memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base,
+ memmap[SIFIVE_U_DEV_MROM].size, &error_fatal);
+ memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_MROM].base,
mask_rom);
/*
* too generous to misbehaving guests.
*/
memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim",
- memmap[SIFIVE_U_L2LIM].size, &error_fatal);
- memory_region_add_subregion(system_memory, memmap[SIFIVE_U_L2LIM].base,
+ memmap[SIFIVE_U_DEV_L2LIM].size, &error_fatal);
+ memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_L2LIM].base,
l2lim_mem);
/* create PLIC hart topology configuration string */
}
/* MMIO */
- s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base,
+ s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base,
plic_hart_config, 0,
SIFIVE_U_PLIC_NUM_SOURCES,
SIFIVE_U_PLIC_NUM_PRIORITIES,
SIFIVE_U_PLIC_ENABLE_STRIDE,
SIFIVE_U_PLIC_CONTEXT_BASE,
SIFIVE_U_PLIC_CONTEXT_STRIDE,
- memmap[SIFIVE_U_PLIC].size);
+ memmap[SIFIVE_U_DEV_PLIC].size);
g_free(plic_hart_config);
- sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
+ sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART0].base,
serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
- sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
+ sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base,
serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
- sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
- memmap[SIFIVE_U_CLINT].size, 0, ms->smp.cpus,
+ sifive_clint_create(memmap[SIFIVE_U_DEV_CLINT].base,
+ memmap[SIFIVE_U_DEV_CLINT].size, 0, ms->smp.cpus,
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
SIFIVE_CLINT_TIMEBASE_FREQ, false);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_DEV_PRCI].base);
qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_GPIO].base);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_DEV_GPIO].base);
/* Pass all GPIOs to the SOC layer so they are available to the board */
qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
/* PDMA */
sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_PDMA].base);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_DEV_PDMA].base);
/* Connect PDMA interrupts to the PLIC */
for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) {
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base);
/* FIXME use qdev NIC properties instead of nd_table[] */
if (nd->used) {
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) {
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_DEV_GEM].base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ));
create_unimplemented_device("riscv.sifive.u.gem-mgmt",
- memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
+ memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
create_unimplemented_device("riscv.sifive.u.dmc",
- memmap[SIFIVE_U_DMC].base, memmap[SIFIVE_U_DMC].size);
+ memmap[SIFIVE_U_DEV_DMC].base, memmap[SIFIVE_U_DEV_DMC].size);
create_unimplemented_device("riscv.sifive.u.l2cc",
- memmap[SIFIVE_U_L2CC].base, memmap[SIFIVE_U_L2CC].size);
+ memmap[SIFIVE_U_DEV_L2CC].base, memmap[SIFIVE_U_DEV_L2CC].size);
}
static Property sifive_u_soc_props[] = {
#define CTRL_OSF 0x20
#define TYPE_DS1338 "ds1338"
-typedef struct DS1338State DS1338State;
-DECLARE_INSTANCE_CHECKER(DS1338State, DS1338,
- TYPE_DS1338)
+OBJECT_DECLARE_SIMPLE_TYPE(DS1338State, DS1338)
struct DS1338State {
I2CSlave parent_obj;
#define RTC_BASE_FREQ 32768
#define TYPE_EXYNOS4210_RTC "exynos4210.rtc"
-typedef struct Exynos4210RTCState Exynos4210RTCState;
-DECLARE_INSTANCE_CHECKER(Exynos4210RTCState, EXYNOS4210_RTC,
- TYPE_EXYNOS4210_RTC)
+OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210RTCState, EXYNOS4210_RTC)
struct Exynos4210RTCState {
SysBusDevice parent_obj;
#include "qom/object.h"
#define TYPE_M41T80 "m41t80"
-typedef struct M41t80State M41t80State;
-DECLARE_INSTANCE_CHECKER(M41t80State, M41T80,
- TYPE_M41T80)
+OBJECT_DECLARE_SIMPLE_TYPE(M41t80State, M41T80)
struct M41t80State {
I2CSlave parent_obj;
#define TYPE_SUN4V_RTC "sun4v_rtc"
-typedef struct Sun4vRtc Sun4vRtc;
-DECLARE_INSTANCE_CHECKER(Sun4vRtc, SUN4V_RTC,
- TYPE_SUN4V_RTC)
+OBJECT_DECLARE_SIMPLE_TYPE(Sun4vRtc, SUN4V_RTC)
struct Sun4vRtc {
SysBusDevice parent_obj;
#define VERBOSE 1
#define TYPE_TWL92230 "twl92230"
-typedef struct MenelausState MenelausState;
-DECLARE_INSTANCE_CHECKER(MenelausState, TWL92230,
- TYPE_TWL92230)
+OBJECT_DECLARE_SIMPLE_TYPE(MenelausState, TWL92230)
struct MenelausState {
I2CSlave parent_obj;
void (*realize)(CcwDevice *, Error **);
void (*refill_ids)(CcwDevice *);
};
-typedef struct CCWDeviceClass CCWDeviceClass;
static inline CcwDevice *to_ccw_dev_fast(DeviceState *d)
{
#define TYPE_CCW_DEVICE "ccw-device"
-DECLARE_OBJ_CHECKERS(CcwDevice, CCWDeviceClass,
- CCW_DEVICE, TYPE_CCW_DEVICE)
+OBJECT_DECLARE_TYPE(CcwDevice, CCWDeviceClass, CCW_DEVICE)
#endif
typedef struct QemuIplParameters QemuIplParameters;
#define TYPE_S390_IPL "s390-ipl"
-typedef struct S390IPLState S390IPLState;
-DECLARE_INSTANCE_CHECKER(S390IPLState, S390_IPL,
- TYPE_S390_IPL)
+OBJECT_DECLARE_SIMPLE_TYPE(S390IPLState, S390_IPL)
struct S390IPLState {
/*< private >*/
#define UID_UNDEFINED 0
#define UID_CHECKING_ENABLED 0x01
-typedef struct S390pciState S390pciState;
-DECLARE_INSTANCE_CHECKER(S390pciState, S390_PCI_HOST_BRIDGE,
- TYPE_S390_PCI_HOST_BRIDGE)
-typedef struct S390PCIBus S390PCIBus;
-DECLARE_INSTANCE_CHECKER(S390PCIBus, S390_PCI_BUS,
- TYPE_S390_PCI_BUS)
-typedef struct S390PCIBusDevice S390PCIBusDevice;
-DECLARE_INSTANCE_CHECKER(S390PCIBusDevice, S390_PCI_DEVICE,
- TYPE_S390_PCI_DEVICE)
-typedef struct S390PCIIOMMU S390PCIIOMMU;
-DECLARE_INSTANCE_CHECKER(S390PCIIOMMU, S390_PCI_IOMMU,
- TYPE_S390_PCI_IOMMU)
+OBJECT_DECLARE_SIMPLE_TYPE(S390pciState, S390_PCI_HOST_BRIDGE)
+OBJECT_DECLARE_SIMPLE_TYPE(S390PCIBus, S390_PCI_BUS)
+OBJECT_DECLARE_SIMPLE_TYPE(S390PCIBusDevice, S390_PCI_DEVICE)
+OBJECT_DECLARE_SIMPLE_TYPE(S390PCIIOMMU, S390_PCI_IOMMU)
#define HP_EVENT_TO_CONFIGURED 0x0301
#define HP_EVENT_RESERVED_TO_STANDBY 0x0302
#define CCW_CMD_SET_VIRTIO_REV 0x83
#define TYPE_VIRTIO_CCW_DEVICE "virtio-ccw-device"
-typedef struct VirtIOCCWDeviceClass VirtIOCCWDeviceClass;
-typedef struct VirtioCcwDevice VirtioCcwDevice;
-DECLARE_OBJ_CHECKERS(VirtioCcwDevice, VirtIOCCWDeviceClass,
- VIRTIO_CCW_DEVICE, TYPE_VIRTIO_CCW_DEVICE)
+OBJECT_DECLARE_TYPE(VirtioCcwDevice, VirtIOCCWDeviceClass, VIRTIO_CCW_DEVICE)
typedef struct VirtioBusState VirtioCcwBusState;
typedef struct VirtioBusClass VirtioCcwBusClass;
/* virtio-scsi-ccw */
#define TYPE_VIRTIO_SCSI_CCW "virtio-scsi-ccw"
-typedef struct VirtIOSCSICcw VirtIOSCSICcw;
-DECLARE_INSTANCE_CHECKER(VirtIOSCSICcw, VIRTIO_SCSI_CCW,
- TYPE_VIRTIO_SCSI_CCW)
+OBJECT_DECLARE_SIMPLE_TYPE(VirtIOSCSICcw, VIRTIO_SCSI_CCW)
struct VirtIOSCSICcw {
VirtioCcwDevice parent_obj;
/* vhost-scsi-ccw */
#define TYPE_VHOST_SCSI_CCW "vhost-scsi-ccw"
-typedef struct VHostSCSICcw VHostSCSICcw;
-DECLARE_INSTANCE_CHECKER(VHostSCSICcw, VHOST_SCSI_CCW,
- TYPE_VHOST_SCSI_CCW)
+OBJECT_DECLARE_SIMPLE_TYPE(VHostSCSICcw, VHOST_SCSI_CCW)
struct VHostSCSICcw {
VirtioCcwDevice parent_obj;
/* virtio-blk-ccw */
#define TYPE_VIRTIO_BLK_CCW "virtio-blk-ccw"
-typedef struct VirtIOBlkCcw VirtIOBlkCcw;
-DECLARE_INSTANCE_CHECKER(VirtIOBlkCcw, VIRTIO_BLK_CCW,
- TYPE_VIRTIO_BLK_CCW)
+OBJECT_DECLARE_SIMPLE_TYPE(VirtIOBlkCcw, VIRTIO_BLK_CCW)
struct VirtIOBlkCcw {
VirtioCcwDevice parent_obj;
/* virtio-balloon-ccw */
#define TYPE_VIRTIO_BALLOON_CCW "virtio-balloon-ccw"
-typedef struct VirtIOBalloonCcw VirtIOBalloonCcw;
-DECLARE_INSTANCE_CHECKER(VirtIOBalloonCcw, VIRTIO_BALLOON_CCW,
- TYPE_VIRTIO_BALLOON_CCW)
+OBJECT_DECLARE_SIMPLE_TYPE(VirtIOBalloonCcw, VIRTIO_BALLOON_CCW)
struct VirtIOBalloonCcw {
VirtioCcwDevice parent_obj;
/* virtio-serial-ccw */
#define TYPE_VIRTIO_SERIAL_CCW "virtio-serial-ccw"
-typedef struct VirtioSerialCcw VirtioSerialCcw;
-DECLARE_INSTANCE_CHECKER(VirtioSerialCcw, VIRTIO_SERIAL_CCW,
- TYPE_VIRTIO_SERIAL_CCW)
+OBJECT_DECLARE_SIMPLE_TYPE(VirtioSerialCcw, VIRTIO_SERIAL_CCW)
struct VirtioSerialCcw {
VirtioCcwDevice parent_obj;
/* virtio-net-ccw */
#define TYPE_VIRTIO_NET_CCW "virtio-net-ccw"
-typedef struct VirtIONetCcw VirtIONetCcw;
-DECLARE_INSTANCE_CHECKER(VirtIONetCcw, VIRTIO_NET_CCW,
- TYPE_VIRTIO_NET_CCW)
+OBJECT_DECLARE_SIMPLE_TYPE(VirtIONetCcw, VIRTIO_NET_CCW)
struct VirtIONetCcw {
VirtioCcwDevice parent_obj;
/* virtio-rng-ccw */
#define TYPE_VIRTIO_RNG_CCW "virtio-rng-ccw"
-typedef struct VirtIORNGCcw VirtIORNGCcw;
-DECLARE_INSTANCE_CHECKER(VirtIORNGCcw, VIRTIO_RNG_CCW,
- TYPE_VIRTIO_RNG_CCW)
+OBJECT_DECLARE_SIMPLE_TYPE(VirtIORNGCcw, VIRTIO_RNG_CCW)
struct VirtIORNGCcw {
VirtioCcwDevice parent_obj;
/* virtio-crypto-ccw */
#define TYPE_VIRTIO_CRYPTO_CCW "virtio-crypto-ccw"
-typedef struct VirtIOCryptoCcw VirtIOCryptoCcw;
-DECLARE_INSTANCE_CHECKER(VirtIOCryptoCcw, VIRTIO_CRYPTO_CCW,
- TYPE_VIRTIO_CRYPTO_CCW)
+OBJECT_DECLARE_SIMPLE_TYPE(VirtIOCryptoCcw, VIRTIO_CRYPTO_CCW)
struct VirtIOCryptoCcw {
VirtioCcwDevice parent_obj;
#include "hw/9pfs/virtio-9p.h"
#define TYPE_VIRTIO_9P_CCW "virtio-9p-ccw"
-typedef struct V9fsCCWState V9fsCCWState;
-DECLARE_INSTANCE_CHECKER(V9fsCCWState, VIRTIO_9P_CCW,
- TYPE_VIRTIO_9P_CCW)
+OBJECT_DECLARE_SIMPLE_TYPE(V9fsCCWState, VIRTIO_9P_CCW)
struct V9fsCCWState {
VirtioCcwDevice parent_obj;
#ifdef CONFIG_VHOST_VSOCK
#define TYPE_VHOST_VSOCK_CCW "vhost-vsock-ccw"
-typedef struct VHostVSockCCWState VHostVSockCCWState;
-DECLARE_INSTANCE_CHECKER(VHostVSockCCWState, VHOST_VSOCK_CCW,
- TYPE_VHOST_VSOCK_CCW)
+OBJECT_DECLARE_SIMPLE_TYPE(VHostVSockCCWState, VHOST_VSOCK_CCW)
struct VHostVSockCCWState {
VirtioCcwDevice parent_obj;
#endif /* CONFIG_VHOST_VSOCK */
#define TYPE_VIRTIO_GPU_CCW "virtio-gpu-ccw"
-typedef struct VirtIOGPUCcw VirtIOGPUCcw;
-DECLARE_INSTANCE_CHECKER(VirtIOGPUCcw, VIRTIO_GPU_CCW,
- TYPE_VIRTIO_GPU_CCW)
+OBJECT_DECLARE_SIMPLE_TYPE(VirtIOGPUCcw, VIRTIO_GPU_CCW)
struct VirtIOGPUCcw {
VirtioCcwDevice parent_obj;
};
#define TYPE_VIRTIO_INPUT_CCW "virtio-input-ccw"
-typedef struct VirtIOInputCcw VirtIOInputCcw;
-DECLARE_INSTANCE_CHECKER(VirtIOInputCcw, VIRTIO_INPUT_CCW,
- TYPE_VIRTIO_INPUT_CCW)
+OBJECT_DECLARE_SIMPLE_TYPE(VirtIOInputCcw, VIRTIO_INPUT_CCW)
struct VirtIOInputCcw {
VirtioCcwDevice parent_obj;
#define TYPE_VIRTIO_KEYBOARD_CCW "virtio-keyboard-ccw"
#define TYPE_VIRTIO_MOUSE_CCW "virtio-mouse-ccw"
#define TYPE_VIRTIO_TABLET_CCW "virtio-tablet-ccw"
-typedef struct VirtIOInputHIDCcw VirtIOInputHIDCcw;
-DECLARE_INSTANCE_CHECKER(VirtIOInputHIDCcw, VIRTIO_INPUT_HID_CCW,
- TYPE_VIRTIO_INPUT_HID_CCW)
+OBJECT_DECLARE_SIMPLE_TYPE(VirtIOInputHIDCcw, VIRTIO_INPUT_HID_CCW)
struct VirtIOInputHIDCcw {
VirtioCcwDevice parent_obj;
uint8_t script_ram[2048 * sizeof(uint32_t)];
};
-typedef struct LSIState LSIState;
#define TYPE_LSI53C810 "lsi53c810"
#define TYPE_LSI53C895A "lsi53c895a"
-DECLARE_INSTANCE_CHECKER(LSIState, LSI53C895A,
- TYPE_LSI53C895A)
+OBJECT_DECLARE_SIMPLE_TYPE(LSIState, LSI53C895A)
static const char *scsi_phases[] = {
"DOUT",
#define TYPE_SCSI_DISK_BASE "scsi-disk-base"
-typedef struct SCSIDiskClass SCSIDiskClass;
-typedef struct SCSIDiskState SCSIDiskState;
-DECLARE_OBJ_CHECKERS(SCSIDiskState, SCSIDiskClass,
- SCSI_DISK_BASE, TYPE_SCSI_DISK_BASE)
+OBJECT_DECLARE_TYPE(SCSIDiskState, SCSIDiskClass, SCSI_DISK_BASE)
struct SCSIDiskClass {
SCSIDeviceClass parent_class;
} vscsi_req;
#define TYPE_VIO_SPAPR_VSCSI_DEVICE "spapr-vscsi"
-typedef struct VSCSIState VSCSIState;
-DECLARE_INSTANCE_CHECKER(VSCSIState, VIO_SPAPR_VSCSI_DEVICE,
- TYPE_VIO_SPAPR_VSCSI_DEVICE)
+OBJECT_DECLARE_SIMPLE_TYPE(VSCSIState, VIO_SPAPR_VSCSI_DEVICE)
struct VSCSIState {
SpaprVioDevice vdev;
PCIDeviceClass parent_class;
DeviceRealize parent_dc_realize;
};
-typedef struct PVSCSIClass PVSCSIClass;
#define TYPE_PVSCSI "pvscsi"
-typedef struct PVSCSIState PVSCSIState;
-DECLARE_OBJ_CHECKERS(PVSCSIState, PVSCSIClass,
- PVSCSI, TYPE_PVSCSI)
+OBJECT_DECLARE_TYPE(PVSCSIState, PVSCSIClass, PVSCSI)
/* Compatibility flags for migration */
};
#define TYPE_MILKYMIST_MEMCARD "milkymist-memcard"
-typedef struct MilkymistMemcardState MilkymistMemcardState;
-DECLARE_INSTANCE_CHECKER(MilkymistMemcardState, MILKYMIST_MEMCARD,
- TYPE_MILKYMIST_MEMCARD)
+OBJECT_DECLARE_SIMPLE_TYPE(MilkymistMemcardState, MILKYMIST_MEMCARD)
#define TYPE_MILKYMIST_SDBUS "milkymist-sdbus"
#define PL181_FIFO_LEN 16
#define TYPE_PL181 "pl181"
-typedef struct PL181State PL181State;
-DECLARE_INSTANCE_CHECKER(PL181State, PL181,
- TYPE_PL181)
+OBJECT_DECLARE_SIMPLE_TYPE(PL181State, PL181)
#define TYPE_PL181_BUS "pl181-bus"
int32_t stopping;
SDBus sdbus;
};
-typedef struct ssi_sd_state ssi_sd_state;
#define TYPE_SSI_SD "ssi-sd"
-DECLARE_INSTANCE_CHECKER(ssi_sd_state, SSI_SD,
- TYPE_SSI_SD)
+OBJECT_DECLARE_SIMPLE_TYPE(ssi_sd_state, SSI_SD)
/* State word bits. */
#define SSI_SDR_LOCKED 0x0001
#define TYPE_SH_PCI_HOST_BRIDGE "sh_pci"
-typedef struct SHPCIState SHPCIState;
-DECLARE_INSTANCE_CHECKER(SHPCIState, SH_PCI_HOST_BRIDGE,
- TYPE_SH_PCI_HOST_BRIDGE)
+OBJECT_DECLARE_SIMPLE_TYPE(SHPCIState, SH_PCI_HOST_BRIDGE)
struct SHPCIState {
PCIHostState parent_obj;
idreg_data, sizeof(idreg_data));
}
-typedef struct IDRegState IDRegState;
-DECLARE_INSTANCE_CHECKER(IDRegState, MACIO_ID_REGISTER,
- TYPE_MACIO_ID_REGISTER)
+OBJECT_DECLARE_SIMPLE_TYPE(IDRegState, MACIO_ID_REGISTER)
struct IDRegState {
SysBusDevice parent_obj;
};
#define TYPE_TCX_AFX "tcx_afx"
-typedef struct AFXState AFXState;
-DECLARE_INSTANCE_CHECKER(AFXState, TCX_AFX,
- TYPE_TCX_AFX)
+OBJECT_DECLARE_SIMPLE_TYPE(AFXState, TCX_AFX)
struct AFXState {
SysBusDevice parent_obj;
MemoryRegion bar0;
MemoryRegion bar1;
};
-typedef struct EbusState EbusState;
#define TYPE_EBUS "ebus"
-DECLARE_INSTANCE_CHECKER(EbusState, EBUS,
- TYPE_EBUS)
+OBJECT_DECLARE_SIMPLE_TYPE(EbusState, EBUS)
const char *fw_cfg_arch_key_name(uint16_t key)
{
} ResetData;
#define TYPE_SUN4U_POWER "power"
-typedef struct PowerDevice PowerDevice;
-DECLARE_INSTANCE_CHECKER(PowerDevice, SUN4U_POWER,
- TYPE_SUN4U_POWER)
+OBJECT_DECLARE_SIMPLE_TYPE(PowerDevice, SUN4U_POWER)
struct PowerDevice {
SysBusDevice parent_obj;
};
#define TYPE_SSI_BUS "SSI"
-DECLARE_INSTANCE_CHECKER(SSIBus, SSI_BUS,
- TYPE_SSI_BUS)
+OBJECT_DECLARE_SIMPLE_TYPE(SSIBus, SSI_BUS)
static const TypeInfo ssi_bus_info = {
.name = TYPE_SSI_BUS,
#define FIFO_CAPACITY 256
#define TYPE_XILINX_SPI "xlnx.xps-spi"
-typedef struct XilinxSPI XilinxSPI;
-DECLARE_INSTANCE_CHECKER(XilinxSPI, XILINX_SPI,
- TYPE_XILINX_SPI)
+OBJECT_DECLARE_SIMPLE_TYPE(XilinxSPI, XILINX_SPI)
struct XilinxSPI {
SysBusDevice parent_obj;
#define CONTROL_STOP 0x0008
#define TYPE_ALTERA_TIMER "ALTR.timer"
-typedef struct AlteraTimer AlteraTimer;
-DECLARE_INSTANCE_CHECKER(AlteraTimer, ALTERA_TIMER,
- TYPE_ALTERA_TIMER)
+OBJECT_DECLARE_SIMPLE_TYPE(AlteraTimer, ALTERA_TIMER)
struct AlteraTimer {
SysBusDevice busdev;
*/
#define TYPE_SP804 "sp804"
-typedef struct SP804State SP804State;
-DECLARE_INSTANCE_CHECKER(SP804State, SP804,
- TYPE_SP804)
+OBJECT_DECLARE_SIMPLE_TYPE(SP804State, SP804)
struct SP804State {
SysBusDevice parent_obj;
/* Integrator/CP timer module. */
#define TYPE_INTEGRATOR_PIT "integrator_pit"
-typedef struct icp_pit_state icp_pit_state;
-DECLARE_INSTANCE_CHECKER(icp_pit_state, INTEGRATOR_PIT,
- TYPE_INTEGRATOR_PIT)
+OBJECT_DECLARE_SIMPLE_TYPE(icp_pit_state, INTEGRATOR_PIT)
struct icp_pit_state {
SysBusDevice parent_obj;
} CadenceTimerState;
#define TYPE_CADENCE_TTC "cadence_ttc"
-typedef struct CadenceTTCState CadenceTTCState;
-DECLARE_INSTANCE_CHECKER(CadenceTTCState, CADENCE_TTC,
- TYPE_CADENCE_TTC)
+OBJECT_DECLARE_SIMPLE_TYPE(CadenceTTCState, CADENCE_TTC)
struct CadenceTTCState {
SysBusDevice parent_obj;
} Exynos4210MCTLT;
#define TYPE_EXYNOS4210_MCT "exynos4210.mct"
-typedef struct Exynos4210MCTState Exynos4210MCTState;
-DECLARE_INSTANCE_CHECKER(Exynos4210MCTState, EXYNOS4210_MCT,
- TYPE_EXYNOS4210_MCT)
+OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210MCTState, EXYNOS4210_MCT)
struct Exynos4210MCTState {
SysBusDevice parent_obj;
} Exynos4210PWM;
#define TYPE_EXYNOS4210_PWM "exynos4210.pwm"
-typedef struct Exynos4210PWMState Exynos4210PWMState;
-DECLARE_INSTANCE_CHECKER(Exynos4210PWMState, EXYNOS4210_PWM,
- TYPE_EXYNOS4210_PWM)
+OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210PWMState, EXYNOS4210_PWM)
struct Exynos4210PWMState {
SysBusDevice parent_obj;
#define COUNTER_RELOAD_OFFSET 0x04
#define TIMER_BASE 0x10
-typedef struct GPTimerUnit GPTimerUnit;
-DECLARE_INSTANCE_CHECKER(GPTimerUnit, GRLIB_GPTIMER,
- TYPE_GRLIB_GPTIMER)
+OBJECT_DECLARE_SIMPLE_TYPE(GPTimerUnit, GRLIB_GPTIMER)
typedef struct GPTimer GPTimer;
#define HPET_MSI_SUPPORT 0
-typedef struct HPETState HPETState;
-DECLARE_INSTANCE_CHECKER(HPETState, HPET,
- TYPE_HPET)
+OBJECT_DECLARE_SIMPLE_TYPE(HPETState, HPET)
struct HPETState;
typedef struct HPETTimer { /* timers */
update_irq(t, 0);
}
-#ifdef HPET_DEBUG
-static uint32_t hpet_ram_readb(void *opaque, hwaddr addr)
-{
- printf("qemu: hpet_read b at %" PRIx64 "\n", addr);
- return 0;
-}
-
-static uint32_t hpet_ram_readw(void *opaque, hwaddr addr)
-{
- printf("qemu: hpet_read w at %" PRIx64 "\n", addr);
- return 0;
-}
-#endif
-
static uint64_t hpet_ram_read(void *opaque, hwaddr addr,
unsigned size)
{
HPETState *s = opaque;
uint64_t old_val, new_val, val, index;
- DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value);
+ DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64 " = 0x%" PRIx64 "\n",
+ addr, value);
index = addr;
old_val = hpet_ram_read(opaque, addr, 4);
new_val = value;
uint8_t timer_id = (addr - 0x100) / 0x20;
HPETTimer *timer = &s->timer[timer_id];
- DPRINTF("qemu: hpet_ram_writel timer_id = %#x\n", timer_id);
+ DPRINTF("qemu: hpet_ram_writel timer_id = 0x%x\n", timer_id);
if (timer_id > s->num_timers) {
DPRINTF("qemu: timer id out of range\n");
return;
}
s->hpet_counter =
(s->hpet_counter & 0xffffffff00000000ULL) | value;
- DPRINTF("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n",
- value, s->hpet_counter);
+ DPRINTF("qemu: HPET counter written. ctr = 0x%" PRIx64 " -> "
+ "%" PRIx64 "\n", value, s->hpet_counter);
break;
case HPET_COUNTER + 4:
if (hpet_enabled(s)) {
}
s->hpet_counter =
(s->hpet_counter & 0xffffffffULL) | (((uint64_t)value) << 32);
- DPRINTF("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n",
- value, s->hpet_counter);
+ DPRINTF("qemu: HPET counter + 4 written. ctr = 0x%" PRIx64 " -> "
+ "%" PRIx64 "\n", value, s->hpet_counter);
break;
default:
DPRINTF("qemu: invalid hpet_ram_writel\n");
};
#define TYPE_LM32_TIMER "lm32-timer"
-typedef struct LM32TimerState LM32TimerState;
-DECLARE_INSTANCE_CHECKER(LM32TimerState, LM32_TIMER,
- TYPE_LM32_TIMER)
+OBJECT_DECLARE_SIMPLE_TYPE(LM32TimerState, LM32_TIMER)
struct LM32TimerState {
SysBusDevice parent_obj;
};
#define TYPE_MILKYMIST_SYSCTL "milkymist-sysctl"
-typedef struct MilkymistSysctlState MilkymistSysctlState;
-DECLARE_INSTANCE_CHECKER(MilkymistSysctlState, MILKYMIST_SYSCTL,
- TYPE_MILKYMIST_SYSCTL)
+OBJECT_DECLARE_SIMPLE_TYPE(MilkymistSysctlState, MILKYMIST_SYSCTL)
struct MilkymistSysctlState {
SysBusDevice parent_obj;
#include "hw/unicore32/puv3.h"
#define TYPE_PUV3_OST "puv3_ost"
-typedef struct PUV3OSTState PUV3OSTState;
-DECLARE_INSTANCE_CHECKER(PUV3OSTState, PUV3_OST,
- TYPE_PUV3_OST)
+OBJECT_DECLARE_SIMPLE_TYPE(PUV3OSTState, PUV3_OST)
/* puv3 ostimer implementation. */
struct PUV3OSTState {
};
#define TYPE_PXA2XX_TIMER "pxa2xx-timer"
-typedef struct PXA2xxTimerInfo PXA2xxTimerInfo;
-DECLARE_INSTANCE_CHECKER(PXA2xxTimerInfo, PXA2XX_TIMER,
- TYPE_PXA2XX_TIMER)
+OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxTimerInfo, PXA2XX_TIMER)
typedef struct {
} CPUTimerState;
#define TYPE_SLAVIO_TIMER "slavio_timer"
-typedef struct SLAVIO_TIMERState SLAVIO_TIMERState;
-DECLARE_INSTANCE_CHECKER(SLAVIO_TIMERState, SLAVIO_TIMER,
- TYPE_SLAVIO_TIMER)
+OBJECT_DECLARE_SIMPLE_TYPE(SLAVIO_TIMERState, SLAVIO_TIMER)
struct SLAVIO_TIMERState {
SysBusDevice parent_obj;
/*< public >*/
TPMState state; /* not a QOM object */
};
-typedef struct TPMStateISA TPMStateISA;
-DECLARE_INSTANCE_CHECKER(TPMStateISA, TPM_TIS_ISA,
- TYPE_TPM_TIS_ISA)
+OBJECT_DECLARE_SIMPLE_TYPE(TPMStateISA, TPM_TIS_ISA)
static int tpm_tis_pre_save_isa(void *opaque)
{
/*< public >*/
TPMState state; /* not a QOM object */
};
-typedef struct TPMStateSysBus TPMStateSysBus;
-DECLARE_INSTANCE_CHECKER(TPMStateSysBus, TPM_TIS_SYSBUS,
- TYPE_TPM_TIS_SYSBUS)
+OBJECT_DECLARE_SIMPLE_TYPE(TPMStateSysBus, TPM_TIS_SYSBUS)
static int tpm_tis_pre_save_sysbus(void *opaque)
{
#include "hw/qdev-core.h"
#include "qom/object.h"
-typedef struct CCIDCardState CCIDCardState;
typedef struct CCIDCardInfo CCIDCardInfo;
#define TYPE_CCID_CARD "ccid-card"
-typedef struct CCIDCardClass CCIDCardClass;
-DECLARE_OBJ_CHECKERS(CCIDCardState, CCIDCardClass,
- CCID_CARD, TYPE_CCID_CARD)
+OBJECT_DECLARE_TYPE(CCIDCardState, CCIDCardClass, CCID_CARD)
/*
* callbacks to be used by the CCID device (hw/usb-ccid.c) to call
uint32_t buffer_user, buffer;
bool multi;
};
-typedef struct USBAudioState USBAudioState;
#define TYPE_USB_AUDIO "usb-audio"
-DECLARE_INSTANCE_CHECKER(USBAudioState, USB_AUDIO,
- TYPE_USB_AUDIO)
+OBJECT_DECLARE_SIMPLE_TYPE(USBAudioState, USB_AUDIO)
static void output_callback(void *opaque, int avail)
{
char *display;
uint32_t head;
};
-typedef struct USBHIDState USBHIDState;
#define TYPE_USB_HID "usb-hid"
-DECLARE_INSTANCE_CHECKER(USBHIDState, USB_HID,
- TYPE_USB_HID)
+OBJECT_DECLARE_SIMPLE_TYPE(USBHIDState, USB_HID)
enum {
STR_MANUFACTURER = 1,
QEMUTimer *port_timer;
USBHubPort ports[MAX_PORTS];
};
-typedef struct USBHubState USBHubState;
#define TYPE_USB_HUB "usb-hub"
-DECLARE_INSTANCE_CHECKER(USBHubState, USB_HUB,
- TYPE_USB_HUB)
+OBJECT_DECLARE_SIMPLE_TYPE(USBHubState, USB_HUB)
#define ClearHubFeature (0x2000 | USB_REQ_CLEAR_FEATURE)
#define ClearPortFeature (0x2300 | USB_REQ_CLEAR_FEATURE)
} QEMU_PACKED ObjectInfo;
#define TYPE_USB_MTP "usb-mtp"
-DECLARE_INSTANCE_CHECKER(MTPState, USB_MTP,
- TYPE_USB_MTP)
+OBJECT_DECLARE_SIMPLE_TYPE(MTPState, USB_MTP)
#define QEMU_STORAGE_ID 0x00010001
NICConf conf;
QTAILQ_HEAD(, rndis_response) rndis_resp;
};
-typedef struct USBNetState USBNetState;
#define TYPE_USB_NET "usb-net"
-DECLARE_INSTANCE_CHECKER(USBNetState, USB_NET,
- TYPE_USB_NET)
+OBJECT_DECLARE_SIMPLE_TYPE(USBNetState, USB_NET)
static int is_rndis(USBNetState *s)
{
int latency; /* ms */
CharBackend cs;
};
-typedef struct USBSerialState USBSerialState;
#define TYPE_USB_SERIAL "usb-serial-dev"
-DECLARE_INSTANCE_CHECKER(USBSerialState, USB_SERIAL,
- TYPE_USB_SERIAL)
+OBJECT_DECLARE_SIMPLE_TYPE(USBSerialState, USB_SERIAL)
enum {
STR_MANUFACTURER = 1,
#define D_VERBOSE 4
#define TYPE_USB_CCID_DEV "usb-ccid"
-typedef struct USBCCIDState USBCCIDState;
-DECLARE_INSTANCE_CHECKER(USBCCIDState, USB_CCID_DEV,
- TYPE_USB_CCID_DEV)
+OBJECT_DECLARE_SIMPLE_TYPE(USBCCIDState, USB_CCID_DEV)
/*
* The two options for variable sized buffers:
* make them constant size, for large enough constant,
};
#define TYPE_CCID_BUS "ccid-bus"
-DECLARE_INSTANCE_CHECKER(CCIDBus, CCID_BUS,
- TYPE_CCID_BUS)
+OBJECT_DECLARE_SIMPLE_TYPE(CCIDBus, CCID_BUS)
static const TypeInfo ccid_bus_info = {
.name = TYPE_CCID_BUS,
};
#define TYPE_USB_UAS "usb-uas"
-DECLARE_INSTANCE_CHECKER(UASDevice, USB_UAS,
- TYPE_USB_UAS)
+OBJECT_DECLARE_SIMPLE_TYPE(UASDevice, USB_UAS)
struct UASRequest {
uint16_t tag;
uint8_t idle;
int changed;
};
-typedef struct USBWacomState USBWacomState;
#define TYPE_USB_WACOM "usb-wacom-tablet"
-DECLARE_INSTANCE_CHECKER(USBWacomState, USB_WACOM,
- TYPE_USB_WACOM)
+OBJECT_DECLARE_SIMPLE_TYPE(USBWacomState, USB_WACOM)
enum {
STR_MANUFACTURER = 1,
};
#define TYPE_DWC2_USB "dwc2-usb"
-DECLARE_OBJ_CHECKERS(DWC2State, DWC2Class,
- DWC2_USB, TYPE_DWC2_USB)
+OBJECT_DECLARE_TYPE(DWC2State, DWC2Class, DWC2_USB)
#endif
void ehci_reset(void *opaque);
#define TYPE_PCI_EHCI "pci-ehci-usb"
-typedef struct EHCIPCIState EHCIPCIState;
-DECLARE_INSTANCE_CHECKER(EHCIPCIState, PCI_EHCI,
- TYPE_PCI_EHCI)
+OBJECT_DECLARE_SIMPLE_TYPE(EHCIPCIState, PCI_EHCI)
struct EHCIPCIState {
/*< private >*/
#define TYPE_PPC4xx_EHCI "ppc4xx-ehci-usb"
#define TYPE_FUSBH200_EHCI "fusbh200-ehci-usb"
-typedef struct EHCISysBusState EHCISysBusState;
-typedef struct SysBusEHCIClass SysBusEHCIClass;
-DECLARE_OBJ_CHECKERS(EHCISysBusState, SysBusEHCIClass,
- SYS_BUS_EHCI, TYPE_SYS_BUS_EHCI)
+OBJECT_DECLARE_TYPE(EHCISysBusState, SysBusEHCIClass, SYS_BUS_EHCI)
struct EHCISysBusState {
/*< private >*/
uint16_t portnr;
};
-typedef struct FUSBH200EHCIState FUSBH200EHCIState;
-DECLARE_INSTANCE_CHECKER(FUSBH200EHCIState, FUSBH200_EHCI,
- TYPE_FUSBH200_EHCI)
+OBJECT_DECLARE_SIMPLE_TYPE(FUSBH200EHCIState, FUSBH200_EHCI)
struct FUSBH200EHCIState {
/*< private >*/
#include "qom/object.h"
#define TYPE_PCI_OHCI "pci-ohci"
-typedef struct OHCIPCIState OHCIPCIState;
-DECLARE_INSTANCE_CHECKER(OHCIPCIState, PCI_OHCI,
- TYPE_PCI_OHCI)
+OBJECT_DECLARE_SIMPLE_TYPE(OHCIPCIState, PCI_OHCI)
struct OHCIPCIState {
/*< private >*/
} OHCIState;
#define TYPE_SYSBUS_OHCI "sysbus-ohci"
-typedef struct OHCISysBusState OHCISysBusState;
-DECLARE_INSTANCE_CHECKER(OHCISysBusState, SYSBUS_OHCI,
- TYPE_SYSBUS_OHCI)
+OBJECT_DECLARE_SIMPLE_TYPE(OHCISysBusState, SYSBUS_OHCI)
struct OHCISysBusState {
/*< private >*/
#define TYPE_NEC_XHCI "nec-usb-xhci"
#define TYPE_QEMU_XHCI "qemu-xhci"
-typedef struct XHCIState XHCIState;
-DECLARE_INSTANCE_CHECKER(XHCIState, XHCI,
- TYPE_XHCI)
+OBJECT_DECLARE_SIMPLE_TYPE(XHCIState, XHCI)
#define MAXPORTS_2 15
#define MAXPORTS_3 15
/* ------------------------------------------------------------------------ */
#define TYPE_USB_HOST_DEVICE "usb-host"
-typedef struct USBHostDevice USBHostDevice;
-DECLARE_INSTANCE_CHECKER(USBHostDevice, USB_HOST_DEVICE,
- TYPE_USB_HOST_DEVICE)
+OBJECT_DECLARE_SIMPLE_TYPE(USBHostDevice, USB_HOST_DEVICE)
typedef struct USBHostRequest USBHostRequest;
typedef struct USBHostIsoXfer USBHostIsoXfer;
#include "qom/object.h"
#define TYPE_TUSB6010 "tusb6010"
-typedef struct TUSBState TUSBState;
-DECLARE_INSTANCE_CHECKER(TUSBState, TUSB6010,
- TYPE_TUSB6010)
+OBJECT_DECLARE_SIMPLE_TYPE(TUSBState, TUSB6010)
struct TUSBState {
SysBusDevice parent_obj;
APDevice apdev;
VFIODevice vdev;
};
-typedef struct VFIOAPDevice VFIOAPDevice;
-DECLARE_INSTANCE_CHECKER(VFIOAPDevice, VFIO_AP_DEVICE,
- TYPE_VFIO_AP_DEVICE)
+OBJECT_DECLARE_SIMPLE_TYPE(VFIOAPDevice, VFIO_AP_DEVICE)
static void vfio_ap_compute_needs_reset(VFIODevice *vdev)
{
} VFIOMSIXInfo;
#define TYPE_VFIO_PCI "vfio-pci"
-typedef struct VFIOPCIDevice VFIOPCIDevice;
-DECLARE_INSTANCE_CHECKER(VFIOPCIDevice, VFIO_PCI,
- TYPE_VFIO_PCI)
+OBJECT_DECLARE_SIMPLE_TYPE(VFIOPCIDevice, VFIO_PCI)
struct VFIOPCIDevice {
PCIDevice pdev;
#include "qemu/module.h"
#include "qom/object.h"
-typedef struct VirtIOInputPCI VirtIOInputPCI;
-typedef struct VirtIOInputHIDPCI VirtIOInputHIDPCI;
/*
* virtio-input-pci: This extends VirtioPCIProxy.
*/
-DECLARE_INSTANCE_CHECKER(VirtIOInputPCI, VIRTIO_INPUT_PCI,
- TYPE_VIRTIO_INPUT_PCI)
+OBJECT_DECLARE_SIMPLE_TYPE(VirtIOInputPCI, VIRTIO_INPUT_PCI)
struct VirtIOInputPCI {
VirtIOPCIProxy parent_obj;
#define TYPE_VIRTIO_KEYBOARD_PCI "virtio-keyboard-pci"
#define TYPE_VIRTIO_MOUSE_PCI "virtio-mouse-pci"
#define TYPE_VIRTIO_TABLET_PCI "virtio-tablet-pci"
-DECLARE_INSTANCE_CHECKER(VirtIOInputHIDPCI, VIRTIO_INPUT_HID_PCI,
- TYPE_VIRTIO_INPUT_HID_PCI)
+OBJECT_DECLARE_SIMPLE_TYPE(VirtIOInputHIDPCI, VIRTIO_INPUT_HID_PCI)
struct VirtIOInputHIDPCI {
VirtIOPCIProxy parent_obj;
#include "hw/virtio/virtio-bus.h"
#include "qom/object.h"
-typedef struct VirtIOPCIProxy VirtIOPCIProxy;
/* virtio-pci-bus */
* virtio-pci: This is the PCIDevice which has a virtio-pci-bus.
*/
#define TYPE_VIRTIO_PCI "virtio-pci"
-typedef struct VirtioPCIClass VirtioPCIClass;
-DECLARE_OBJ_CHECKERS(VirtIOPCIProxy, VirtioPCIClass,
- VIRTIO_PCI, TYPE_VIRTIO_PCI)
+OBJECT_DECLARE_TYPE(VirtIOPCIProxy, VirtioPCIClass, VIRTIO_PCI)
struct VirtioPCIClass {
PCIDeviceClass parent_class;
*/
};
-typedef struct I6300State I6300State;
#define TYPE_WATCHDOG_I6300ESB_DEVICE "i6300esb"
-DECLARE_INSTANCE_CHECKER(I6300State, WATCHDOG_I6300ESB_DEVICE,
- TYPE_WATCHDOG_I6300ESB_DEVICE)
+OBJECT_DECLARE_SIMPLE_TYPE(I6300State, WATCHDOG_I6300ESB_DEVICE)
/* This function is called when the watchdog has either been enabled
* (hence it starts counting down) or has been keep-alived.
typedef const struct XenPTRegInfo XenPTRegInfo;
typedef struct XenPTReg XenPTReg;
-typedef struct XenPCIPassthroughState XenPCIPassthroughState;
#define TYPE_XEN_PT_DEVICE "xen-pci-passthrough"
-DECLARE_INSTANCE_CHECKER(XenPCIPassthroughState, XEN_PT_DEVICE,
- TYPE_XEN_PT_DEVICE)
+OBJECT_DECLARE_SIMPLE_TYPE(XenPCIPassthroughState, XEN_PT_DEVICE)
uint32_t igd_read_opregion(XenPCIPassthroughState *s);
void igd_write_opregion(XenPCIPassthroughState *s, uint32_t val);
#define TYPE_QAUTHZ "authz"
OBJECT_DECLARE_TYPE(QAuthZ, QAuthZClass,
- qauthz, QAUTHZ)
+ QAUTHZ)
/**
#define TYPE_QAUTHZ_LIST "authz-list"
-OBJECT_DECLARE_SIMPLE_TYPE(QAuthZList, qauthz_list,
- QAUTHZ_LIST, QAuthZClass)
+OBJECT_DECLARE_SIMPLE_TYPE(QAuthZList,
+ QAUTHZ_LIST)
#define TYPE_QAUTHZ_LIST_FILE "authz-list-file"
-OBJECT_DECLARE_SIMPLE_TYPE(QAuthZListFile, qauthz_list_file,
- QAUTHZ_LIST_FILE, QAuthZClass)
+OBJECT_DECLARE_SIMPLE_TYPE(QAuthZListFile,
+ QAUTHZ_LIST_FILE)
#define TYPE_QAUTHZ_PAM "authz-pam"
-OBJECT_DECLARE_SIMPLE_TYPE(QAuthZPAM, qauthz_pam,
- QAUTHZ_PAM, QAuthZClass)
+OBJECT_DECLARE_SIMPLE_TYPE(QAuthZPAM,
+ QAUTHZ_PAM)
#define TYPE_QAUTHZ_SIMPLE "authz-simple"
-OBJECT_DECLARE_SIMPLE_TYPE(QAuthZSimple, qauthz_simple,
- QAUTHZ_SIMPLE, QAuthZClass)
+OBJECT_DECLARE_SIMPLE_TYPE(QAuthZSimple,
+ QAUTHZ_SIMPLE)
} ThrottleGroupMember;
#define TYPE_THROTTLE_GROUP "throttle-group"
-typedef struct ThrottleGroup ThrottleGroup;
-DECLARE_INSTANCE_CHECKER(ThrottleGroup, THROTTLE_GROUP,
- TYPE_THROTTLE_GROUP)
+OBJECT_DECLARE_SIMPLE_TYPE(ThrottleGroup, THROTTLE_GROUP)
const char *throttle_group_get_name(ThrottleGroupMember *tgm);
int qemu_chr_wait_connected(Chardev *chr, Error **errp);
#define TYPE_CHARDEV "chardev"
-typedef struct ChardevClass ChardevClass;
-DECLARE_OBJ_CHECKERS(Chardev, ChardevClass,
- CHARDEV, TYPE_CHARDEV)
+OBJECT_DECLARE_TYPE(Chardev, ChardevClass, CHARDEV)
#define TYPE_CHARDEV_NULL "chardev-null"
#define TYPE_CHARDEV_MUX "chardev-mux"
#define TYPE_QCRYPTO_SECRET_COMMON "secret_common"
OBJECT_DECLARE_TYPE(QCryptoSecretCommon, QCryptoSecretCommonClass,
- qcrypto_secret_common, QCRYPTO_SECRET_COMMON)
+ QCRYPTO_SECRET_COMMON)
struct QCryptoSecretCommon {
#include "crypto/secret_common.h"
#define TYPE_QCRYPTO_SECRET_KEYRING "secret_keyring"
-OBJECT_DECLARE_SIMPLE_TYPE(QCryptoSecretKeyring, qcrypto_secret_keyring,
- QCRYPTO_SECRET_KEYRING, QCryptoSecretCommonClass)
+OBJECT_DECLARE_SIMPLE_TYPE(QCryptoSecretKeyring,
+ QCRYPTO_SECRET_KEYRING)
struct QCryptoSecretKeyring {
#define ACPI_POWER_BUTTON_DEVICE "PWRB"
#define TYPE_ACPI_GED "acpi-ged"
-typedef struct AcpiGedState AcpiGedState;
-DECLARE_INSTANCE_CHECKER(AcpiGedState, ACPI_GED,
- TYPE_ACPI_GED)
+OBJECT_DECLARE_SIMPLE_TYPE(AcpiGedState, ACPI_GED)
#define TYPE_ACPI_GED_X86 "acpi-ged-x86"
#define ACPI_GED_X86(obj) \
* OVMF SDT Header Probe Supressor
*/
-typedef struct VmGenIdState VmGenIdState;
-DECLARE_INSTANCE_CHECKER(VmGenIdState, VMGENID,
- TYPE_VMGENID)
+OBJECT_DECLARE_SIMPLE_TYPE(VmGenIdState, VMGENID)
struct VmGenIdState {
DeviceClass parent_obj;
#define ADC_COMMON_ADDRESS 0x100
#define TYPE_STM32F2XX_ADC "stm32f2xx-adc"
-typedef struct STM32F2XXADCState STM32F2XXADCState;
-DECLARE_INSTANCE_CHECKER(STM32F2XXADCState, STM32F2XX_ADC,
- TYPE_STM32F2XX_ADC)
+OBJECT_DECLARE_SIMPLE_TYPE(STM32F2XXADCState, STM32F2XX_ADC)
struct STM32F2XXADCState {
/* <private> */
#define AW_A10_NUM_USB 2
#define TYPE_AW_A10 "allwinner-a10"
-typedef struct AwA10State AwA10State;
-DECLARE_INSTANCE_CHECKER(AwA10State, AW_A10,
- TYPE_AW_A10)
+OBJECT_DECLARE_SIMPLE_TYPE(AwA10State, AW_A10)
struct AwA10State {
/*< private >*/
#define TYPE_AW_H3 "allwinner-h3"
/** Convert input object to Allwinner H3 state object */
-typedef struct AwH3State AwH3State;
-DECLARE_INSTANCE_CHECKER(AwH3State, AW_H3,
- TYPE_AW_H3)
+OBJECT_DECLARE_SIMPLE_TYPE(AwH3State, AW_H3)
/** @} */
#define TYPE_ARM_SSE "arm-sse"
OBJECT_DECLARE_TYPE(ARMSSE, ARMSSEClass,
- arm_sse, ARM_SSE)
+ ARM_SSE)
/*
* These type names are for specific IoTKit subsystems; other than
#include "qom/object.h"
#define TYPE_BITBAND "ARM,bitband-memory"
-typedef struct BitBandState BitBandState;
-DECLARE_INSTANCE_CHECKER(BitBandState, BITBAND,
- TYPE_BITBAND)
+OBJECT_DECLARE_SIMPLE_TYPE(BitBandState, BITBAND)
struct BitBandState {
/*< private >*/
};
#define TYPE_ARMV7M "armv7m"
-typedef struct ARMv7MState ARMv7MState;
-DECLARE_INSTANCE_CHECKER(ARMv7MState, ARMV7M,
- TYPE_ARMV7M)
+OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MState, ARMV7M)
#define ARMV7M_NUM_BITBANDS 2
AspeedSDHCIState sdhci;
AspeedSDHCIState emmc;
};
-typedef struct AspeedSoCState AspeedSoCState;
#define TYPE_ASPEED_SOC "aspeed-soc"
-typedef struct AspeedSoCClass AspeedSoCClass;
-DECLARE_OBJ_CHECKERS(AspeedSoCState, AspeedSoCClass,
- ASPEED_SOC, TYPE_ASPEED_SOC)
+OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
struct AspeedSoCClass {
DeviceClass parent_class;
#include "qom/object.h"
#define TYPE_BCM2835_PERIPHERALS "bcm2835-peripherals"
-typedef struct BCM2835PeripheralState BCM2835PeripheralState;
-DECLARE_INSTANCE_CHECKER(BCM2835PeripheralState, BCM2835_PERIPHERALS,
- TYPE_BCM2835_PERIPHERALS)
+OBJECT_DECLARE_SIMPLE_TYPE(BCM2835PeripheralState, BCM2835_PERIPHERALS)
struct BCM2835PeripheralState {
/*< private >*/
#include "qom/object.h"
#define TYPE_BCM283X "bcm283x"
-typedef struct BCM283XClass BCM283XClass;
-typedef struct BCM283XState BCM283XState;
-DECLARE_OBJ_CHECKERS(BCM283XState, BCM283XClass,
- BCM283X, TYPE_BCM283X)
+OBJECT_DECLARE_TYPE(BCM283XState, BCM283XClass, BCM283X)
#define BCM283X_NCPUS 4
#define TYPE_DIGIC "digic"
-typedef struct DigicState DigicState;
-DECLARE_INSTANCE_CHECKER(DigicState, DIGIC,
- TYPE_DIGIC)
+OBJECT_DECLARE_SIMPLE_TYPE(DigicState, DIGIC)
#define DIGIC4_NB_TIMERS 3
I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA];
};
-typedef struct Exynos4210State Exynos4210State;
#define TYPE_EXYNOS4210_SOC "exynos4210"
-DECLARE_INSTANCE_CHECKER(Exynos4210State, EXYNOS4210_SOC,
- TYPE_EXYNOS4210_SOC)
+OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210State, EXYNOS4210_SOC)
void exynos4210_write_secondary(ARMCPU *cpu,
const struct arm_boot_info *info);
#include "qom/object.h"
#define TYPE_FSL_IMX25 "fsl,imx25"
-typedef struct FslIMX25State FslIMX25State;
-DECLARE_INSTANCE_CHECKER(FslIMX25State, FSL_IMX25,
- TYPE_FSL_IMX25)
+OBJECT_DECLARE_SIMPLE_TYPE(FslIMX25State, FSL_IMX25)
#define FSL_IMX25_NUM_UARTS 5
#define FSL_IMX25_NUM_GPTS 4
#include "qom/object.h"
#define TYPE_FSL_IMX31 "fsl,imx31"
-typedef struct FslIMX31State FslIMX31State;
-DECLARE_INSTANCE_CHECKER(FslIMX31State, FSL_IMX31,
- TYPE_FSL_IMX31)
+OBJECT_DECLARE_SIMPLE_TYPE(FslIMX31State, FSL_IMX31)
#define FSL_IMX31_NUM_UARTS 2
#define FSL_IMX31_NUM_EPITS 2
#include "qom/object.h"
#define TYPE_FSL_IMX6 "fsl,imx6"
-typedef struct FslIMX6State FslIMX6State;
-DECLARE_INSTANCE_CHECKER(FslIMX6State, FSL_IMX6,
- TYPE_FSL_IMX6)
+OBJECT_DECLARE_SIMPLE_TYPE(FslIMX6State, FSL_IMX6)
#define FSL_IMX6_NUM_CPUS 4
#define FSL_IMX6_NUM_UARTS 5
#include "qom/object.h"
#define TYPE_FSL_IMX6UL "fsl,imx6ul"
-typedef struct FslIMX6ULState FslIMX6ULState;
-DECLARE_INSTANCE_CHECKER(FslIMX6ULState, FSL_IMX6UL,
- TYPE_FSL_IMX6UL)
+OBJECT_DECLARE_SIMPLE_TYPE(FslIMX6ULState, FSL_IMX6UL)
enum FslIMX6ULConfiguration {
FSL_IMX6UL_NUM_CPUS = 1,
#include "qom/object.h"
#define TYPE_FSL_IMX7 "fsl,imx7"
-typedef struct FslIMX7State FslIMX7State;
-DECLARE_INSTANCE_CHECKER(FslIMX7State, FSL_IMX7,
- TYPE_FSL_IMX7)
+OBJECT_DECLARE_SIMPLE_TYPE(FslIMX7State, FSL_IMX7)
enum FslIMX7Configuration {
FSL_IMX7_NUM_CPUS = 2,
#include "qom/object.h"
#define TYPE_MSF2_SOC "msf2-soc"
-typedef struct MSF2State MSF2State;
-DECLARE_INSTANCE_CHECKER(MSF2State, MSF2_SOC,
- TYPE_MSF2_SOC)
+OBJECT_DECLARE_SIMPLE_TYPE(MSF2State, MSF2_SOC)
#define MSF2_NUM_SPIS 2
#define MSF2_NUM_UARTS 2
#include "qom/object.h"
#define TYPE_NRF51_SOC "nrf51-soc"
-typedef struct NRF51State NRF51State;
-DECLARE_INSTANCE_CHECKER(NRF51State, NRF51_SOC,
- TYPE_NRF51_SOC)
+OBJECT_DECLARE_SIMPLE_TYPE(NRF51State, NRF51_SOC)
#define NRF51_NUM_TIMERS 3
/* omap_i2c.c */
#define TYPE_OMAP_I2C "omap_i2c"
-typedef struct OMAPI2CState OMAPI2CState;
-DECLARE_INSTANCE_CHECKER(OMAPI2CState, OMAP_I2C,
- TYPE_OMAP_I2C)
+OBJECT_DECLARE_SIMPLE_TYPE(OMAPI2CState, OMAP_I2C)
/* TODO: clock framework (see above) */
/* pxa2xx_mmci.c */
#define TYPE_PXA2XX_MMCI "pxa2xx-mmci"
-typedef struct PXA2xxMMCIState PXA2xxMMCIState;
-DECLARE_INSTANCE_CHECKER(PXA2xxMMCIState, PXA2XX_MMCI,
- TYPE_PXA2XX_MMCI)
+OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxMMCIState, PXA2XX_MMCI)
PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem,
hwaddr base,
/* pxa2xx_pcmcia.c */
#define TYPE_PXA2XX_PCMCIA "pxa2xx-pcmcia"
-typedef struct PXA2xxPCMCIAState PXA2xxPCMCIAState;
-DECLARE_INSTANCE_CHECKER(PXA2xxPCMCIAState, PXA2XX_PCMCIA,
- TYPE_PXA2XX_PCMCIA)
+OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxPCMCIAState, PXA2XX_PCMCIA)
PXA2xxPCMCIAState *pxa2xx_pcmcia_init(MemoryRegion *sysmem,
hwaddr base);
#define TYPE_PXA2XX_I2C "pxa2xx_i2c"
typedef struct PXA2xxI2SState PXA2xxI2SState;
-DECLARE_INSTANCE_CHECKER(PXA2xxI2CState, PXA2XX_I2C,
- TYPE_PXA2XX_I2C)
+OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxI2CState, PXA2XX_I2C)
#define TYPE_PXA2XX_FIR "pxa2xx-fir"
-typedef struct PXA2xxFIrState PXA2xxFIrState;
-DECLARE_INSTANCE_CHECKER(PXA2xxFIrState, PXA2XX_FIR,
- TYPE_PXA2XX_FIR)
+OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxFIrState, PXA2XX_FIR)
typedef struct {
ARMCPU *cpu;
uint8_t bus_num;
PCIBus *primary_bus;
};
-typedef struct SMMUState SMMUState;
struct SMMUBaseClass {
/* <private> */
DeviceRealize parent_realize;
};
-typedef struct SMMUBaseClass SMMUBaseClass;
#define TYPE_ARM_SMMU "arm-smmu"
-DECLARE_OBJ_CHECKERS(SMMUState, SMMUBaseClass,
- ARM_SMMU, TYPE_ARM_SMMU)
+OBJECT_DECLARE_TYPE(SMMUState, SMMUBaseClass, ARM_SMMU)
/* Return the SMMUPciBus handle associated to a PCI bus number */
SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8_t bus_num);
qemu_irq irq[4];
QemuMutex mutex;
};
-typedef struct SMMUv3State SMMUv3State;
typedef enum {
SMMU_IRQ_EVTQ,
DeviceRealize parent_realize;
DeviceReset parent_reset;
};
-typedef struct SMMUv3Class SMMUv3Class;
#define TYPE_ARM_SMMUV3 "arm-smmuv3"
-DECLARE_OBJ_CHECKERS(SMMUv3State, SMMUv3Class,
- ARM_SMMUV3, TYPE_ARM_SMMUV3)
+OBJECT_DECLARE_TYPE(SMMUv3State, SMMUv3Class, ARM_SMMUV3)
#endif
#include "qom/object.h"
#define TYPE_STM32F205_SOC "stm32f205-soc"
-typedef struct STM32F205State STM32F205State;
-DECLARE_INSTANCE_CHECKER(STM32F205State, STM32F205_SOC,
- TYPE_STM32F205_SOC)
+OBJECT_DECLARE_SIMPLE_TYPE(STM32F205State, STM32F205_SOC)
#define STM_NUM_USARTS 6
#define STM_NUM_TIMERS 4
#include "qom/object.h"
#define TYPE_STM32F405_SOC "stm32f405-soc"
-typedef struct STM32F405State STM32F405State;
-DECLARE_INSTANCE_CHECKER(STM32F405State, STM32F405_SOC,
- TYPE_STM32F405_SOC)
+OBJECT_DECLARE_SIMPLE_TYPE(STM32F405State, STM32F405_SOC)
#define STM_NUM_USARTS 7
#define STM_NUM_TIMERS 4
bool kvm_no_adjvtime;
bool acpi_expose_flash;
};
-typedef struct VirtMachineClass VirtMachineClass;
struct VirtMachineState {
MachineState parent;
DeviceState *acpi_dev;
Notifier powerdown_notifier;
};
-typedef struct VirtMachineState VirtMachineState;
#define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM)
#define TYPE_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
-DECLARE_OBJ_CHECKERS(VirtMachineState, VirtMachineClass,
- VIRT_MACHINE, TYPE_VIRT_MACHINE)
+OBJECT_DECLARE_TYPE(VirtMachineState, VirtMachineClass, VIRT_MACHINE)
void virt_acpi_setup(VirtMachineState *vms);
bool virt_is_acpi_enabled(VirtMachineState *vms);
#include "qom/object.h"
#define TYPE_XLNX_VERSAL "xlnx-versal"
-typedef struct Versal Versal;
-DECLARE_INSTANCE_CHECKER(Versal, XLNX_VERSAL,
- TYPE_XLNX_VERSAL)
+OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
#define XLNX_VERSAL_NR_ACPUS 2
#define XLNX_VERSAL_NR_UARTS 2
#include "qom/object.h"
#define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
-typedef struct XlnxZynqMPState XlnxZynqMPState;
-DECLARE_INSTANCE_CHECKER(XlnxZynqMPState, XLNX_ZYNQMP,
- TYPE_XLNX_ZYNQMP)
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
#define XLNX_ZYNQMP_NUM_APU_CPUS 4
#define XLNX_ZYNQMP_NUM_RPU_CPUS 2
/* pflash_cfi01.c */
#define TYPE_PFLASH_CFI01 "cfi.pflash01"
-typedef struct PFlashCFI01 PFlashCFI01;
-DECLARE_INSTANCE_CHECKER(PFlashCFI01, PFLASH_CFI01,
- TYPE_PFLASH_CFI01)
+OBJECT_DECLARE_SIMPLE_TYPE(PFlashCFI01, PFLASH_CFI01)
PFlashCFI01 *pflash_cfi01_register(hwaddr base,
/* pflash_cfi02.c */
#define TYPE_PFLASH_CFI02 "cfi.pflash02"
-typedef struct PFlashCFI02 PFlashCFI02;
-DECLARE_INSTANCE_CHECKER(PFlashCFI02, PFLASH_CFI02,
- TYPE_PFLASH_CFI02)
+OBJECT_DECLARE_SIMPLE_TYPE(PFlashCFI02, PFLASH_CFI02)
PFlashCFI02 *pflash_cfi02_register(hwaddr base,
#define SWIM_MAX_FD 2
-typedef struct SWIMDrive SWIMDrive;
-typedef struct SWIMBus SWIMBus;
typedef struct SWIMCtrl SWIMCtrl;
#define TYPE_SWIM_DRIVE "swim-drive"
-DECLARE_INSTANCE_CHECKER(SWIMDrive, SWIM_DRIVE,
- TYPE_SWIM_DRIVE)
+OBJECT_DECLARE_SIMPLE_TYPE(SWIMDrive, SWIM_DRIVE)
struct SWIMDrive {
DeviceState qdev;
};
#define TYPE_SWIM_BUS "swim-bus"
-DECLARE_INSTANCE_CHECKER(SWIMBus, SWIM_BUS,
- TYPE_SWIM_BUS)
+OBJECT_DECLARE_SIMPLE_TYPE(SWIMBus, SWIM_BUS)
struct SWIMBus {
BusState bus;
};
#define TYPE_SWIM "swim"
-typedef struct Swim Swim;
-DECLARE_INSTANCE_CHECKER(Swim, SWIM,
- TYPE_SWIM)
+OBJECT_DECLARE_SIMPLE_TYPE(Swim, SWIM)
struct Swim {
SysBusDevice parent_obj;
#define TYPE_MACHINE "machine"
#undef MACHINE /* BSD defines it and QEMU does not use it */
-DECLARE_OBJ_CHECKERS(MachineState, MachineClass,
- MACHINE, TYPE_MACHINE)
+OBJECT_DECLARE_TYPE(MachineState, MachineClass, MACHINE)
extern MachineState *current_machine;
#define USART_CSRC_CSZ0 (1 << 1)
#define TYPE_AVR_USART "avr-usart"
-typedef struct AVRUsartState AVRUsartState;
-DECLARE_INSTANCE_CHECKER(AVRUsartState, AVR_USART,
- TYPE_AVR_USART)
+OBJECT_DECLARE_SIMPLE_TYPE(AVRUsartState, AVR_USART)
struct AVRUsartState {
/* <private> */
#include "qom/object.h"
#define TYPE_BCM2835_AUX "bcm2835-aux"
-typedef struct BCM2835AuxState BCM2835AuxState;
-DECLARE_INSTANCE_CHECKER(BCM2835AuxState, BCM2835_AUX,
- TYPE_BCM2835_AUX)
+OBJECT_DECLARE_SIMPLE_TYPE(BCM2835AuxState, BCM2835_AUX)
#define BCM2835_AUX_RX_FIFO_LEN 8
#define CADENCE_UART_R_MAX (0x48/4)
#define TYPE_CADENCE_UART "cadence_uart"
-typedef struct CadenceUARTState CadenceUARTState;
-DECLARE_INSTANCE_CHECKER(CadenceUARTState, CADENCE_UART,
- TYPE_CADENCE_UART)
+OBJECT_DECLARE_SIMPLE_TYPE(CadenceUARTState, CADENCE_UART)
struct CadenceUARTState {
/*< private >*/
#include "qom/object.h"
#define TYPE_CMSDK_APB_UART "cmsdk-apb-uart"
-typedef struct CMSDKAPBUART CMSDKAPBUART;
-DECLARE_INSTANCE_CHECKER(CMSDKAPBUART, CMSDK_APB_UART,
- TYPE_CMSDK_APB_UART)
+OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBUART, CMSDK_APB_UART)
struct CMSDKAPBUART {
/*< private >*/
#include "qom/object.h"
#define TYPE_DIGIC_UART "digic-uart"
-typedef struct DigicUartState DigicUartState;
-DECLARE_INSTANCE_CHECKER(DigicUartState, DIGIC_UART,
- TYPE_DIGIC_UART)
+OBJECT_DECLARE_SIMPLE_TYPE(DigicUartState, DIGIC_UART)
enum {
R_TX = 0x00,
#define TYPE_ESCC "escc"
#define ESCC_SIZE 4
-typedef struct ESCCState ESCCState;
-DECLARE_INSTANCE_CHECKER(ESCCState, ESCC,
- TYPE_ESCC)
+OBJECT_DECLARE_SIMPLE_TYPE(ESCCState, ESCC)
typedef enum {
escc_chn_a, escc_chn_b,
#define IBEX_UART_CLOCK 50000000 /* 50MHz clock */
#define TYPE_IBEX_UART "ibex-uart"
-typedef struct IbexUartState IbexUartState;
-DECLARE_INSTANCE_CHECKER(IbexUartState, IBEX_UART,
- TYPE_IBEX_UART)
+OBJECT_DECLARE_SIMPLE_TYPE(IbexUartState, IBEX_UART)
struct IbexUartState {
/* <private> */
#include "qom/object.h"
#define TYPE_IMX_SERIAL "imx.serial"
-typedef struct IMXSerialState IMXSerialState;
-DECLARE_INSTANCE_CHECKER(IMXSerialState, IMX_SERIAL,
- TYPE_IMX_SERIAL)
+OBJECT_DECLARE_SIMPLE_TYPE(IMXSerialState, IMX_SERIAL)
#define URXD_CHARRDY (1<<15) /* character read is valid */
#define URXD_ERR (1<<14) /* Character has error */
#define UART_SIZE 0x1000
#define TYPE_NRF51_UART "nrf51_soc.uart"
-typedef struct NRF51UARTState NRF51UARTState;
-DECLARE_INSTANCE_CHECKER(NRF51UARTState, NRF51_UART,
- TYPE_NRF51_UART)
+OBJECT_DECLARE_SIMPLE_TYPE(NRF51UARTState, NRF51_UART)
REG32(UART_STARTRX, 0x000)
REG32(UART_STOPRX, 0x004)
#include "qom/object.h"
#define TYPE_PL011 "pl011"
-typedef struct PL011State PL011State;
-DECLARE_INSTANCE_CHECKER(PL011State, PL011,
- TYPE_PL011)
+OBJECT_DECLARE_SIMPLE_TYPE(PL011State, PL011)
/* This shares the same struct (and cast macro) as the base pl011 device */
#define TYPE_PL011_LUMINARY "pl011_luminary"
uint8_t regshift;
uint8_t endianness;
};
-typedef struct SerialMM SerialMM;
struct SerialIO {
SysBusDevice parent;
SerialState serial;
};
-typedef struct SerialIO SerialIO;
extern const VMStateDescription vmstate_serial;
extern const MemoryRegionOps serial_io_ops;
void serial_set_frequency(SerialState *s, uint32_t frequency);
#define TYPE_SERIAL "serial"
-DECLARE_INSTANCE_CHECKER(SerialState, SERIAL,
- TYPE_SERIAL)
+OBJECT_DECLARE_SIMPLE_TYPE(SerialState, SERIAL)
#define TYPE_SERIAL_MM "serial-mm"
-DECLARE_INSTANCE_CHECKER(SerialMM, SERIAL_MM,
- TYPE_SERIAL_MM)
+OBJECT_DECLARE_SIMPLE_TYPE(SerialMM, SERIAL_MM)
#define TYPE_SERIAL_IO "serial-io"
-DECLARE_INSTANCE_CHECKER(SerialIO, SERIAL_IO,
- TYPE_SERIAL_IO)
+OBJECT_DECLARE_SIMPLE_TYPE(SerialIO, SERIAL_IO)
SerialMM *serial_mm_init(MemoryRegion *address_space,
hwaddr base, int regshift,
#include "chardev/char-fe.h"
#include "hw/sysbus.h"
+#include "qom/object.h"
enum {
SIFIVE_UART_TXFIFO = 0,
#define TYPE_SIFIVE_UART "riscv.sifive.uart"
-#define SIFIVE_UART(obj) \
- OBJECT_CHECK(SiFiveUARTState, (obj), TYPE_SIFIVE_UART)
+typedef struct SiFiveUARTState SiFiveUARTState;
+DECLARE_INSTANCE_CHECKER(SiFiveUARTState, SIFIVE_UART,
+ TYPE_SIFIVE_UART)
-typedef struct SiFiveUARTState {
+struct SiFiveUARTState {
/*< private >*/
SysBusDevice parent_obj;
uint32_t txctrl;
uint32_t rxctrl;
uint32_t div;
-} SiFiveUARTState;
+};
SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base,
Chardev *chr, qemu_irq irq);
#define USART_CR1_RE (1 << 2)
#define TYPE_STM32F2XX_USART "stm32f2xx-usart"
-typedef struct STM32F2XXUsartState STM32F2XXUsartState;
-DECLARE_INSTANCE_CHECKER(STM32F2XXUsartState, STM32F2XX_USART,
- TYPE_STM32F2XX_USART)
+OBJECT_DECLARE_SIMPLE_TYPE(STM32F2XXUsartState, STM32F2XX_USART)
struct STM32F2XXUsartState {
/* <private> */
#include "qemu/queue.h"
#define TYPE_CLOCK "clock"
-typedef struct Clock Clock;
-DECLARE_INSTANCE_CHECKER(Clock, CLOCK,
- TYPE_CLOCK)
+OBJECT_DECLARE_SIMPLE_TYPE(Clock, CLOCK)
typedef void ClockCallback(void *opaque);
bool data_be;
bool set_pc;
};
-typedef struct GenericLoaderState GenericLoaderState;
#define TYPE_GENERIC_LOADER "loader"
-DECLARE_INSTANCE_CHECKER(GenericLoaderState, GENERIC_LOADER,
- TYPE_GENERIC_LOADER)
+OBJECT_DECLARE_SIMPLE_TYPE(GenericLoaderState, GENERIC_LOADER)
#endif
#define MAX_SPLIT_LINES 16
-typedef struct SplitIRQ SplitIRQ;
-DECLARE_INSTANCE_CHECKER(SplitIRQ, SPLIT_IRQ,
- TYPE_SPLIT_IRQ)
+OBJECT_DECLARE_SIMPLE_TYPE(SplitIRQ, SPLIT_IRQ)
struct SplitIRQ {
DeviceState parent_obj;
/* A15MP private memory region. */
#define TYPE_A15MPCORE_PRIV "a15mpcore_priv"
-typedef struct A15MPPrivState A15MPPrivState;
-DECLARE_INSTANCE_CHECKER(A15MPPrivState, A15MPCORE_PRIV,
- TYPE_A15MPCORE_PRIV)
+OBJECT_DECLARE_SIMPLE_TYPE(A15MPPrivState, A15MPCORE_PRIV)
struct A15MPPrivState {
/*< private >*/
#include "qom/object.h"
#define TYPE_A9MPCORE_PRIV "a9mpcore_priv"
-typedef struct A9MPPrivState A9MPPrivState;
-DECLARE_INSTANCE_CHECKER(A9MPPrivState, A9MPCORE_PRIV,
- TYPE_A9MPCORE_PRIV)
+OBJECT_DECLARE_SIMPLE_TYPE(A9MPPrivState, A9MPCORE_PRIV)
struct A9MPPrivState {
/*< private >*/
#include "qom/object.h"
#define TYPE_ARM11MPCORE_PRIV "arm11mpcore_priv"
-typedef struct ARM11MPCorePriveState ARM11MPCorePriveState;
-DECLARE_INSTANCE_CHECKER(ARM11MPCorePriveState, ARM11MPCORE_PRIV,
- TYPE_ARM11MPCORE_PRIV)
+OBJECT_DECLARE_SIMPLE_TYPE(ARM11MPCorePriveState, ARM11MPCORE_PRIV)
struct ARM11MPCorePriveState {
SysBusDevice parent_obj;
*/
#define TYPE_CPU_CLUSTER "cpu-cluster"
-typedef struct CPUClusterState CPUClusterState;
-DECLARE_INSTANCE_CHECKER(CPUClusterState, CPU_CLUSTER,
- TYPE_CPU_CLUSTER)
+OBJECT_DECLARE_SIMPLE_TYPE(CPUClusterState, CPU_CLUSTER)
/*
* This limit is imposed by TCG, which puts the cluster ID into an
#define TYPE_CPU_CORE "cpu-core"
-typedef struct CPUCore CPUCore;
-DECLARE_INSTANCE_CHECKER(CPUCore, CPU_CORE,
- TYPE_CPU_CORE)
+OBJECT_DECLARE_SIMPLE_TYPE(CPUCore, CPU_CORE)
struct CPUCore {
/*< private >*/
#include "qom/object.h"
#define TYPE_BCM2835_FB "bcm2835-fb"
-typedef struct BCM2835FBState BCM2835FBState;
-DECLARE_INSTANCE_CHECKER(BCM2835FBState, BCM2835_FB,
- TYPE_BCM2835_FB)
+OBJECT_DECLARE_SIMPLE_TYPE(BCM2835FBState, BCM2835_FB)
/*
* Configuration information about the fb which the guest can program
#define DPCD_H
#include "qom/object.h"
-typedef struct DPCDState DPCDState;
#define TYPE_DPCD "dpcd"
-DECLARE_INSTANCE_CHECKER(DPCDState, DPCD,
- TYPE_DPCD)
+OBJECT_DECLARE_SIMPLE_TYPE(DPCDState, DPCD)
/* DCPD Revision. */
#define DPCD_REVISION 0x00
uint8_t edid_blob[128];
};
-typedef struct I2CDDCState I2CDDCState;
#define TYPE_I2CDDC "i2c-ddc"
-DECLARE_INSTANCE_CHECKER(I2CDDCState, I2CDDC,
- TYPE_I2CDDC)
+OBJECT_DECLARE_SIMPLE_TYPE(I2CDDCState, I2CDDC)
#endif /* I2C_DDC_H */
} MacfbState;
#define TYPE_MACFB "sysbus-macfb"
-typedef struct MacfbSysBusState MacfbSysBusState;
-DECLARE_INSTANCE_CHECKER(MacfbSysBusState, MACFB,
- TYPE_MACFB)
+OBJECT_DECLARE_SIMPLE_TYPE(MacfbSysBusState, MACFB)
struct MacfbSysBusState {
SysBusDevice busdev;
};
#define TYPE_NUBUS_MACFB "nubus-macfb"
-typedef struct MacfbNubusDeviceClass MacfbNubusDeviceClass;
-typedef struct MacfbNubusState MacfbNubusState;
-DECLARE_OBJ_CHECKERS(MacfbNubusState, MacfbNubusDeviceClass,
- NUBUS_MACFB, TYPE_NUBUS_MACFB)
+OBJECT_DECLARE_TYPE(MacfbNubusState, MacfbNubusDeviceClass, NUBUS_MACFB)
struct MacfbNubusDeviceClass {
DeviceClass parent_class;
DPCDState *dpcd;
I2CDDCState *edid;
};
-typedef struct XlnxDPState XlnxDPState;
#define TYPE_XLNX_DP "xlnx.v-dp"
-DECLARE_INSTANCE_CHECKER(XlnxDPState, XLNX_DP,
- TYPE_XLNX_DP)
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxDPState, XLNX_DP)
#endif
} BCM2835DMAChan;
#define TYPE_BCM2835_DMA "bcm2835-dma"
-typedef struct BCM2835DMAState BCM2835DMAState;
-DECLARE_INSTANCE_CHECKER(BCM2835DMAState, BCM2835_DMA,
- TYPE_BCM2835_DMA)
+OBJECT_DECLARE_SIMPLE_TYPE(BCM2835DMAState, BCM2835_DMA)
#define BCM2835_DMA_NCHANS 16
#include "qom/object.h"
#define TYPE_I8257 "i8257"
-typedef struct I8257State I8257State;
-DECLARE_INSTANCE_CHECKER(I8257State, I8257,
- TYPE_I8257)
+OBJECT_DECLARE_SIMPLE_TYPE(I8257State, I8257)
typedef struct I8257Regs {
int now[2];
#define TYPE_PL080 "pl080"
#define TYPE_PL081 "pl081"
-typedef struct PL080State PL080State;
-DECLARE_INSTANCE_CHECKER(PL080State, PL080,
- TYPE_PL080)
+OBJECT_DECLARE_SIMPLE_TYPE(PL080State, PL080)
struct PL080State {
SysBusDevice parent_obj;
to model write only mode. */
uint8_t buf[2048];
};
-typedef struct XlnxZDMA XlnxZDMA;
#define TYPE_XLNX_ZDMA "xlnx.zdma"
-DECLARE_INSTANCE_CHECKER(XlnxZDMA, XLNX_ZDMA,
- TYPE_XLNX_ZDMA)
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxZDMA, XLNX_ZDMA)
#endif /* XLNX_ZDMA_H */
#define TYPE_XLNX_ZYNQ_DEVCFG "xlnx.ps7-dev-cfg"
-typedef struct XlnxZynqDevcfg XlnxZynqDevcfg;
-DECLARE_INSTANCE_CHECKER(XlnxZynqDevcfg, XLNX_ZYNQ_DEVCFG,
- TYPE_XLNX_ZYNQ_DEVCFG)
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqDevcfg, XLNX_ZYNQ_DEVCFG)
#define XLNX_ZYNQ_DEVCFG_R_MAX (0x100 / 4)
qemu_irq irq;
};
-typedef struct XlnxDPDMAState XlnxDPDMAState;
#define TYPE_XLNX_DPDMA "xlnx.dpdma"
-DECLARE_INSTANCE_CHECKER(XlnxDPDMAState, XLNX_DPDMA,
- TYPE_XLNX_DPDMA)
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxDPDMAState, XLNX_DPDMA)
/*
* xlnx_dpdma_start_operation: Start the operation on the specified channel. The
#include "qom/object.h"
#define TYPE_ASPEED_GPIO "aspeed.gpio"
-typedef struct AspeedGPIOClass AspeedGPIOClass;
-typedef struct AspeedGPIOState AspeedGPIOState;
-DECLARE_OBJ_CHECKERS(AspeedGPIOState, AspeedGPIOClass,
- ASPEED_GPIO, TYPE_ASPEED_GPIO)
+OBJECT_DECLARE_TYPE(AspeedGPIOState, AspeedGPIOClass, ASPEED_GPIO)
#define ASPEED_GPIO_MAX_NR_SETS 8
#define ASPEED_REGS_PER_BANK 14
uint8_t sd_fsel;
qemu_irq out[54];
};
-typedef struct BCM2835GpioState BCM2835GpioState;
#define TYPE_BCM2835_GPIO "bcm2835_gpio"
-DECLARE_INSTANCE_CHECKER(BCM2835GpioState, BCM2835_GPIO,
- TYPE_BCM2835_GPIO)
+OBJECT_DECLARE_SIMPLE_TYPE(BCM2835GpioState, BCM2835_GPIO)
#endif
#include "qom/object.h"
#define TYPE_IMX_GPIO "imx.gpio"
-typedef struct IMXGPIOState IMXGPIOState;
-DECLARE_INSTANCE_CHECKER(IMXGPIOState, IMX_GPIO,
- TYPE_IMX_GPIO)
+OBJECT_DECLARE_SIMPLE_TYPE(IMXGPIOState, IMX_GPIO)
#define IMX_GPIO_MEM_SIZE 0x20
#include "hw/sysbus.h"
#include "qom/object.h"
#define TYPE_NRF51_GPIO "nrf51_soc.gpio"
-typedef struct NRF51GPIOState NRF51GPIOState;
-DECLARE_INSTANCE_CHECKER(NRF51GPIOState, NRF51_GPIO,
- TYPE_NRF51_GPIO)
+OBJECT_DECLARE_SIMPLE_TYPE(NRF51GPIOState, NRF51_GPIO)
#define NRF51_GPIO_PINS 32
#define SIFIVE_GPIO_H
#include "hw/sysbus.h"
+#include "qom/object.h"
#define TYPE_SIFIVE_GPIO "sifive_soc.gpio"
-#define SIFIVE_GPIO(obj) OBJECT_CHECK(SIFIVEGPIOState, (obj), TYPE_SIFIVE_GPIO)
+typedef struct SIFIVEGPIOState SIFIVEGPIOState;
+DECLARE_INSTANCE_CHECKER(SIFIVEGPIOState, SIFIVE_GPIO,
+ TYPE_SIFIVE_GPIO)
#define SIFIVE_GPIO_PINS 32
#define SIFIVE_GPIO_REG_IOF_SEL 0x03C
#define SIFIVE_GPIO_REG_OUT_XOR 0x040
-typedef struct SIFIVEGPIOState {
+struct SIFIVEGPIOState {
SysBusDevice parent_obj;
MemoryRegion mmio;
/* config */
uint32_t ngpio;
-} SIFIVEGPIOState;
+};
#endif /* SIFIVE_GPIO_H */
VMBus *bus;
};
-typedef struct VMBusBridge VMBusBridge;
-DECLARE_INSTANCE_CHECKER(VMBusBridge, VMBUS_BRIDGE,
- TYPE_VMBUS_BRIDGE)
+OBJECT_DECLARE_SIMPLE_TYPE(VMBusBridge, VMBUS_BRIDGE)
static inline VMBusBridge *vmbus_bridge_find(void)
{
#define TYPE_VMBUS_DEVICE "vmbus-dev"
OBJECT_DECLARE_TYPE(VMBusDevice, VMBusDeviceClass,
- vmbus_device, VMBUS_DEVICE)
+ VMBUS_DEVICE)
#define TYPE_VMBUS "vmbus"
-typedef struct VMBus VMBus;
-DECLARE_INSTANCE_CHECKER(VMBus, VMBUS,
- TYPE_VMBUS)
+OBJECT_DECLARE_SIMPLE_TYPE(VMBus, VMBUS)
/*
* Object wrapping a GPADL -- GPA Descriptor List -- an array of guest physical
#define TYPE_ASPEED_2400_I2C TYPE_ASPEED_I2C "-ast2400"
#define TYPE_ASPEED_2500_I2C TYPE_ASPEED_I2C "-ast2500"
#define TYPE_ASPEED_2600_I2C TYPE_ASPEED_I2C "-ast2600"
-typedef struct AspeedI2CClass AspeedI2CClass;
-typedef struct AspeedI2CState AspeedI2CState;
-DECLARE_OBJ_CHECKERS(AspeedI2CState, AspeedI2CClass,
- ASPEED_I2C, TYPE_ASPEED_I2C)
+OBJECT_DECLARE_TYPE(AspeedI2CState, AspeedI2CClass, ASPEED_I2C)
#define ASPEED_I2C_NR_BUSSES 16
#define ASPEED_I2C_MAX_POOL_SIZE 0x800
#define TYPE_I2C_SLAVE "i2c-slave"
OBJECT_DECLARE_TYPE(I2CSlave, I2CSlaveClass,
- i2c_slave, I2C_SLAVE)
+ I2C_SLAVE)
struct I2CSlaveClass {
DeviceClass parent_class;
};
#define TYPE_I2C_BUS "i2c-bus"
-DECLARE_INSTANCE_CHECKER(I2CBus, I2C_BUS,
- TYPE_I2C_BUS)
+OBJECT_DECLARE_SIMPLE_TYPE(I2CBus, I2C_BUS)
typedef struct I2CNode I2CNode;
#include "qom/object.h"
#define TYPE_IMX_I2C "imx.i2c"
-typedef struct IMXI2CState IMXI2CState;
-DECLARE_INSTANCE_CHECKER(IMXI2CState, IMX_I2C,
- TYPE_IMX_I2C)
+OBJECT_DECLARE_SIMPLE_TYPE(IMXI2CState, IMX_I2C)
#define IMX_I2C_MEM_SIZE 0x14
#define NRF51_TWI_REG_ADDRESS 0x588
#define TYPE_MICROBIT_I2C "microbit.i2c"
-typedef struct MicrobitI2CState MicrobitI2CState;
-DECLARE_INSTANCE_CHECKER(MicrobitI2CState, MICROBIT_I2C,
- TYPE_MICROBIT_I2C)
+OBJECT_DECLARE_SIMPLE_TYPE(MicrobitI2CState, MICROBIT_I2C)
#define MICROBIT_I2C_NREGS (NRF51_PERIPHERAL_SIZE / sizeof(uint32_t))
#include "qom/object.h"
#define TYPE_PPC4xx_I2C "ppc4xx-i2c"
-typedef struct PPC4xxI2CState PPC4xxI2CState;
-DECLARE_INSTANCE_CHECKER(PPC4xxI2CState, PPC4xx_I2C,
- TYPE_PPC4xx_I2C)
+OBJECT_DECLARE_SIMPLE_TYPE(PPC4xxI2CState, PPC4xx_I2C)
struct PPC4xxI2CState {
/*< private >*/
#define TYPE_SMBUS_DEVICE "smbus-device"
OBJECT_DECLARE_TYPE(SMBusDevice, SMBusDeviceClass,
- smbus_device, SMBUS_DEVICE)
+ SMBUS_DEVICE)
struct SMBusDeviceClass {
#define ICH9_CC_SIZE (16 * 1024) /* 16KB. Chipset configuration registers */
#define TYPE_ICH9_LPC_DEVICE "ICH9-LPC"
-typedef struct ICH9LPCState ICH9LPCState;
-DECLARE_INSTANCE_CHECKER(ICH9LPCState, ICH9_LPC_DEVICE,
- TYPE_ICH9_LPC_DEVICE)
+OBJECT_DECLARE_SIMPLE_TYPE(ICH9LPCState, ICH9_LPC_DEVICE)
struct ICH9LPCState {
/* ICH9 LPC PCI to ISA bridge */
#include "qom/object.h"
#define TYPE_INTEL_IOMMU_DEVICE "intel-iommu"
-typedef struct IntelIOMMUState IntelIOMMUState;
-DECLARE_INSTANCE_CHECKER(IntelIOMMUState, INTEL_IOMMU_DEVICE,
- TYPE_INTEL_IOMMU_DEVICE)
+OBJECT_DECLARE_SIMPLE_TYPE(IntelIOMMUState, INTEL_IOMMU_DEVICE)
#define TYPE_INTEL_IOMMU_MEMORY_REGION "intel-iommu-iommu-memory-region"
#define IOAPIC_VER_ENTRIES_SHIFT 16
-typedef struct IOAPICCommonState IOAPICCommonState;
#define TYPE_IOAPIC_COMMON "ioapic-common"
-typedef struct IOAPICCommonClass IOAPICCommonClass;
-DECLARE_OBJ_CHECKERS(IOAPICCommonState, IOAPICCommonClass,
- IOAPIC_COMMON, TYPE_IOAPIC_COMMON)
+OBJECT_DECLARE_TYPE(IOAPICCommonState, IOAPICCommonClass, IOAPIC_COMMON)
struct IOAPICCommonClass {
SysBusDeviceClass parent_class;
HotplugHandler *(*orig_hotplug_handler)(MachineState *machine,
DeviceState *dev);
};
-typedef struct MicrovmMachineClass MicrovmMachineClass;
struct MicrovmMachineState {
X86MachineState parent;
Notifier machine_done;
Notifier powerdown_req;
};
-typedef struct MicrovmMachineState MicrovmMachineState;
#define TYPE_MICROVM_MACHINE MACHINE_TYPE_NAME("microvm")
-DECLARE_OBJ_CHECKERS(MicrovmMachineState, MicrovmMachineClass,
- MICROVM_MACHINE, TYPE_MICROVM_MACHINE)
+OBJECT_DECLARE_TYPE(MicrovmMachineState, MicrovmMachineClass, MICROVM_MACHINE)
#endif
/* use PVH to load kernels that support this feature */
bool pvh_enabled;
};
-typedef struct PCMachineClass PCMachineClass;
#define TYPE_PC_MACHINE "generic-pc-machine"
-DECLARE_OBJ_CHECKERS(PCMachineState, PCMachineClass,
- PC_MACHINE, TYPE_PC_MACHINE)
+OBJECT_DECLARE_TYPE(PCMachineState, PCMachineClass, PC_MACHINE)
/* ioapic.c */
#include "hw/isa/isa.h"
#define TYPE_VMPORT "vmport"
-typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address);
+typedef uint32_t VMPortReadFunc(void *opaque, uint32_t address);
typedef enum {
VMPORT_CMD_GETVERSION = 10,
#include "qom/object.h"
#define TYPE_X86_IOMMU_DEVICE ("x86-iommu")
-typedef struct X86IOMMUClass X86IOMMUClass;
-typedef struct X86IOMMUState X86IOMMUState;
-DECLARE_OBJ_CHECKERS(X86IOMMUState, X86IOMMUClass,
- X86_IOMMU_DEVICE, TYPE_X86_IOMMU_DEVICE)
+OBJECT_DECLARE_TYPE(X86IOMMUState, X86IOMMUClass, X86_IOMMU_DEVICE)
#define X86_IOMMU_SID_INVALID (0xffff)
/* Enables contiguous-apic-ID mode */
bool compat_apic_id_mode;
};
-typedef struct X86MachineClass X86MachineClass;
struct X86MachineState {
/*< private >*/
*/
AddressSpace *ioapic_as;
};
-typedef struct X86MachineState X86MachineState;
#define X86_MACHINE_SMM "smm"
#define X86_MACHINE_ACPI "acpi"
#define TYPE_X86_MACHINE MACHINE_TYPE_NAME("x86")
-DECLARE_OBJ_CHECKERS(X86MachineState, X86MachineClass,
- X86_MACHINE, TYPE_X86_MACHINE)
+OBJECT_DECLARE_TYPE(X86MachineState, X86MachineClass, X86_MACHINE)
void init_topo_info(X86CPUTopoInfo *topo_info, const X86MachineState *x86ms);
AddressSpace *as;
} AHCIState;
-typedef struct AHCIPCIState AHCIPCIState;
#define TYPE_ICH9_AHCI "ich9-ahci"
-DECLARE_INSTANCE_CHECKER(AHCIPCIState, ICH9_AHCI,
- TYPE_ICH9_AHCI)
+OBJECT_DECLARE_SIMPLE_TYPE(AHCIPCIState, ICH9_AHCI)
int32_t ahci_get_num_ports(PCIDevice *dev);
void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd);
#define TYPE_SYSBUS_AHCI "sysbus-ahci"
-typedef struct SysbusAHCIState SysbusAHCIState;
-DECLARE_INSTANCE_CHECKER(SysbusAHCIState, SYSBUS_AHCI,
- TYPE_SYSBUS_AHCI)
+OBJECT_DECLARE_SIMPLE_TYPE(SysbusAHCIState, SYSBUS_AHCI)
struct SysbusAHCIState {
/*< private >*/
};
#define TYPE_ALLWINNER_AHCI "allwinner-ahci"
-typedef struct AllwinnerAHCIState AllwinnerAHCIState;
-DECLARE_INSTANCE_CHECKER(AllwinnerAHCIState, ALLWINNER_AHCI,
- TYPE_ALLWINNER_AHCI)
+OBJECT_DECLARE_SIMPLE_TYPE(AllwinnerAHCIState, ALLWINNER_AHCI)
#define ALLWINNER_AHCI_MMIO_OFF 0x80
#define ALLWINNER_AHCI_MMIO_SIZE 0x80
#define USE_DMA_CDROM
#include "qom/object.h"
-typedef struct IDEBus IDEBus;
typedef struct IDEDevice IDEDevice;
typedef struct IDEState IDEState;
typedef struct IDEDMA IDEDMA;
typedef struct IDEDMAOps IDEDMAOps;
#define TYPE_IDE_BUS "IDE"
-DECLARE_INSTANCE_CHECKER(IDEBus, IDE_BUS,
- TYPE_IDE_BUS)
+OBJECT_DECLARE_SIMPLE_TYPE(IDEBus, IDE_BUS)
#define MAX_IDE_DEVS 2
};
#define TYPE_IDE_DEVICE "ide-device"
-typedef struct IDEDeviceClass IDEDeviceClass;
-DECLARE_OBJ_CHECKERS(IDEDevice, IDEDeviceClass,
- IDE_DEVICE, TYPE_IDE_DEVICE)
+OBJECT_DECLARE_TYPE(IDEDevice, IDEDeviceClass, IDE_DEVICE)
struct IDEDeviceClass {
DeviceClass parent_class;
} BMDMAState;
#define TYPE_PCI_IDE "pci-ide"
-typedef struct PCIIDEState PCIIDEState;
-DECLARE_INSTANCE_CHECKER(PCIIDEState, PCI_IDE,
- TYPE_PCI_IDE)
+OBJECT_DECLARE_SIMPLE_TYPE(PCIIDEState, PCI_IDE)
struct PCIIDEState {
/*< private >*/
#define ADB_MAX_OUT_LEN 16
-typedef struct ADBBusState ADBBusState;
typedef struct ADBDevice ADBDevice;
/* buf = NULL means polling */
typedef bool ADBDeviceHasData(ADBDevice *d);
#define TYPE_ADB_DEVICE "adb-device"
-typedef struct ADBDeviceClass ADBDeviceClass;
-DECLARE_OBJ_CHECKERS(ADBDevice, ADBDeviceClass,
- ADB_DEVICE, TYPE_ADB_DEVICE)
+OBJECT_DECLARE_TYPE(ADBDevice, ADBDeviceClass, ADB_DEVICE)
struct ADBDevice {
/*< private >*/
};
#define TYPE_ADB_BUS "apple-desktop-bus"
-DECLARE_INSTANCE_CHECKER(ADBBusState, ADB_BUS,
- TYPE_ADB_BUS)
+OBJECT_DECLARE_SIMPLE_TYPE(ADBBusState, ADB_BUS)
#define ADB_STATUS_BUSTIMEOUT 0x1
#define ADB_STATUS_POLLREPLY 0x2
#include "qom/object.h"
#define TYPE_I8042 "i8042"
-typedef struct ISAKBDState ISAKBDState;
-DECLARE_INSTANCE_CHECKER(ISAKBDState, I8042,
- TYPE_I8042)
+OBJECT_DECLARE_SIMPLE_TYPE(ISAKBDState, I8042)
#define I8042_A20_LINE "a20"
#include "qom/object.h"
#define TYPE_AW_A10_PIC "allwinner-a10-pic"
-typedef struct AwA10PICState AwA10PICState;
-DECLARE_INSTANCE_CHECKER(AwA10PICState, AW_A10_PIC,
- TYPE_AW_A10_PIC)
+OBJECT_DECLARE_SIMPLE_TYPE(AwA10PICState, AW_A10_PIC)
#define AW_A10_PIC_VECTOR 0
#define AW_A10_PIC_BASE_ADDR 4
#include "qom/object.h"
#define TYPE_ASPEED_VIC "aspeed.vic"
-typedef struct AspeedVICState AspeedVICState;
-DECLARE_INSTANCE_CHECKER(AspeedVICState, ASPEED_VIC,
- TYPE_ASPEED_VIC)
+OBJECT_DECLARE_SIMPLE_TYPE(AspeedVICState, ASPEED_VIC)
#define ASPEED_VIC_NR_IRQS 51
#include "qom/object.h"
#define TYPE_BCM2835_IC "bcm2835-ic"
-typedef struct BCM2835ICState BCM2835ICState;
-DECLARE_INSTANCE_CHECKER(BCM2835ICState, BCM2835_IC,
- TYPE_BCM2835_IC)
+OBJECT_DECLARE_SIMPLE_TYPE(BCM2835ICState, BCM2835_IC)
#define BCM2835_IC_GPU_IRQ "gpu-irq"
#define BCM2835_IC_ARM_IRQ "arm-irq"
#define BCM2836_MBPERCORE 4
#define TYPE_BCM2836_CONTROL "bcm2836-control"
-typedef struct BCM2836ControlState BCM2836ControlState;
-DECLARE_INSTANCE_CHECKER(BCM2836ControlState, BCM2836_CONTROL,
- TYPE_BCM2836_CONTROL)
+OBJECT_DECLARE_SIMPLE_TYPE(BCM2836ControlState, BCM2836_CONTROL)
struct BCM2836ControlState {
/*< private >*/
#include "qom/object.h"
#define TYPE_HEATHROW "heathrow"
-typedef struct HeathrowState HeathrowState;
-DECLARE_INSTANCE_CHECKER(HeathrowState, HEATHROW,
- TYPE_HEATHROW)
+OBJECT_DECLARE_SIMPLE_TYPE(HeathrowState, HEATHROW)
typedef struct HeathrowPICState {
uint32_t events;
#include "qom/object.h"
#define TYPE_IBEX_PLIC "ibex-plic"
-typedef struct IbexPlicState IbexPlicState;
-DECLARE_INSTANCE_CHECKER(IbexPlicState, IBEX_PLIC,
- TYPE_IBEX_PLIC)
+OBJECT_DECLARE_SIMPLE_TYPE(IbexPlicState, IBEX_PLIC)
struct IbexPlicState {
/*< private >*/
#include "qom/object.h"
#define TYPE_IMX_AVIC "imx.avic"
-typedef struct IMXAVICState IMXAVICState;
-DECLARE_INSTANCE_CHECKER(IMXAVICState, IMX_AVIC,
- TYPE_IMX_AVIC)
+OBJECT_DECLARE_SIMPLE_TYPE(IMXAVICState, IMX_AVIC)
#define IMX_AVIC_NUM_IRQS 64
MemoryRegion iomem;
uint32_t regs[GPC_NUM];
};
-typedef struct IMXGPCv2State IMXGPCv2State;
#define TYPE_IMX_GPCV2 "imx-gpcv2"
-DECLARE_INSTANCE_CHECKER(IMXGPCv2State, IMX_GPCV2,
- TYPE_IMX_GPCV2)
+OBJECT_DECLARE_SIMPLE_TYPE(IMXGPCv2State, IMX_GPCV2)
#endif /* IMX_GPCV2_H */
#define GIC_LOCAL_INT_WD 0 /* GIC watchdog */
#define TYPE_MIPS_GIC "mips-gic"
-typedef struct MIPSGICState MIPSGICState;
-DECLARE_INSTANCE_CHECKER(MIPSGICState, MIPS_GIC,
- TYPE_MIPS_GIC)
+OBJECT_DECLARE_SIMPLE_TYPE(MIPSGICState, MIPS_GIC)
/* Support up to 32 VPs and 256 IRQs */
#define GIC_MAX_VPS 32
#include "qom/object.h"
#define TYPE_REALVIEW_GIC "realview_gic"
-typedef struct RealViewGICState RealViewGICState;
-DECLARE_INSTANCE_CHECKER(RealViewGICState, REALVIEW_GIC,
- TYPE_REALVIEW_GIC)
+OBJECT_DECLARE_SIMPLE_TYPE(RealViewGICState, REALVIEW_GIC)
struct RealViewGICState {
SysBusDevice parent_obj;
qemu_irq _fir;
qemu_irq _swi;
};
-typedef struct RXICUState RXICUState;
#define TYPE_RX_ICU "rx-icu"
-DECLARE_INSTANCE_CHECKER(RXICUState, RX_ICU,
- TYPE_RX_ICU)
+OBJECT_DECLARE_SIMPLE_TYPE(RXICUState, RX_ICU)
#endif /* RX_ICU_H */
#define TYPE_XLNX_PMU_IO_INTC "xlnx.pmu_io_intc"
-typedef struct XlnxPMUIOIntc XlnxPMUIOIntc;
-DECLARE_INSTANCE_CHECKER(XlnxPMUIOIntc, XLNX_PMU_IO_INTC,
- TYPE_XLNX_PMU_IO_INTC)
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxPMUIOIntc, XLNX_PMU_IO_INTC)
/* This is R_PIT3_CONTROL + 1 */
#define XLNXPMUIOINTC_R_MAX (0x78 + 1)
#define TYPE_XLNX_ZYNQMP_IPI "xlnx.zynqmp_ipi"
-typedef struct XlnxZynqMPIPI XlnxZynqMPIPI;
-DECLARE_INSTANCE_CHECKER(XlnxZynqMPIPI, XLNX_ZYNQMP_IPI,
- TYPE_XLNX_ZYNQMP_IPI)
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPIPI, XLNX_ZYNQMP_IPI)
/* This is R_IPI_IDR + 1 */
#define R_XLNX_ZYNQMP_IPI_MAX ((0x1c / 4) + 1)
#include "hw/qdev-core.h"
#include "qom/object.h"
-typedef struct IPackBus IPackBus;
#define TYPE_IPACK_BUS "IndustryPack"
-DECLARE_INSTANCE_CHECKER(IPackBus, IPACK_BUS,
- TYPE_IPACK_BUS)
+OBJECT_DECLARE_SIMPLE_TYPE(IPackBus, IPACK_BUS)
struct IPackBus {
/*< private >*/
#define TYPE_IPACK_DEVICE "ipack-device"
OBJECT_DECLARE_TYPE(IPackDevice, IPackDeviceClass,
- ipack_device, IPACK_DEVICE)
+ IPACK_DEVICE)
struct IPackDeviceClass {
/*< private >*/
*/
#define TYPE_IPMI_BMC "ipmi-bmc"
OBJECT_DECLARE_TYPE(IPMIBmc, IPMIBmcClass,
- ipmi_bmc, IPMI_BMC)
+ IPMI_BMC)
struct IPMIBmc {
DeviceState parent;
void ipmi_bmc_gen_event(IPMIBmc *b, uint8_t *evt, bool log);
#define TYPE_IPMI_BMC_SIMULATOR "ipmi-bmc-sim"
-typedef struct IPMIBmcSim IPMIBmcSim;
-DECLARE_INSTANCE_CHECKER(IPMIBmcSim, IPMI_BMC_SIMULATOR,
- TYPE_IPMI_BMC_SIMULATOR)
+OBJECT_DECLARE_SIMPLE_TYPE(IPMIBmcSim, IPMI_BMC_SIMULATOR)
typedef struct RspBuffer {
#include "hw/intc/i8259.h"
#include "qom/object.h"
-typedef struct PICCommonState PICCommonState;
#define TYPE_PIC_COMMON "pic-common"
-typedef struct PICCommonClass PICCommonClass;
-DECLARE_OBJ_CHECKERS(PICCommonState, PICCommonClass,
- PIC_COMMON, TYPE_PIC_COMMON)
+OBJECT_DECLARE_TYPE(PICCommonState, PICCommonClass, PIC_COMMON)
struct PICCommonClass {
ISADeviceClass parent_class;
#define ISA_NUM_IRQS 16
#define TYPE_ISA_DEVICE "isa-device"
-typedef struct ISADeviceClass ISADeviceClass;
-DECLARE_OBJ_CHECKERS(ISADevice, ISADeviceClass,
- ISA_DEVICE, TYPE_ISA_DEVICE)
+OBJECT_DECLARE_TYPE(ISADevice, ISADeviceClass, ISA_DEVICE)
#define TYPE_ISA_BUS "ISA"
-DECLARE_INSTANCE_CHECKER(ISABus, ISA_BUS,
- TYPE_ISA_BUS)
+OBJECT_DECLARE_SIMPLE_TYPE(ISABus, ISA_BUS)
#define TYPE_APPLE_SMC "isa-applesmc"
#define APPLESMC_MAX_DATA_LENGTH 32
#define TYPE_PC87312 "pc87312"
-typedef struct PC87312State PC87312State;
-DECLARE_INSTANCE_CHECKER(PC87312State, PC87312,
- TYPE_PC87312)
+OBJECT_DECLARE_SIMPLE_TYPE(PC87312State, PC87312)
struct PC87312State {
/*< private >*/
#include "qom/object.h"
#define TYPE_MCF_FEC_NET "mcf-fec"
-typedef struct mcf_fec_state mcf_fec_state;
-DECLARE_INSTANCE_CHECKER(mcf_fec_state, MCF_FEC_NET,
- TYPE_MCF_FEC_NET)
+OBJECT_DECLARE_SIMPLE_TYPE(mcf_fec_state, MCF_FEC_NET)
#define FEC_NUM_IRQ 13
#define MIN_NAMESPACE_LABEL_SIZE (128UL << 10)
#define TYPE_NVDIMM "nvdimm"
-typedef struct NVDIMMClass NVDIMMClass;
-typedef struct NVDIMMDevice NVDIMMDevice;
-DECLARE_OBJ_CHECKERS(NVDIMMDevice, NVDIMMClass,
- NVDIMM, TYPE_NVDIMM)
+OBJECT_DECLARE_TYPE(NVDIMMDevice, NVDIMMClass, NVDIMM)
#define NVDIMM_LABEL_SIZE_PROP "label-size"
#define NVDIMM_UUID_PROP "uuid"
#define TYPE_PC_DIMM "pc-dimm"
OBJECT_DECLARE_TYPE(PCDIMMDevice, PCDIMMDeviceClass,
- pc_dimm, PC_DIMM)
+ PC_DIMM)
#define PC_DIMM_ADDR_PROP "addr"
#define PC_DIMM_SLOT_PROP "slot"
#include "qom/object.h"
#define TYPE_MIPS_CPS "mips-cps"
-typedef struct MIPSCPSState MIPSCPSState;
-DECLARE_INSTANCE_CHECKER(MIPSCPSState, MIPS_CPS,
- TYPE_MIPS_CPS)
+OBJECT_DECLARE_SIMPLE_TYPE(MIPSCPSState, MIPS_CPS)
struct MIPSCPSState {
SysBusDevice parent_obj;
uint32_t status;
uint32_t num_cpu;
};
-typedef struct A9SCUState A9SCUState;
#define TYPE_A9_SCU "a9-scu"
-DECLARE_INSTANCE_CHECKER(A9SCUState, A9_SCU,
- TYPE_A9_SCU)
+OBJECT_DECLARE_SIMPLE_TYPE(A9SCUState, A9_SCU)
#endif
*/
#define TYPE_AW_CPUCFG "allwinner-cpucfg"
-typedef struct AwCpuCfgState AwCpuCfgState;
-DECLARE_INSTANCE_CHECKER(AwCpuCfgState, AW_CPUCFG,
- TYPE_AW_CPUCFG)
+OBJECT_DECLARE_SIMPLE_TYPE(AwCpuCfgState, AW_CPUCFG)
/** @} */
*/
#define TYPE_AW_H3_CCU "allwinner-h3-ccu"
-typedef struct AwH3ClockCtlState AwH3ClockCtlState;
-DECLARE_INSTANCE_CHECKER(AwH3ClockCtlState, AW_H3_CCU,
- TYPE_AW_H3_CCU)
+OBJECT_DECLARE_SIMPLE_TYPE(AwH3ClockCtlState, AW_H3_CCU)
/** @} */
*/
#define TYPE_AW_H3_DRAMC "allwinner-h3-dramc"
-typedef struct AwH3DramCtlState AwH3DramCtlState;
-DECLARE_INSTANCE_CHECKER(AwH3DramCtlState, AW_H3_DRAMC,
- TYPE_AW_H3_DRAMC)
+OBJECT_DECLARE_SIMPLE_TYPE(AwH3DramCtlState, AW_H3_DRAMC)
/** @} */
*/
#define TYPE_AW_H3_SYSCTRL "allwinner-h3-sysctrl"
-typedef struct AwH3SysCtrlState AwH3SysCtrlState;
-DECLARE_INSTANCE_CHECKER(AwH3SysCtrlState, AW_H3_SYSCTRL,
- TYPE_AW_H3_SYSCTRL)
+OBJECT_DECLARE_SIMPLE_TYPE(AwH3SysCtrlState, AW_H3_SYSCTRL)
/** @} */
*/
#define TYPE_AW_SID "allwinner-sid"
-typedef struct AwSidState AwSidState;
-DECLARE_INSTANCE_CHECKER(AwSidState, AW_SID,
- TYPE_AW_SID)
+OBJECT_DECLARE_SIMPLE_TYPE(AwSidState, AW_SID)
/** @} */
#include "qom/object.h"
#define TYPE_ARM11_SCU "arm11-scu"
-typedef struct ARM11SCUState ARM11SCUState;
-DECLARE_INSTANCE_CHECKER(ARM11SCUState, ARM11_SCU,
- TYPE_ARM11_SCU)
+OBJECT_DECLARE_SIMPLE_TYPE(ARM11SCUState, ARM11_SCU)
struct ARM11SCUState {
/*< private >*/
#include "qom/object.h"
#define TYPE_ARMSSE_CPUID "armsse-cpuid"
-typedef struct ARMSSECPUID ARMSSECPUID;
-DECLARE_INSTANCE_CHECKER(ARMSSECPUID, ARMSSE_CPUID,
- TYPE_ARMSSE_CPUID)
+OBJECT_DECLARE_SIMPLE_TYPE(ARMSSECPUID, ARMSSE_CPUID)
struct ARMSSECPUID {
/*< private >*/
#include "qom/object.h"
#define TYPE_ARMSSE_MHU "armsse-mhu"
-typedef struct ARMSSEMHU ARMSSEMHU;
-DECLARE_INSTANCE_CHECKER(ARMSSEMHU, ARMSSE_MHU,
- TYPE_ARMSSE_MHU)
+OBJECT_DECLARE_SIMPLE_TYPE(ARMSSEMHU, ARMSSE_MHU)
struct ARMSSEMHU {
/*< private >*/
#include "qom/object.h"
#define TYPE_ASPEED_SCU "aspeed.scu"
-typedef struct AspeedSCUClass AspeedSCUClass;
-typedef struct AspeedSCUState AspeedSCUState;
-DECLARE_OBJ_CHECKERS(AspeedSCUState, AspeedSCUClass,
- ASPEED_SCU, TYPE_ASPEED_SCU)
+OBJECT_DECLARE_TYPE(AspeedSCUState, AspeedSCUClass, ASPEED_SCU)
#define TYPE_ASPEED_2400_SCU TYPE_ASPEED_SCU "-ast2400"
#define TYPE_ASPEED_2500_SCU TYPE_ASPEED_SCU "-ast2500"
#define TYPE_ASPEED_2600_SCU TYPE_ASPEED_SCU "-ast2600"
#include "qom/object.h"
#define TYPE_ASPEED_SDMC "aspeed.sdmc"
-typedef struct AspeedSDMCClass AspeedSDMCClass;
-typedef struct AspeedSDMCState AspeedSDMCState;
-DECLARE_OBJ_CHECKERS(AspeedSDMCState, AspeedSDMCClass,
- ASPEED_SDMC, TYPE_ASPEED_SDMC)
+OBJECT_DECLARE_TYPE(AspeedSDMCState, AspeedSDMCClass, ASPEED_SDMC)
#define TYPE_ASPEED_2400_SDMC TYPE_ASPEED_SDMC "-ast2400"
#define TYPE_ASPEED_2500_SDMC TYPE_ASPEED_SDMC "-ast2500"
#define TYPE_ASPEED_2600_SDMC TYPE_ASPEED_SDMC "-ast2600"
#include "qom/object.h"
#define TYPE_ASPEED_XDMA "aspeed.xdma"
-typedef struct AspeedXDMAState AspeedXDMAState;
-DECLARE_INSTANCE_CHECKER(AspeedXDMAState, ASPEED_XDMA,
- TYPE_ASPEED_XDMA)
+OBJECT_DECLARE_SIMPLE_TYPE(AspeedXDMAState, ASPEED_XDMA)
#define ASPEED_XDMA_NUM_REGS (ASPEED_XDMA_REG_SIZE / sizeof(uint32_t))
#define ASPEED_XDMA_REG_SIZE 0x7C
#include "hw/qdev-core.h"
#include "qom/object.h"
-typedef struct AUXBus AUXBus;
typedef struct AUXSlave AUXSlave;
typedef enum AUXCommand AUXCommand;
typedef enum AUXReply AUXReply;
#define TYPE_AUXTOI2C "aux-to-i2c-bridge"
-typedef struct AUXTOI2CState AUXTOI2CState;
-DECLARE_INSTANCE_CHECKER(AUXTOI2CState, AUXTOI2C,
- TYPE_AUXTOI2C)
+OBJECT_DECLARE_SIMPLE_TYPE(AUXTOI2CState, AUXTOI2C)
enum AUXCommand {
WRITE_I2C = 0,
};
#define TYPE_AUX_BUS "aux-bus"
-DECLARE_INSTANCE_CHECKER(AUXBus, AUX_BUS,
- TYPE_AUX_BUS)
+OBJECT_DECLARE_SIMPLE_TYPE(AUXBus, AUX_BUS)
struct AUXBus {
/* < private > */
};
#define TYPE_AUX_SLAVE "aux-slave"
-DECLARE_INSTANCE_CHECKER(AUXSlave, AUX_SLAVE,
- TYPE_AUX_SLAVE)
+OBJECT_DECLARE_SIMPLE_TYPE(AUXSlave, AUX_SLAVE)
struct AUXSlave {
/* < private > */
#define TYPE_AVR_MASK "avr-power"
-typedef struct AVRMaskState AVRMaskState;
-DECLARE_INSTANCE_CHECKER(AVRMaskState, AVR_MASK,
- TYPE_AVR_MASK)
+OBJECT_DECLARE_SIMPLE_TYPE(AVRMaskState, AVR_MASK)
struct AVRMaskState {
/* <private> */
#include "qom/object.h"
#define TYPE_BCM2835_MBOX "bcm2835-mbox"
-typedef struct BCM2835MboxState BCM2835MboxState;
-DECLARE_INSTANCE_CHECKER(BCM2835MboxState, BCM2835_MBOX,
- TYPE_BCM2835_MBOX)
+OBJECT_DECLARE_SIMPLE_TYPE(BCM2835MboxState, BCM2835_MBOX)
typedef struct {
uint32_t reg[MBOX_SIZE];
#define TYPE_BCM2835_MPHI "bcm2835-mphi"
-DECLARE_INSTANCE_CHECKER(BCM2835MphiState, BCM2835_MPHI,
- TYPE_BCM2835_MPHI)
+OBJECT_DECLARE_SIMPLE_TYPE(BCM2835MphiState, BCM2835_MPHI)
#endif
#include "qom/object.h"
#define TYPE_BCM2835_PROPERTY "bcm2835-property"
-typedef struct BCM2835PropertyState BCM2835PropertyState;
-DECLARE_INSTANCE_CHECKER(BCM2835PropertyState, BCM2835_PROPERTY,
- TYPE_BCM2835_PROPERTY)
+OBJECT_DECLARE_SIMPLE_TYPE(BCM2835PropertyState, BCM2835_PROPERTY)
struct BCM2835PropertyState {
/*< private >*/
#include "qom/object.h"
#define TYPE_BCM2835_RNG "bcm2835-rng"
-typedef struct BCM2835RngState BCM2835RngState;
-DECLARE_INSTANCE_CHECKER(BCM2835RngState, BCM2835_RNG,
- TYPE_BCM2835_RNG)
+OBJECT_DECLARE_SIMPLE_TYPE(BCM2835RngState, BCM2835_RNG)
struct BCM2835RngState {
SysBusDevice busdev;
#define TYPE_BCM2835_THERMAL "bcm2835-thermal"
-typedef struct Bcm2835ThermalState Bcm2835ThermalState;
-DECLARE_INSTANCE_CHECKER(Bcm2835ThermalState, BCM2835_THERMAL,
- TYPE_BCM2835_THERMAL)
+OBJECT_DECLARE_SIMPLE_TYPE(Bcm2835ThermalState, BCM2835_THERMAL)
struct Bcm2835ThermalState {
/*< private >*/
#include "qom/object.h"
#define TYPE_GRLIB_AHB_PNP "grlib,ahbpnp"
-typedef struct AHBPnp AHBPnp;
-DECLARE_INSTANCE_CHECKER(AHBPnp, GRLIB_AHB_PNP,
- TYPE_GRLIB_AHB_PNP)
+OBJECT_DECLARE_SIMPLE_TYPE(AHBPnp, GRLIB_AHB_PNP)
#define TYPE_GRLIB_APB_PNP "grlib,apbpnp"
-typedef struct APBPnp APBPnp;
-DECLARE_INSTANCE_CHECKER(APBPnp, GRLIB_APB_PNP,
- TYPE_GRLIB_APB_PNP)
+OBJECT_DECLARE_SIMPLE_TYPE(APBPnp, GRLIB_APB_PNP)
void grlib_ahb_pnp_add_entry(AHBPnp *dev, uint32_t address, uint32_t mask,
uint8_t vendor, uint16_t device, int slave,
CCTL_##name##_SHIFT)
#define TYPE_IMX25_CCM "imx25.ccm"
-typedef struct IMX25CCMState IMX25CCMState;
-DECLARE_INSTANCE_CHECKER(IMX25CCMState, IMX25_CCM,
- TYPE_IMX25_CCM)
+OBJECT_DECLARE_SIMPLE_TYPE(IMX25CCMState, IMX25_CCM)
struct IMX25CCMState {
/* <private> */
PDR0_##name##_PODF_SHIFT)
#define TYPE_IMX31_CCM "imx31.ccm"
-typedef struct IMX31CCMState IMX31CCMState;
-DECLARE_INSTANCE_CHECKER(IMX31CCMState, IMX31_CCM,
- TYPE_IMX31_CCM)
+OBJECT_DECLARE_SIMPLE_TYPE(IMX31CCMState, IMX31_CCM)
struct IMX31CCMState {
/* <private> */
#define EXTRACT(value, name) extract32(value, name##_SHIFT, name##_LENGTH)
#define TYPE_IMX6_CCM "imx6.ccm"
-typedef struct IMX6CCMState IMX6CCMState;
-DECLARE_INSTANCE_CHECKER(IMX6CCMState, IMX6_CCM,
- TYPE_IMX6_CCM)
+OBJECT_DECLARE_SIMPLE_TYPE(IMX6CCMState, IMX6_CCM)
struct IMX6CCMState {
/* <private> */
#define EXTRACT(value, name) extract32(value, name##_SHIFT, name##_LENGTH)
#define TYPE_IMX6_SRC "imx6.src"
-typedef struct IMX6SRCState IMX6SRCState;
-DECLARE_INSTANCE_CHECKER(IMX6SRCState, IMX6_SRC,
- TYPE_IMX6_SRC)
+OBJECT_DECLARE_SIMPLE_TYPE(IMX6SRCState, IMX6_SRC)
struct IMX6SRCState {
/* <private> */
#define CCM_ANALOG_PLL_LOCK (1 << 31);
#define TYPE_IMX6UL_CCM "imx6ul.ccm"
-typedef struct IMX6ULCCMState IMX6ULCCMState;
-DECLARE_INSTANCE_CHECKER(IMX6ULCCMState, IMX6UL_CCM,
- TYPE_IMX6UL_CCM)
+OBJECT_DECLARE_SIMPLE_TYPE(IMX6ULCCMState, IMX6UL_CCM)
struct IMX6ULCCMState {
/* <private> */
};
#define TYPE_IMX7_CCM "imx7.ccm"
-typedef struct IMX7CCMState IMX7CCMState;
-DECLARE_INSTANCE_CHECKER(IMX7CCMState, IMX7_CCM,
- TYPE_IMX7_CCM)
+OBJECT_DECLARE_SIMPLE_TYPE(IMX7CCMState, IMX7_CCM)
struct IMX7CCMState {
/* <private> */
#define TYPE_IMX7_ANALOG "imx7.analog"
-typedef struct IMX7AnalogState IMX7AnalogState;
-DECLARE_INSTANCE_CHECKER(IMX7AnalogState, IMX7_ANALOG,
- TYPE_IMX7_ANALOG)
+OBJECT_DECLARE_SIMPLE_TYPE(IMX7AnalogState, IMX7_ANALOG)
struct IMX7AnalogState {
/* <private> */
#include "qom/object.h"
#define TYPE_IMX7_GPR "imx7.gpr"
-typedef struct IMX7GPRState IMX7GPRState;
-DECLARE_INSTANCE_CHECKER(IMX7GPRState, IMX7_GPR,
- TYPE_IMX7_GPR)
+OBJECT_DECLARE_SIMPLE_TYPE(IMX7GPRState, IMX7_GPR)
struct IMX7GPRState {
/* <private> */
};
#define TYPE_IMX7_SNVS "imx7.snvs"
-typedef struct IMX7SNVSState IMX7SNVSState;
-DECLARE_INSTANCE_CHECKER(IMX7SNVSState, IMX7_SNVS,
- TYPE_IMX7_SNVS)
+OBJECT_DECLARE_SIMPLE_TYPE(IMX7SNVSState, IMX7_SNVS)
struct IMX7SNVSState {
/* <private> */
#define PLL_MFN(x) (((x) & 0x3ff) << 0)
#define TYPE_IMX_CCM "imx.ccm"
-typedef struct IMXCCMClass IMXCCMClass;
-typedef struct IMXCCMState IMXCCMState;
-DECLARE_OBJ_CHECKERS(IMXCCMState, IMXCCMClass,
- IMX_CCM, TYPE_IMX_CCM)
+OBJECT_DECLARE_TYPE(IMXCCMState, IMXCCMClass, IMX_CCM)
struct IMXCCMState {
/* <private> */
#include "qom/object.h"
#define TYPE_IMX_RNGC "imx.rngc"
-typedef struct IMXRNGCState IMXRNGCState;
-DECLARE_INSTANCE_CHECKER(IMXRNGCState, IMX_RNGC,
- TYPE_IMX_RNGC)
+OBJECT_DECLARE_SIMPLE_TYPE(IMXRNGCState, IMX_RNGC)
struct IMXRNGCState {
/*< private >*/
#include "qom/object.h"
#define TYPE_IOTKIT_SECCTL "iotkit-secctl"
-typedef struct IoTKitSecCtl IoTKitSecCtl;
-DECLARE_INSTANCE_CHECKER(IoTKitSecCtl, IOTKIT_SECCTL,
- TYPE_IOTKIT_SECCTL)
+OBJECT_DECLARE_SIMPLE_TYPE(IoTKitSecCtl, IOTKIT_SECCTL)
#define IOTS_APB_PPC0_NUM_PORTS 3
#define IOTS_APB_PPC1_NUM_PORTS 1
#include "qom/object.h"
#define TYPE_IOTKIT_SYSCTL "iotkit-sysctl"
-typedef struct IoTKitSysCtl IoTKitSysCtl;
-DECLARE_INSTANCE_CHECKER(IoTKitSysCtl, IOTKIT_SYSCTL,
- TYPE_IOTKIT_SYSCTL)
+OBJECT_DECLARE_SIMPLE_TYPE(IoTKitSysCtl, IOTKIT_SYSCTL)
struct IoTKitSysCtl {
/*< private >*/
#include "qom/object.h"
#define TYPE_IOTKIT_SYSINFO "iotkit-sysinfo"
-typedef struct IoTKitSysInfo IoTKitSysInfo;
-DECLARE_INSTANCE_CHECKER(IoTKitSysInfo, IOTKIT_SYSINFO,
- TYPE_IOTKIT_SYSINFO)
+OBJECT_DECLARE_SIMPLE_TYPE(IoTKitSysInfo, IOTKIT_SYSINFO)
struct IoTKitSysInfo {
/*< private >*/
#define TYPE_MOS6522_Q800_VIA1 "mos6522-q800-via1"
-typedef struct MOS6522Q800VIA1State MOS6522Q800VIA1State;
-DECLARE_INSTANCE_CHECKER(MOS6522Q800VIA1State, MOS6522_Q800_VIA1,
- TYPE_MOS6522_Q800_VIA1)
+OBJECT_DECLARE_SIMPLE_TYPE(MOS6522Q800VIA1State, MOS6522_Q800_VIA1)
struct MOS6522Q800VIA1State {
/*< private >*/
#define VIA2_IRQ_ASC (1 << VIA2_IRQ_ASC_BIT)
#define TYPE_MOS6522_Q800_VIA2 "mos6522-q800-via2"
-typedef struct MOS6522Q800VIA2State MOS6522Q800VIA2State;
-DECLARE_INSTANCE_CHECKER(MOS6522Q800VIA2State, MOS6522_Q800_VIA2,
- TYPE_MOS6522_Q800_VIA2)
+OBJECT_DECLARE_SIMPLE_TYPE(MOS6522Q800VIA2State, MOS6522_Q800_VIA2)
struct MOS6522Q800VIA2State {
/*< private >*/
#define TYPE_MAC_VIA "mac_via"
-typedef struct MacVIAState MacVIAState;
-DECLARE_INSTANCE_CHECKER(MacVIAState, MAC_VIA,
- TYPE_MAC_VIA)
+OBJECT_DECLARE_SIMPLE_TYPE(MacVIAState, MAC_VIA)
struct MacVIAState {
SysBusDevice busdev;
/*< private >*/
MOS6522State parent_obj;
};
-typedef struct MOS6522CUDAState MOS6522CUDAState;
#define TYPE_MOS6522_CUDA "mos6522-cuda"
-DECLARE_INSTANCE_CHECKER(MOS6522CUDAState, MOS6522_CUDA,
- TYPE_MOS6522_CUDA)
+OBJECT_DECLARE_SIMPLE_TYPE(MOS6522CUDAState, MOS6522_CUDA)
/* Cuda */
#define TYPE_CUDA "cuda"
-typedef struct CUDAState CUDAState;
-DECLARE_INSTANCE_CHECKER(CUDAState, CUDA,
- TYPE_CUDA)
+OBJECT_DECLARE_SIMPLE_TYPE(CUDAState, CUDA)
struct CUDAState {
/*< private >*/
#include "qom/object.h"
#define TYPE_MACIO_GPIO "macio-gpio"
-typedef struct MacIOGPIOState MacIOGPIOState;
-DECLARE_INSTANCE_CHECKER(MacIOGPIOState, MACIO_GPIO,
- TYPE_MACIO_GPIO)
+OBJECT_DECLARE_SIMPLE_TYPE(MacIOGPIOState, MACIO_GPIO)
struct MacIOGPIOState {
/*< private >*/
/* MacIO virtual bus */
#define TYPE_MACIO_BUS "macio-bus"
-typedef struct MacIOBusState MacIOBusState;
-DECLARE_INSTANCE_CHECKER(MacIOBusState, MACIO_BUS,
- TYPE_MACIO_BUS)
+OBJECT_DECLARE_SIMPLE_TYPE(MacIOBusState, MACIO_BUS)
struct MacIOBusState {
/*< private >*/
/* MacIO IDE */
#define TYPE_MACIO_IDE "macio-ide"
-typedef struct MACIOIDEState MACIOIDEState;
-DECLARE_INSTANCE_CHECKER(MACIOIDEState, MACIO_IDE,
- TYPE_MACIO_IDE)
+OBJECT_DECLARE_SIMPLE_TYPE(MACIOIDEState, MACIO_IDE)
struct MACIOIDEState {
/*< private >*/
void macio_ide_register_dma(MACIOIDEState *ide);
#define TYPE_MACIO "macio"
-typedef struct MacIOState MacIOState;
-DECLARE_INSTANCE_CHECKER(MacIOState, MACIO,
- TYPE_MACIO)
+OBJECT_DECLARE_SIMPLE_TYPE(MacIOState, MACIO)
struct MacIOState {
/*< private >*/
};
#define TYPE_OLDWORLD_MACIO "macio-oldworld"
-typedef struct OldWorldMacIOState OldWorldMacIOState;
-DECLARE_INSTANCE_CHECKER(OldWorldMacIOState, OLDWORLD_MACIO,
- TYPE_OLDWORLD_MACIO)
+OBJECT_DECLARE_SIMPLE_TYPE(OldWorldMacIOState, OLDWORLD_MACIO)
struct OldWorldMacIOState {
/*< private >*/
};
#define TYPE_NEWWORLD_MACIO "macio-newworld"
-typedef struct NewWorldMacIOState NewWorldMacIOState;
-DECLARE_INSTANCE_CHECKER(NewWorldMacIOState, NEWWORLD_MACIO,
- TYPE_NEWWORLD_MACIO)
+OBJECT_DECLARE_SIMPLE_TYPE(NewWorldMacIOState, NEWWORLD_MACIO)
struct NewWorldMacIOState {
/*< private >*/
/*< private >*/
MOS6522State parent_obj;
};
-typedef struct MOS6522PMUState MOS6522PMUState;
#define TYPE_MOS6522_PMU "mos6522-pmu"
-DECLARE_INSTANCE_CHECKER(MOS6522PMUState, MOS6522_PMU,
- TYPE_MOS6522_PMU)
+OBJECT_DECLARE_SIMPLE_TYPE(MOS6522PMUState, MOS6522_PMU)
/**
* PMUState:
* @last_b: last value of B register
/* GPIO */
MacIOGPIOState *gpio;
};
-typedef struct PMUState PMUState;
#define TYPE_VIA_PMU "via-pmu"
-DECLARE_INSTANCE_CHECKER(PMUState, VIA_PMU,
- TYPE_VIA_PMU)
+OBJECT_DECLARE_SIMPLE_TYPE(PMUState, VIA_PMU)
#endif /* PMU_H */
uint8_t input[8];
int inputs, com;
};
-typedef struct MAX111xState MAX111xState;
#define TYPE_MAX_111X "max111x"
-DECLARE_INSTANCE_CHECKER(MAX111xState, MAX_111X,
- TYPE_MAX_111X)
+OBJECT_DECLARE_SIMPLE_TYPE(MAX111xState, MAX_111X)
#define TYPE_MAX_1110 "max1110"
#define TYPE_MAX_1111 "max1111"
#include "qom/object.h"
#define TYPE_MIPS_GCR "mips-gcr"
-typedef struct MIPSGCRState MIPSGCRState;
-DECLARE_INSTANCE_CHECKER(MIPSGCRState, MIPS_GCR,
- TYPE_MIPS_GCR)
+OBJECT_DECLARE_SIMPLE_TYPE(MIPSGCRState, MIPS_GCR)
#define GCR_BASE_ADDR 0x1fbf8000ULL
#define GCR_ADDRSPACE_SZ 0x8000
#define CPC_VP_RUNNING_OFS 0x30
#define TYPE_MIPS_CPC "mips-cpc"
-typedef struct MIPSCPCState MIPSCPCState;
-DECLARE_INSTANCE_CHECKER(MIPSCPCState, MIPS_CPC,
- TYPE_MIPS_CPC)
+OBJECT_DECLARE_SIMPLE_TYPE(MIPSCPCState, MIPS_CPC)
struct MIPSCPCState {
SysBusDevice parent_obj;
#include "qom/object.h"
#define TYPE_MIPS_ITU "mips-itu"
-typedef struct MIPSITUState MIPSITUState;
-DECLARE_INSTANCE_CHECKER(MIPSITUState, MIPS_ITU,
- TYPE_MIPS_ITU)
+OBJECT_DECLARE_SIMPLE_TYPE(MIPSITUState, MIPS_ITU)
#define ITC_CELL_DEPTH_SHIFT 2
#define ITC_CELL_DEPTH (1u << ITC_CELL_DEPTH_SHIFT)
qemu_irq irq;
};
-typedef struct MOS6522State MOS6522State;
#define TYPE_MOS6522 "mos6522"
-typedef struct MOS6522DeviceClass MOS6522DeviceClass;
-DECLARE_OBJ_CHECKERS(MOS6522State, MOS6522DeviceClass,
- MOS6522, TYPE_MOS6522)
+OBJECT_DECLARE_TYPE(MOS6522State, MOS6522DeviceClass, MOS6522)
struct MOS6522DeviceClass {
DeviceClass parent_class;
#include "qom/object.h"
#define TYPE_MPS2_FPGAIO "mps2-fpgaio"
-typedef struct MPS2FPGAIO MPS2FPGAIO;
-DECLARE_INSTANCE_CHECKER(MPS2FPGAIO, MPS2_FPGAIO,
- TYPE_MPS2_FPGAIO)
+OBJECT_DECLARE_SIMPLE_TYPE(MPS2FPGAIO, MPS2_FPGAIO)
struct MPS2FPGAIO {
/*< private >*/
#include "qom/object.h"
#define TYPE_MPS2_SCC "mps2-scc"
-typedef struct MPS2SCC MPS2SCC;
-DECLARE_INSTANCE_CHECKER(MPS2SCC, MPS2_SCC,
- TYPE_MPS2_SCC)
+OBJECT_DECLARE_SIMPLE_TYPE(MPS2SCC, MPS2_SCC)
#define NUM_OSCCLK 3
#define MSF2_SYSREG_MMIO_SIZE 0x300
#define TYPE_MSF2_SYSREG "msf2-sysreg"
-typedef struct MSF2SysregState MSF2SysregState;
-DECLARE_INSTANCE_CHECKER(MSF2SysregState, MSF2_SYSREG,
- TYPE_MSF2_SYSREG)
+OBJECT_DECLARE_SIMPLE_TYPE(MSF2SysregState, MSF2_SYSREG)
struct MSF2SysregState {
SysBusDevice parent_obj;
#include "qemu/timer.h"
#include "qom/object.h"
#define TYPE_NRF51_RNG "nrf51_soc.rng"
-typedef struct NRF51RNGState NRF51RNGState;
-DECLARE_INSTANCE_CHECKER(NRF51RNGState, NRF51_RNG,
- TYPE_NRF51_RNG)
+OBJECT_DECLARE_SIMPLE_TYPE(NRF51RNGState, NRF51_RNG)
#define NRF51_RNG_SIZE 0x1000
#ifndef HW_SIFIVE_E_PRCI_H
#define HW_SIFIVE_E_PRCI_H
+#include "qom/object.h"
enum {
SIFIVE_E_PRCI_HFROSCCFG = 0x0,
#define TYPE_SIFIVE_E_PRCI "riscv.sifive.e.prci"
-#define SIFIVE_E_PRCI(obj) \
- OBJECT_CHECK(SiFiveEPRCIState, (obj), TYPE_SIFIVE_E_PRCI)
+typedef struct SiFiveEPRCIState SiFiveEPRCIState;
+DECLARE_INSTANCE_CHECKER(SiFiveEPRCIState, SIFIVE_E_PRCI,
+ TYPE_SIFIVE_E_PRCI)
-typedef struct SiFiveEPRCIState {
+struct SiFiveEPRCIState {
/*< private >*/
SysBusDevice parent_obj;
uint32_t hfxosccfg;
uint32_t pllcfg;
uint32_t plloutdiv;
-} SiFiveEPRCIState;
+};
DeviceState *sifive_e_prci_create(hwaddr addr);
#define HW_SIFIVE_TEST_H
#include "hw/sysbus.h"
+#include "qom/object.h"
#define TYPE_SIFIVE_TEST "riscv.sifive.test"
-#define SIFIVE_TEST(obj) \
- OBJECT_CHECK(SiFiveTestState, (obj), TYPE_SIFIVE_TEST)
+typedef struct SiFiveTestState SiFiveTestState;
+DECLARE_INSTANCE_CHECKER(SiFiveTestState, SIFIVE_TEST,
+ TYPE_SIFIVE_TEST)
-typedef struct SiFiveTestState {
+struct SiFiveTestState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion mmio;
-} SiFiveTestState;
+};
enum {
FINISHER_FAIL = 0x3333,
#ifndef HW_SIFIVE_U_OTP_H
#define HW_SIFIVE_U_OTP_H
+#include "qom/object.h"
#define SIFIVE_U_OTP_PA 0x00
#define SIFIVE_U_OTP_PAIO 0x04
#define TYPE_SIFIVE_U_OTP "riscv.sifive.u.otp"
-#define SIFIVE_U_OTP(obj) \
- OBJECT_CHECK(SiFiveUOTPState, (obj), TYPE_SIFIVE_U_OTP)
+typedef struct SiFiveUOTPState SiFiveUOTPState;
+DECLARE_INSTANCE_CHECKER(SiFiveUOTPState, SIFIVE_U_OTP,
+ TYPE_SIFIVE_U_OTP)
-typedef struct SiFiveUOTPState {
+struct SiFiveUOTPState {
/*< private >*/
SysBusDevice parent_obj;
uint32_t fuse[SIFIVE_U_OTP_NUM_FUSES];
/* config */
uint32_t serial;
-} SiFiveUOTPState;
+};
#endif /* HW_SIFIVE_U_OTP_H */
#ifndef HW_SIFIVE_U_PRCI_H
#define HW_SIFIVE_U_PRCI_H
+#include "qom/object.h"
#define SIFIVE_U_PRCI_HFXOSCCFG 0x00
#define SIFIVE_U_PRCI_COREPLLCFG0 0x04
#define TYPE_SIFIVE_U_PRCI "riscv.sifive.u.prci"
-#define SIFIVE_U_PRCI(obj) \
- OBJECT_CHECK(SiFiveUPRCIState, (obj), TYPE_SIFIVE_U_PRCI)
+typedef struct SiFiveUPRCIState SiFiveUPRCIState;
+DECLARE_INSTANCE_CHECKER(SiFiveUPRCIState, SIFIVE_U_PRCI,
+ TYPE_SIFIVE_U_PRCI)
-typedef struct SiFiveUPRCIState {
+struct SiFiveUPRCIState {
/*< private >*/
SysBusDevice parent_obj;
uint32_t coreclksel;
uint32_t devicesreset;
uint32_t clkmuxstatus;
-} SiFiveUPRCIState;
+};
/*
* Clock indexes for use by Device Tree data and the PRCI driver.
#define SYSCFG_CMPCR 0x20
#define TYPE_STM32F2XX_SYSCFG "stm32f2xx-syscfg"
-typedef struct STM32F2XXSyscfgState STM32F2XXSyscfgState;
-DECLARE_INSTANCE_CHECKER(STM32F2XXSyscfgState, STM32F2XX_SYSCFG,
- TYPE_STM32F2XX_SYSCFG)
+OBJECT_DECLARE_SIMPLE_TYPE(STM32F2XXSyscfgState, STM32F2XX_SYSCFG)
struct STM32F2XXSyscfgState {
/* <private> */
#define EXTI_PR 0x14
#define TYPE_STM32F4XX_EXTI "stm32f4xx-exti"
-typedef struct STM32F4xxExtiState STM32F4xxExtiState;
-DECLARE_INSTANCE_CHECKER(STM32F4xxExtiState, STM32F4XX_EXTI,
- TYPE_STM32F4XX_EXTI)
+OBJECT_DECLARE_SIMPLE_TYPE(STM32F4xxExtiState, STM32F4XX_EXTI)
#define NUM_GPIO_EVENT_IN_LINES 16
#define NUM_INTERRUPT_OUT_LINES 16
#define SYSCFG_CMPCR 0x20
#define TYPE_STM32F4XX_SYSCFG "stm32f4xx-syscfg"
-typedef struct STM32F4xxSyscfgState STM32F4xxSyscfgState;
-DECLARE_INSTANCE_CHECKER(STM32F4xxSyscfgState, STM32F4XX_SYSCFG,
- TYPE_STM32F4XX_SYSCFG)
+OBJECT_DECLARE_SIMPLE_TYPE(STM32F4xxSyscfgState, STM32F4XX_SYSCFG)
#define SYSCFG_NUM_EXTICR 4
#include "qom/object.h"
#define TYPE_TZ_MPC "tz-mpc"
-typedef struct TZMPC TZMPC;
-DECLARE_INSTANCE_CHECKER(TZMPC, TZ_MPC,
- TYPE_TZ_MPC)
+OBJECT_DECLARE_SIMPLE_TYPE(TZMPC, TZ_MPC)
#define TZ_NUM_PORTS 16
#include "qom/object.h"
#define TYPE_TZ_MSC "tz-msc"
-typedef struct TZMSC TZMSC;
-DECLARE_INSTANCE_CHECKER(TZMSC, TZ_MSC,
- TYPE_TZ_MSC)
+OBJECT_DECLARE_SIMPLE_TYPE(TZMSC, TZ_MSC)
struct TZMSC {
/*< private >*/
#include "qom/object.h"
#define TYPE_TZ_PPC "tz-ppc"
-typedef struct TZPPC TZPPC;
-DECLARE_INSTANCE_CHECKER(TZPPC, TZ_PPC,
- TYPE_TZ_PPC)
+OBJECT_DECLARE_SIMPLE_TYPE(TZPPC, TZ_PPC)
#define TZ_NUM_PORTS 16
#define TYPE_UNIMPLEMENTED_DEVICE "unimplemented-device"
-typedef struct UnimplementedDeviceState UnimplementedDeviceState;
-DECLARE_INSTANCE_CHECKER(UnimplementedDeviceState, UNIMPLEMENTED_DEVICE,
- TYPE_UNIMPLEMENTED_DEVICE)
+OBJECT_DECLARE_SIMPLE_TYPE(UnimplementedDeviceState, UNIMPLEMENTED_DEVICE)
struct UnimplementedDeviceState {
SysBusDevice parent_obj;
#define ZYNQ_XADC_FIFO_DEPTH 15
#define TYPE_ZYNQ_XADC "xlnx,zynq-xadc"
-typedef struct ZynqXADCState ZynqXADCState;
-DECLARE_INSTANCE_CHECKER(ZynqXADCState, ZYNQ_XADC,
- TYPE_ZYNQ_XADC)
+OBJECT_DECLARE_SIMPLE_TYPE(ZynqXADCState, ZYNQ_XADC)
struct ZynqXADCState {
/*< private >*/
*/
#define TYPE_AW_SUN8I_EMAC "allwinner-sun8i-emac"
-typedef struct AwSun8iEmacState AwSun8iEmacState;
-DECLARE_INSTANCE_CHECKER(AwSun8iEmacState, AW_SUN8I_EMAC,
- TYPE_AW_SUN8I_EMAC)
+OBJECT_DECLARE_SIMPLE_TYPE(AwSun8iEmacState, AW_SUN8I_EMAC)
/** @} */
#include "qom/object.h"
#define TYPE_AW_EMAC "allwinner-emac"
-typedef struct AwEmacState AwEmacState;
-DECLARE_INSTANCE_CHECKER(AwEmacState, AW_EMAC,
- TYPE_AW_EMAC)
+OBJECT_DECLARE_SIMPLE_TYPE(AwEmacState, AW_EMAC)
/*
* Allwinner EMAC register list
#include "qom/object.h"
#define TYPE_CADENCE_GEM "cadence_gem"
-typedef struct CadenceGEMState CadenceGEMState;
-DECLARE_INSTANCE_CHECKER(CadenceGEMState, CADENCE_GEM,
- TYPE_CADENCE_GEM)
+OBJECT_DECLARE_SIMPLE_TYPE(CadenceGEMState, CADENCE_GEM)
#include "net/net.h"
#include "hw/sysbus.h"
#include "qom/object.h"
#define TYPE_FTGMAC100 "ftgmac100"
-typedef struct FTGMAC100State FTGMAC100State;
-DECLARE_INSTANCE_CHECKER(FTGMAC100State, FTGMAC100,
- TYPE_FTGMAC100)
+OBJECT_DECLARE_SIMPLE_TYPE(FTGMAC100State, FTGMAC100)
#include "hw/sysbus.h"
#include "net/net.h"
};
#define TYPE_ASPEED_MII "aspeed-mmi"
-typedef struct AspeedMiiState AspeedMiiState;
-DECLARE_INSTANCE_CHECKER(AspeedMiiState, ASPEED_MII,
- TYPE_ASPEED_MII)
+OBJECT_DECLARE_SIMPLE_TYPE(AspeedMiiState, ASPEED_MII)
/*
* AST2600 MII controller
#include "qom/object.h"
#define TYPE_IMX_FEC "imx.fec"
-typedef struct IMXFECState IMXFECState;
-DECLARE_INSTANCE_CHECKER(IMXFECState, IMX_FEC,
- TYPE_IMX_FEC)
+OBJECT_DECLARE_SIMPLE_TYPE(IMXFECState, IMX_FEC)
#define TYPE_IMX_ENET "imx.enet"
#include "qom/object.h"
#define TYPE_MSS_EMAC "msf2-emac"
-typedef struct MSF2EmacState MSF2EmacState;
-DECLARE_INSTANCE_CHECKER(MSF2EmacState, MSS_EMAC,
- TYPE_MSS_EMAC)
+OBJECT_DECLARE_SIMPLE_TYPE(MSF2EmacState, MSS_EMAC)
#define R_MAX (0x1a0 / 4)
#define PHY_MAX_REGS 32
#include "qom/object.h"
#define TYPE_MAC_NUBUS_BRIDGE "mac-nubus-bridge"
-typedef struct MacNubusState MacNubusState;
-DECLARE_INSTANCE_CHECKER(MacNubusState, MAC_NUBUS_BRIDGE,
- TYPE_MAC_NUBUS_BRIDGE)
+OBJECT_DECLARE_SIMPLE_TYPE(MacNubusState, MAC_NUBUS_BRIDGE)
struct MacNubusState {
SysBusDevice sysbus_dev;
#define NUBUS_LAST_SLOT 0xF
#define TYPE_NUBUS_DEVICE "nubus-device"
-typedef struct NubusDevice NubusDevice;
-DECLARE_INSTANCE_CHECKER(NubusDevice, NUBUS_DEVICE,
- TYPE_NUBUS_DEVICE)
+OBJECT_DECLARE_SIMPLE_TYPE(NubusDevice, NUBUS_DEVICE)
#define TYPE_NUBUS_BUS "nubus-bus"
-typedef struct NubusBus NubusBus;
-DECLARE_INSTANCE_CHECKER(NubusBus, NUBUS_BUS,
- TYPE_NUBUS_BUS)
+OBJECT_DECLARE_SIMPLE_TYPE(NubusBus, NUBUS_BUS)
#define TYPE_NUBUS_BRIDGE "nubus-bridge"
#define TYPE_FW_CFG_MEM "fw_cfg_mem"
#define TYPE_FW_CFG_DATA_GENERATOR_INTERFACE "fw_cfg-data-generator"
-DECLARE_INSTANCE_CHECKER(FWCfgState, FW_CFG,
- TYPE_FW_CFG)
-DECLARE_INSTANCE_CHECKER(FWCfgIoState, FW_CFG_IO,
- TYPE_FW_CFG_IO)
-DECLARE_INSTANCE_CHECKER(FWCfgMemState, FW_CFG_MEM,
- TYPE_FW_CFG_MEM)
+OBJECT_DECLARE_SIMPLE_TYPE(FWCfgState, FW_CFG)
+OBJECT_DECLARE_SIMPLE_TYPE(FWCfgIoState, FW_CFG_IO)
+OBJECT_DECLARE_SIMPLE_TYPE(FWCfgMemState, FW_CFG_MEM)
typedef struct FWCfgDataGeneratorClass FWCfgDataGeneratorClass;
DECLARE_CLASS_CHECKERS(FWCfgDataGeneratorClass, FW_CFG_DATA_GENERATOR,
#include "hw/sysbus.h"
#include "qom/object.h"
#define TYPE_NRF51_NVM "nrf51_soc.nvm"
-typedef struct NRF51NVMState NRF51NVMState;
-DECLARE_INSTANCE_CHECKER(NRF51NVMState, NRF51_NVM,
- TYPE_NRF51_NVM)
+OBJECT_DECLARE_SIMPLE_TYPE(NRF51NVMState, NRF51_NVM)
#define NRF51_UICR_FIXTURE_SIZE 64
/*< private >*/
PCIBridge parent_obj;
};
-typedef struct SimbaPCIBridge SimbaPCIBridge;
#define TYPE_SIMBA_PCI_BRIDGE "pbm-bridge"
-DECLARE_INSTANCE_CHECKER(SimbaPCIBridge, SIMBA_PCI_BRIDGE,
- TYPE_SIMBA_PCI_BRIDGE)
+OBJECT_DECLARE_SIMPLE_TYPE(SimbaPCIBridge, SIMBA_PCI_BRIDGE)
#endif
#include "qom/object.h"
#define TYPE_DESIGNWARE_PCIE_HOST "designware-pcie-host"
-typedef struct DesignwarePCIEHost DesignwarePCIEHost;
-DECLARE_INSTANCE_CHECKER(DesignwarePCIEHost, DESIGNWARE_PCIE_HOST,
- TYPE_DESIGNWARE_PCIE_HOST)
+OBJECT_DECLARE_SIMPLE_TYPE(DesignwarePCIEHost, DESIGNWARE_PCIE_HOST)
#define TYPE_DESIGNWARE_PCIE_ROOT "designware-pcie-root"
-typedef struct DesignwarePCIERoot DesignwarePCIERoot;
-DECLARE_INSTANCE_CHECKER(DesignwarePCIERoot, DESIGNWARE_PCIE_ROOT,
- TYPE_DESIGNWARE_PCIE_ROOT)
+OBJECT_DECLARE_SIMPLE_TYPE(DesignwarePCIERoot, DESIGNWARE_PCIE_ROOT)
struct DesignwarePCIERoot;
#include "qom/object.h"
#define TYPE_GPEX_HOST "gpex-pcihost"
-typedef struct GPEXHost GPEXHost;
-DECLARE_INSTANCE_CHECKER(GPEXHost, GPEX_HOST,
- TYPE_GPEX_HOST)
+OBJECT_DECLARE_SIMPLE_TYPE(GPEXHost, GPEX_HOST)
#define TYPE_GPEX_ROOT_DEVICE "gpex-root"
-typedef struct GPEXRootState GPEXRootState;
-DECLARE_INSTANCE_CHECKER(GPEXRootState, GPEX_ROOT_DEVICE,
- TYPE_GPEX_ROOT_DEVICE)
+OBJECT_DECLARE_SIMPLE_TYPE(GPEXRootState, GPEX_ROOT_DEVICE)
#define GPEX_NUM_IRQS 4
#define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost"
#define TYPE_I440FX_PCI_DEVICE "i440FX"
-typedef struct PCII440FXState PCII440FXState;
-DECLARE_INSTANCE_CHECKER(PCII440FXState, I440FX_PCI_DEVICE,
- TYPE_I440FX_PCI_DEVICE)
+OBJECT_DECLARE_SIMPLE_TYPE(PCII440FXState, I440FX_PCI_DEVICE)
struct PCII440FXState {
/*< private >*/
* PHB3 Power Bus Common Queue
*/
#define TYPE_PNV_PBCQ "pnv-pbcq"
-typedef struct PnvPBCQState PnvPBCQState;
-DECLARE_INSTANCE_CHECKER(PnvPBCQState, PNV_PBCQ,
- TYPE_PNV_PBCQ)
+OBJECT_DECLARE_SIMPLE_TYPE(PnvPBCQState, PNV_PBCQ)
struct PnvPBCQState {
DeviceState parent;
* PHB3 PCIe Host Bridge for PowerNV machines (POWER8)
*/
#define TYPE_PNV_PHB3 "pnv-phb3"
-DECLARE_INSTANCE_CHECKER(PnvPHB3, PNV_PHB3,
- TYPE_PNV_PHB3)
+OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB3, PNV_PHB3)
#define PNV_PHB3_NUM_M64 16
#define PNV_PHB3_NUM_REGS (0x1000 >> 3)
#include "hw/ppc/xive.h"
#include "qom/object.h"
-typedef struct PnvPhb4PecState PnvPhb4PecState;
typedef struct PnvPhb4PecStack PnvPhb4PecStack;
typedef struct PnvPHB4 PnvPHB4;
typedef struct PnvChip PnvChip;
* PHB4 PCIe Host Bridge for PowerNV machines (POWER9)
*/
#define TYPE_PNV_PHB4 "pnv-phb4"
-DECLARE_INSTANCE_CHECKER(PnvPHB4, PNV_PHB4,
- TYPE_PNV_PHB4)
+OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4, PNV_PHB4)
#define PNV_PHB4_MAX_LSIs 8
#define PNV_PHB4_MAX_INTs 4096
* PHB4 PEC (PCI Express Controller)
*/
#define TYPE_PNV_PHB4_PEC "pnv-phb4-pec"
-typedef struct PnvPhb4PecClass PnvPhb4PecClass;
-DECLARE_OBJ_CHECKERS(PnvPhb4PecState, PnvPhb4PecClass,
- PNV_PHB4_PEC, TYPE_PNV_PHB4_PEC)
+OBJECT_DECLARE_TYPE(PnvPhb4PecState, PnvPhb4PecClass, PNV_PHB4_PEC)
#define TYPE_PNV_PHB4_PEC_STACK "pnv-phb4-pec-stack"
-DECLARE_INSTANCE_CHECKER(PnvPhb4PecStack, PNV_PHB4_PEC_STACK,
- TYPE_PNV_PHB4_PEC_STACK)
+OBJECT_DECLARE_SIMPLE_TYPE(PnvPhb4PecStack, PNV_PHB4_PEC_STACK)
/* Per-stack data */
struct PnvPhb4PecStack {
#include "qom/object.h"
#define TYPE_Q35_HOST_DEVICE "q35-pcihost"
-typedef struct Q35PCIHost Q35PCIHost;
-DECLARE_INSTANCE_CHECKER(Q35PCIHost, Q35_HOST_DEVICE,
- TYPE_Q35_HOST_DEVICE)
+OBJECT_DECLARE_SIMPLE_TYPE(Q35PCIHost, Q35_HOST_DEVICE)
#define TYPE_MCH_PCI_DEVICE "mch"
-typedef struct MCHPCIState MCHPCIState;
-DECLARE_INSTANCE_CHECKER(MCHPCIState, MCH_PCI_DEVICE,
- TYPE_MCH_PCI_DEVICE)
+OBJECT_DECLARE_SIMPLE_TYPE(MCHPCIState, MCH_PCI_DEVICE)
struct MCHPCIState {
/*< private >*/
struct SabrePCIState {
PCIDevice parent_obj;
};
-typedef struct SabrePCIState SabrePCIState;
#define TYPE_SABRE_PCI_DEVICE "sabre-pci"
-DECLARE_INSTANCE_CHECKER(SabrePCIState, SABRE_PCI_DEVICE,
- TYPE_SABRE_PCI_DEVICE)
+OBJECT_DECLARE_SIMPLE_TYPE(SabrePCIState, SABRE_PCI_DEVICE)
struct SabreState {
PCIHostState parent_obj;
uint32_t reset_control;
unsigned int nr_resets;
};
-typedef struct SabreState SabreState;
#define TYPE_SABRE "sabre"
-DECLARE_INSTANCE_CHECKER(SabreState, SABRE,
- TYPE_SABRE)
+OBJECT_DECLARE_SIMPLE_TYPE(SabreState, SABRE)
#endif
#define TYPE_SPAPR_PCI_HOST_BRIDGE "spapr-pci-host-bridge"
-typedef struct SpaprPhbState SpaprPhbState;
-DECLARE_INSTANCE_CHECKER(SpaprPhbState, SPAPR_PCI_HOST_BRIDGE,
- TYPE_SPAPR_PCI_HOST_BRIDGE)
+OBJECT_DECLARE_SIMPLE_TYPE(SpaprPhbState, SPAPR_PCI_HOST_BRIDGE)
#define SPAPR_PCI_DMA_MAX_WINDOWS 2
MemoryRegion mem;
};
-typedef struct UNINState UNINState;
#define TYPE_UNI_NORTH "uni-north"
-DECLARE_INSTANCE_CHECKER(UNINState, UNI_NORTH,
- TYPE_UNI_NORTH)
+OBJECT_DECLARE_SIMPLE_TYPE(UNINState, UNI_NORTH)
#endif /* UNINORTH_H */
#include "qom/object.h"
#define TYPE_XILINX_PCIE_HOST "xilinx-pcie-host"
-typedef struct XilinxPCIEHost XilinxPCIEHost;
-DECLARE_INSTANCE_CHECKER(XilinxPCIEHost, XILINX_PCIE_HOST,
- TYPE_XILINX_PCIE_HOST)
+OBJECT_DECLARE_SIMPLE_TYPE(XilinxPCIEHost, XILINX_PCIE_HOST)
#define TYPE_XILINX_PCIE_ROOT "xilinx-pcie-root"
-typedef struct XilinxPCIERoot XilinxPCIERoot;
-DECLARE_INSTANCE_CHECKER(XilinxPCIERoot, XILINX_PCIE_ROOT,
- TYPE_XILINX_PCIE_ROOT)
+OBJECT_DECLARE_SIMPLE_TYPE(XilinxPCIERoot, XILINX_PCIE_ROOT)
struct XilinxPCIERoot {
PCIBridge parent_obj;
typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
#define TYPE_PCI_BUS "PCI"
-typedef struct PCIBusClass PCIBusClass;
-DECLARE_OBJ_CHECKERS(PCIBus, PCIBusClass,
- PCI_BUS, TYPE_PCI_BUS)
+OBJECT_DECLARE_TYPE(PCIBus, PCIBusClass, PCI_BUS)
#define TYPE_PCIE_BUS "PCIE"
bool pci_bus_is_express(PCIBus *bus);
};
#define TYPE_PCI_BRIDGE "base-pci-bridge"
-DECLARE_INSTANCE_CHECKER(PCIBridge, PCI_BRIDGE,
- TYPE_PCI_BRIDGE)
+OBJECT_DECLARE_SIMPLE_TYPE(PCIBridge, PCI_BRIDGE)
struct PCIBridge {
/*< private >*/
#include "qom/object.h"
#define TYPE_PCI_HOST_BRIDGE "pci-host-bridge"
-typedef struct PCIHostBridgeClass PCIHostBridgeClass;
-DECLARE_OBJ_CHECKERS(PCIHostState, PCIHostBridgeClass,
- PCI_HOST_BRIDGE, TYPE_PCI_HOST_BRIDGE)
+OBJECT_DECLARE_TYPE(PCIHostState, PCIHostBridgeClass, PCI_HOST_BRIDGE)
struct PCIHostState {
SysBusDevice busdev;
#include "qom/object.h"
#define TYPE_PCIE_HOST_BRIDGE "pcie-host-bridge"
-DECLARE_INSTANCE_CHECKER(PCIExpressHost, PCIE_HOST_BRIDGE,
- TYPE_PCIE_HOST_BRIDGE)
+OBJECT_DECLARE_SIMPLE_TYPE(PCIExpressHost, PCIE_HOST_BRIDGE)
#define PCIE_HOST_MCFG_BASE "MCFG"
#define PCIE_HOST_MCFG_SIZE "mcfg_size"
#include "qom/object.h"
#define TYPE_PCIE_PORT "pcie-port"
-DECLARE_INSTANCE_CHECKER(PCIEPort, PCIE_PORT,
- TYPE_PCIE_PORT)
+OBJECT_DECLARE_SIMPLE_TYPE(PCIEPort, PCIE_PORT)
struct PCIEPort {
/*< private >*/
void pcie_port_init_reg(PCIDevice *d);
#define TYPE_PCIE_SLOT "pcie-slot"
-DECLARE_INSTANCE_CHECKER(PCIESlot, PCIE_SLOT,
- TYPE_PCIE_SLOT)
+OBJECT_DECLARE_SIMPLE_TYPE(PCIESlot, PCIE_SLOT)
struct PCIESlot {
/*< private >*/
} PCMCIASocket;
#define TYPE_PCMCIA_CARD "pcmcia-card"
-typedef struct PCMCIACardClass PCMCIACardClass;
-typedef struct PCMCIACardState PCMCIACardState;
-DECLARE_OBJ_CHECKERS(PCMCIACardState, PCMCIACardClass,
- PCMCIA_CARD, TYPE_PCMCIA_CARD)
+OBJECT_DECLARE_TYPE(PCMCIACardState, PCMCIACardClass, PCMCIA_CARD)
struct PCMCIACardState {
/*< private >*/
#include "hw/sysbus.h"
#include "qom/object.h"
-typedef struct PlatformBusDevice PlatformBusDevice;
#define TYPE_PLATFORM_BUS_DEVICE "platform-bus-device"
-DECLARE_INSTANCE_CHECKER(PlatformBusDevice, PLATFORM_BUS_DEVICE,
- TYPE_PLATFORM_BUS_DEVICE)
+OBJECT_DECLARE_SIMPLE_TYPE(PlatformBusDevice, PLATFORM_BUS_DEVICE)
struct PlatformBusDevice {
/*< private >*/
void DBDMA_kick(DBDMAState *dbdma);
#define TYPE_MAC_DBDMA "mac-dbdma"
-DECLARE_INSTANCE_CHECKER(DBDMAState, MAC_DBDMA,
- TYPE_MAC_DBDMA)
+OBJECT_DECLARE_SIMPLE_TYPE(DBDMAState, MAC_DBDMA)
#endif
} IRQDest;
#define TYPE_OPENPIC "openpic"
-typedef struct OpenPICState OpenPICState;
-DECLARE_INSTANCE_CHECKER(OpenPICState, OPENPIC,
- TYPE_OPENPIC)
+OBJECT_DECLARE_SIMPLE_TYPE(OpenPICState, OPENPIC)
struct OpenPICState {
/*< private >*/
#define TYPE_PNV_CHIP "pnv-chip"
OBJECT_DECLARE_TYPE(PnvChip, PnvChipClass,
- pnv_chip, PNV_CHIP)
+ PNV_CHIP)
struct PnvChip {
/*< private >*/
#define TYPE_PNV_CORE "powernv-cpu-core"
OBJECT_DECLARE_TYPE(PnvCore, PnvCoreClass,
- pnv_core, PNV_CORE)
+ PNV_CORE)
typedef struct PnvChip PnvChip;
}
#define TYPE_PNV_QUAD "powernv-cpu-quad"
-typedef struct PnvQuad PnvQuad;
-DECLARE_INSTANCE_CHECKER(PnvQuad, PNV_QUAD,
- TYPE_PNV_QUAD)
+OBJECT_DECLARE_SIMPLE_TYPE(PnvQuad, PNV_QUAD)
struct PnvQuad {
DeviceState parent_obj;
#define TYPE_PNV_HOMER "pnv-homer"
OBJECT_DECLARE_TYPE(PnvHomer, PnvHomerClass,
- pnv_homer, PNV_HOMER)
+ PNV_HOMER)
#define TYPE_PNV8_HOMER TYPE_PNV_HOMER "-POWER8"
DECLARE_INSTANCE_CHECKER(PnvHomer, PNV8_HOMER,
TYPE_PNV8_HOMER)
#define TYPE_PNV_OCC "pnv-occ"
OBJECT_DECLARE_TYPE(PnvOCC, PnvOCCClass,
- pnv_occ, PNV_OCC)
+ PNV_OCC)
#define TYPE_PNV8_OCC TYPE_PNV_OCC "-POWER8"
DECLARE_INSTANCE_CHECKER(PnvOCC, PNV8_OCC,
TYPE_PNV8_OCC)
#define PNOR_SPI_OFFSET 0x0c000000UL
#define TYPE_PNV_PNOR "pnv-pnor"
-typedef struct PnvPnor PnvPnor;
-DECLARE_INSTANCE_CHECKER(PnvPnor, PNV_PNOR,
- TYPE_PNV_PNOR)
+OBJECT_DECLARE_SIMPLE_TYPE(PnvPnor, PNV_PNOR)
struct PnvPnor {
SysBusDevice parent_obj;
#define TYPE_PNV_PSI "pnv-psi"
OBJECT_DECLARE_TYPE(PnvPsi, PnvPsiClass,
- pnv_psi, PNV_PSI)
+ PNV_PSI)
#define PSIHB_XSCOM_MAX 0x20
};
#define TYPE_PNV8_PSI TYPE_PNV_PSI "-POWER8"
-typedef struct Pnv8Psi Pnv8Psi;
-DECLARE_INSTANCE_CHECKER(Pnv8Psi, PNV8_PSI,
- TYPE_PNV8_PSI)
+OBJECT_DECLARE_SIMPLE_TYPE(Pnv8Psi, PNV8_PSI)
struct Pnv8Psi {
PnvPsi parent;
};
#define TYPE_PNV9_PSI TYPE_PNV_PSI "-POWER9"
-typedef struct Pnv9Psi Pnv9Psi;
-DECLARE_INSTANCE_CHECKER(Pnv9Psi, PNV9_PSI,
- TYPE_PNV9_PSI)
+OBJECT_DECLARE_SIMPLE_TYPE(Pnv9Psi, PNV9_PSI)
struct Pnv9Psi {
PnvPsi parent;
#define TYPE_PNV_XIVE "pnv-xive"
OBJECT_DECLARE_TYPE(PnvXive, PnvXiveClass,
- pnv_xive, PNV_XIVE)
+ PNV_XIVE)
#define XIVE_BLOCK_MAX 16
#define TYPE_SPAPR_RTC "spapr-rtc"
-typedef struct SpaprRtcState SpaprRtcState;
-DECLARE_INSTANCE_CHECKER(SpaprRtcState, SPAPR_RTC,
- TYPE_SPAPR_RTC)
+OBJECT_DECLARE_SIMPLE_TYPE(SpaprRtcState, SPAPR_RTC)
struct SpaprRtcState {
/*< private >*/
};
typedef struct SpaprDimmState SpaprDimmState;
-typedef struct SpaprMachineClass SpaprMachineClass;
#define TYPE_SPAPR_MACHINE "spapr-machine"
-typedef struct SpaprMachineState SpaprMachineState;
-DECLARE_OBJ_CHECKERS(SpaprMachineState, SpaprMachineClass,
- SPAPR_MACHINE, TYPE_SPAPR_MACHINE)
+OBJECT_DECLARE_TYPE(SpaprMachineState, SpaprMachineClass, SPAPR_MACHINE)
typedef enum {
SPAPR_RESIZE_HPT_DEFAULT = 0,
intspec[1] = is_lsi ? cpu_to_be32(1) : 0;
}
-typedef struct SpaprTceTable SpaprTceTable;
#define TYPE_SPAPR_TCE_TABLE "spapr-tce-table"
-DECLARE_INSTANCE_CHECKER(SpaprTceTable, SPAPR_TCE_TABLE,
- TYPE_SPAPR_TCE_TABLE)
+OBJECT_DECLARE_SIMPLE_TYPE(SpaprTceTable, SPAPR_TCE_TABLE)
#define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region"
DECLARE_INSTANCE_CHECKER(IOMMUMemoryRegion, SPAPR_IOMMU_MEMORY_REGION,
#define TYPE_SPAPR_CPU_CORE "spapr-cpu-core"
OBJECT_DECLARE_TYPE(SpaprCpuCore, SpaprCpuCoreClass,
- spapr_cpu_core, SPAPR_CPU_CORE)
+ SPAPR_CPU_CORE)
#define SPAPR_CPU_CORE_TYPE_NAME(model) model "-" TYPE_SPAPR_CPU_CORE
#include "hw/qdev-core.h"
#define TYPE_SPAPR_TPM_PROXY "spapr-tpm-proxy"
-typedef struct SpaprTpmProxy SpaprTpmProxy;
-DECLARE_INSTANCE_CHECKER(SpaprTpmProxy, SPAPR_TPM_PROXY,
- TYPE_SPAPR_TPM_PROXY)
+OBJECT_DECLARE_SIMPLE_TYPE(SpaprTpmProxy, SPAPR_TPM_PROXY)
struct SpaprTpmProxy {
/*< private >*/
#define TYPE_VIO_SPAPR_DEVICE "vio-spapr-device"
OBJECT_DECLARE_TYPE(SpaprVioDevice, SpaprVioDeviceClass,
- vio_spapr_device, VIO_SPAPR_DEVICE)
+ VIO_SPAPR_DEVICE)
#define TYPE_SPAPR_VIO_BUS "spapr-vio-bus"
-typedef struct SpaprVioBus SpaprVioBus;
-DECLARE_INSTANCE_CHECKER(SpaprVioBus, SPAPR_VIO_BUS,
- TYPE_SPAPR_VIO_BUS)
+OBJECT_DECLARE_SIMPLE_TYPE(SpaprVioBus, SPAPR_VIO_BUS)
#define TYPE_SPAPR_VIO_BRIDGE "spapr-vio-bridge"
#define TYPE_ICP "icp"
OBJECT_DECLARE_TYPE(ICPState, ICPStateClass,
- icp, ICP)
+ ICP)
#define TYPE_PNV_ICP "pnv-icp"
DECLARE_INSTANCE_CHECKER(PnvICPState, PNV_ICP,
*/
#define TYPE_XIVE_SOURCE "xive-source"
-typedef struct XiveSource XiveSource;
-DECLARE_INSTANCE_CHECKER(XiveSource, XIVE_SOURCE,
- TYPE_XIVE_SOURCE)
+OBJECT_DECLARE_SIMPLE_TYPE(XiveSource, XIVE_SOURCE)
/*
* XIVE Interrupt Source characteristics, which define how the ESB are
*/
#define TYPE_XIVE_TCTX "xive-tctx"
-typedef struct XiveTCTX XiveTCTX;
-DECLARE_INSTANCE_CHECKER(XiveTCTX, XIVE_TCTX,
- TYPE_XIVE_TCTX)
+OBJECT_DECLARE_SIMPLE_TYPE(XiveTCTX, XIVE_TCTX)
/*
* XIVE Thread interrupt Management register rings :
#define TYPE_XIVE_ROUTER "xive-router"
OBJECT_DECLARE_TYPE(XiveRouter, XiveRouterClass,
- xive_router, XIVE_ROUTER)
+ XIVE_ROUTER)
struct XiveRouterClass {
SysBusDeviceClass parent;
*/
#define TYPE_XIVE_END_SOURCE "xive-end-source"
-typedef struct XiveENDSource XiveENDSource;
-DECLARE_INSTANCE_CHECKER(XiveENDSource, XIVE_END_SOURCE,
- TYPE_XIVE_END_SOURCE)
+OBJECT_DECLARE_SIMPLE_TYPE(XiveENDSource, XIVE_END_SOURCE)
struct XiveENDSource {
DeviceState parent;
};
#define TYPE_DEVICE "device"
-typedef struct DeviceClass DeviceClass;
-DECLARE_OBJ_CHECKERS(DeviceState, DeviceClass,
- DEVICE, TYPE_DEVICE)
+OBJECT_DECLARE_TYPE(DeviceState, DeviceClass, DEVICE)
typedef enum DeviceCategory {
DEVICE_CATEGORY_BRIDGE,
#include "qom/object.h"
#define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc"
-typedef struct LowRISCIbexSoCState LowRISCIbexSoCState;
-DECLARE_INSTANCE_CHECKER(LowRISCIbexSoCState, RISCV_IBEX_SOC,
- TYPE_RISCV_IBEX_SOC)
+OBJECT_DECLARE_SIMPLE_TYPE(LowRISCIbexSoCState, RISCV_IBEX_SOC)
struct LowRISCIbexSoCState {
/*< private >*/
#define TYPE_RISCV_HART_ARRAY "riscv.hart_array"
-typedef struct RISCVHartArrayState RISCVHartArrayState;
-DECLARE_INSTANCE_CHECKER(RISCVHartArrayState, RISCV_HART_ARRAY,
- TYPE_RISCV_HART_ARRAY)
+OBJECT_DECLARE_SIMPLE_TYPE(RISCVHartArrayState, RISCV_HART_ARRAY)
struct RISCVHartArrayState {
/*< private >*/
OBJECT_CHECK(SiFiveEState, (obj), TYPE_RISCV_E_MACHINE)
enum {
- SIFIVE_E_DEBUG,
- SIFIVE_E_MROM,
- SIFIVE_E_OTP,
- SIFIVE_E_CLINT,
- SIFIVE_E_PLIC,
- SIFIVE_E_AON,
- SIFIVE_E_PRCI,
- SIFIVE_E_OTP_CTRL,
- SIFIVE_E_GPIO0,
- SIFIVE_E_UART0,
- SIFIVE_E_QSPI0,
- SIFIVE_E_PWM0,
- SIFIVE_E_UART1,
- SIFIVE_E_QSPI1,
- SIFIVE_E_PWM1,
- SIFIVE_E_QSPI2,
- SIFIVE_E_PWM2,
- SIFIVE_E_XIP,
- SIFIVE_E_DTIM
+ SIFIVE_E_DEV_DEBUG,
+ SIFIVE_E_DEV_MROM,
+ SIFIVE_E_DEV_OTP,
+ SIFIVE_E_DEV_CLINT,
+ SIFIVE_E_DEV_PLIC,
+ SIFIVE_E_DEV_AON,
+ SIFIVE_E_DEV_PRCI,
+ SIFIVE_E_DEV_OTP_CTRL,
+ SIFIVE_E_DEV_GPIO0,
+ SIFIVE_E_DEV_UART0,
+ SIFIVE_E_DEV_QSPI0,
+ SIFIVE_E_DEV_PWM0,
+ SIFIVE_E_DEV_UART1,
+ SIFIVE_E_DEV_QSPI1,
+ SIFIVE_E_DEV_PWM1,
+ SIFIVE_E_DEV_QSPI2,
+ SIFIVE_E_DEV_PWM2,
+ SIFIVE_E_DEV_XIP,
+ SIFIVE_E_DEV_DTIM
};
enum {
} SiFiveUState;
enum {
- SIFIVE_U_DEBUG,
- SIFIVE_U_MROM,
- SIFIVE_U_CLINT,
- SIFIVE_U_L2CC,
- SIFIVE_U_PDMA,
- SIFIVE_U_L2LIM,
- SIFIVE_U_PLIC,
- SIFIVE_U_PRCI,
- SIFIVE_U_UART0,
- SIFIVE_U_UART1,
- SIFIVE_U_GPIO,
- SIFIVE_U_OTP,
- SIFIVE_U_DMC,
- SIFIVE_U_FLASH0,
- SIFIVE_U_DRAM,
- SIFIVE_U_GEM,
- SIFIVE_U_GEM_MGMT
+ SIFIVE_U_DEV_DEBUG,
+ SIFIVE_U_DEV_MROM,
+ SIFIVE_U_DEV_CLINT,
+ SIFIVE_U_DEV_L2CC,
+ SIFIVE_U_DEV_PDMA,
+ SIFIVE_U_DEV_L2LIM,
+ SIFIVE_U_DEV_PLIC,
+ SIFIVE_U_DEV_PRCI,
+ SIFIVE_U_DEV_UART0,
+ SIFIVE_U_DEV_UART1,
+ SIFIVE_U_DEV_GPIO,
+ SIFIVE_U_DEV_OTP,
+ SIFIVE_U_DEV_DMC,
+ SIFIVE_U_DEV_FLASH0,
+ SIFIVE_U_DEV_DRAM,
+ SIFIVE_U_DEV_GEM,
+ SIFIVE_U_DEV_GEM_MGMT
};
enum {
* @{
*/
-typedef struct AwRtcClass AwRtcClass;
-typedef struct AwRtcState AwRtcState;
-DECLARE_OBJ_CHECKERS(AwRtcState, AwRtcClass,
- AW_RTC, TYPE_AW_RTC)
+OBJECT_DECLARE_TYPE(AwRtcState, AwRtcClass, AW_RTC)
/** @} */
int offset;
};
-typedef struct AspeedRtcState AspeedRtcState;
#define TYPE_ASPEED_RTC "aspeed.rtc"
-DECLARE_INSTANCE_CHECKER(AspeedRtcState, ASPEED_RTC,
- TYPE_ASPEED_RTC)
+OBJECT_DECLARE_SIMPLE_TYPE(AspeedRtcState, ASPEED_RTC)
#endif /* HW_RTC_ASPEED_RTC_H */
#include "qom/object.h"
#define TYPE_GOLDFISH_RTC "goldfish_rtc"
-typedef struct GoldfishRTCState GoldfishRTCState;
-DECLARE_INSTANCE_CHECKER(GoldfishRTCState, GOLDFISH_RTC,
- TYPE_GOLDFISH_RTC)
+OBJECT_DECLARE_SIMPLE_TYPE(GoldfishRTCState, GOLDFISH_RTC)
struct GoldfishRTCState {
SysBusDevice parent_obj;
#include "qom/object.h"
#define TYPE_MC146818_RTC "mc146818rtc"
-typedef struct RTCState RTCState;
-DECLARE_INSTANCE_CHECKER(RTCState, MC146818_RTC,
- TYPE_MC146818_RTC)
+OBJECT_DECLARE_SIMPLE_TYPE(RTCState, MC146818_RTC)
struct RTCState {
ISADevice parent_obj;
#include "qom/object.h"
#define TYPE_PL031 "pl031"
-typedef struct PL031State PL031State;
-DECLARE_INSTANCE_CHECKER(PL031State, PL031,
- TYPE_PL031)
+OBJECT_DECLARE_SIMPLE_TYPE(PL031State, PL031)
struct PL031State {
SysBusDevice parent_obj;
#define TYPE_XLNX_ZYNQMP_RTC "xlnx-zynmp.rtc"
-typedef struct XlnxZynqMPRTC XlnxZynqMPRTC;
-DECLARE_INSTANCE_CHECKER(XlnxZynqMPRTC, XLNX_ZYNQMP_RTC,
- TYPE_XLNX_ZYNQMP_RTC)
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPRTC, XLNX_ZYNQMP_RTC)
REG32(SET_TIME_WRITE, 0x0)
REG32(SET_TIME_READ, 0x4)
#define TC_EWRITEA 0x0d /* Erase write alternate */
#define TC_WRITESF 0x11 /* Write structured field */
-typedef struct EmulatedCcw3270Class EmulatedCcw3270Class;
-typedef struct EmulatedCcw3270Device EmulatedCcw3270Device;
-DECLARE_OBJ_CHECKERS(EmulatedCcw3270Device, EmulatedCcw3270Class,
- EMULATED_CCW_3270, TYPE_EMULATED_CCW_3270)
+OBJECT_DECLARE_TYPE(EmulatedCcw3270Device, EmulatedCcw3270Class, EMULATED_CCW_3270)
struct EmulatedCcw3270Device {
CcwDevice parent_obj;
SysBusDevice sysbus_dev;
bool css_dev_path;
};
-typedef struct VirtualCssBridge VirtualCssBridge;
#define TYPE_VIRTUAL_CSS_BRIDGE "virtual-css-bridge"
-DECLARE_INSTANCE_CHECKER(VirtualCssBridge, VIRTUAL_CSS_BRIDGE,
- TYPE_VIRTUAL_CSS_BRIDGE)
+OBJECT_DECLARE_SIMPLE_TYPE(VirtualCssBridge, VIRTUAL_CSS_BRIDGE)
/* virtual css bus type */
struct VirtualCssBus {
BusState parent_obj;
};
-typedef struct VirtualCssBus VirtualCssBus;
#define TYPE_VIRTUAL_CSS_BUS "virtual-css-bus"
-DECLARE_INSTANCE_CHECKER(VirtualCssBus, VIRTUAL_CSS_BUS,
- TYPE_VIRTUAL_CSS_BUS)
+OBJECT_DECLARE_SIMPLE_TYPE(VirtualCssBus, VIRTUAL_CSS_BUS)
VirtualCssBus *virtual_css_bus_init(void);
#endif
#define TYPE_SCLP_EVENT "s390-sclp-event-type"
OBJECT_DECLARE_TYPE(SCLPEvent, SCLPEventClass,
- sclp_event, SCLP_EVENT)
+ SCLP_EVENT)
#define TYPE_SCLP_CPU_HOTPLUG "sclp-cpu-hotplug"
#define TYPE_SCLP_QUIESCE "sclpquiesce"
#define TYPE_S390_CCW_MACHINE "s390-ccw-machine"
-typedef struct S390CcwMachineClass S390CcwMachineClass;
-typedef struct S390CcwMachineState S390CcwMachineState;
-DECLARE_OBJ_CHECKERS(S390CcwMachineState, S390CcwMachineClass,
- S390_CCW_MACHINE, TYPE_S390_CCW_MACHINE)
+OBJECT_DECLARE_TYPE(S390CcwMachineState, S390CcwMachineClass, S390_CCW_MACHINE)
struct S390CcwMachineState {
#define TYPE_S390_FLIC_COMMON "s390-flic"
OBJECT_DECLARE_TYPE(S390FLICState, S390FLICStateClass,
- s390_flic_common, S390_FLIC_COMMON)
+ S390_FLIC_COMMON)
struct S390FLICState {
SysBusDevice parent_obj;
TYPE_KVM_S390_FLIC)
#define TYPE_QEMU_S390_FLIC "s390-flic-qemu"
-typedef struct QEMUS390FLICState QEMUS390FLICState;
-DECLARE_INSTANCE_CHECKER(QEMUS390FLICState, QEMU_S390_FLIC,
- TYPE_QEMU_S390_FLIC)
+OBJECT_DECLARE_SIMPLE_TYPE(QEMUS390FLICState, QEMU_S390_FLIC)
#define SIC_IRQ_MODE_ALL 0
#define SIC_IRQ_MODE_SINGLE 1
#define TYPE_SCLP "sclp"
OBJECT_DECLARE_TYPE(SCLPDevice, SCLPDeviceClass,
- sclp, SCLP)
+ SCLP)
struct SCLPEventFacility;
#define TYPE_QEMU_S390_STATTRIB "s390-storage_attributes-qemu"
#define TYPE_KVM_S390_STATTRIB "s390-storage_attributes-kvm"
-typedef struct S390StAttribClass S390StAttribClass;
-typedef struct S390StAttribState S390StAttribState;
-DECLARE_OBJ_CHECKERS(S390StAttribState, S390StAttribClass,
- S390_STATTRIB, TYPE_S390_STATTRIB)
+OBJECT_DECLARE_TYPE(S390StAttribState, S390StAttribClass, S390_STATTRIB)
struct S390StAttribState {
DeviceState parent_obj;
#include "qom/object.h"
#define TYPE_S390_SKEYS "s390-skeys"
-typedef struct S390SKeysClass S390SKeysClass;
-typedef struct S390SKeysState S390SKeysState;
-DECLARE_OBJ_CHECKERS(S390SKeysState, S390SKeysClass,
- S390_SKEYS, TYPE_S390_SKEYS)
+OBJECT_DECLARE_TYPE(S390SKeysState, S390SKeysClass, S390_SKEYS)
struct S390SKeysState {
DeviceState parent_obj;
} S390TOD;
#define TYPE_S390_TOD "s390-tod"
-typedef struct S390TODClass S390TODClass;
-typedef struct S390TODState S390TODState;
-DECLARE_OBJ_CHECKERS(S390TODState, S390TODClass,
- S390_TOD, TYPE_S390_TOD)
+OBJECT_DECLARE_TYPE(S390TODState, S390TODClass, S390_TOD)
#define TYPE_KVM_S390_TOD TYPE_S390_TOD "-kvm"
#define TYPE_QEMU_S390_TOD TYPE_S390_TOD "-qemu"
#include "qom/object.h"
#define TYPE_VFIO_CCW "vfio-ccw"
-typedef struct VFIOCCWDevice VFIOCCWDevice;
-DECLARE_INSTANCE_CHECKER(VFIOCCWDevice, VFIO_CCW,
- TYPE_VFIO_CCW)
+OBJECT_DECLARE_SIMPLE_TYPE(VFIOCCWDevice, VFIO_CCW)
#define TYPE_VFIO_CCW "vfio-ccw"
};
#define TYPE_ESP "esp"
-typedef struct SysBusESPState SysBusESPState;
-DECLARE_INSTANCE_CHECKER(SysBusESPState, ESP,
- TYPE_ESP)
+OBJECT_DECLARE_SIMPLE_TYPE(SysBusESPState, ESP)
struct SysBusESPState {
/*< private >*/
};
#define TYPE_SCSI_DEVICE "scsi-device"
-typedef struct SCSIDeviceClass SCSIDeviceClass;
-DECLARE_OBJ_CHECKERS(SCSIDevice, SCSIDeviceClass,
- SCSI_DEVICE, TYPE_SCSI_DEVICE)
+OBJECT_DECLARE_TYPE(SCSIDevice, SCSIDeviceClass, SCSI_DEVICE)
struct SCSIDeviceClass {
DeviceClass parent_class;
};
#define TYPE_SCSI_BUS "SCSI"
-DECLARE_INSTANCE_CHECKER(SCSIBus, SCSI_BUS,
- TYPE_SCSI_BUS)
+OBJECT_DECLARE_SIMPLE_TYPE(SCSIBus, SCSI_BUS)
struct SCSIBus {
BusState qbus;
* @{
*/
-typedef struct AwSdHostClass AwSdHostClass;
-typedef struct AwSdHostState AwSdHostState;
-DECLARE_OBJ_CHECKERS(AwSdHostState, AwSdHostClass,
- AW_SDHOST, TYPE_AW_SDHOST)
+OBJECT_DECLARE_TYPE(AwSdHostState, AwSdHostClass, AW_SDHOST)
/** @} */
#include "qom/object.h"
#define TYPE_ASPEED_SDHCI "aspeed.sdhci"
-typedef struct AspeedSDHCIState AspeedSDHCIState;
-DECLARE_INSTANCE_CHECKER(AspeedSDHCIState, ASPEED_SDHCI,
- TYPE_ASPEED_SDHCI)
+OBJECT_DECLARE_SIMPLE_TYPE(AspeedSDHCIState, ASPEED_SDHCI)
#define ASPEED_SDHCI_CAPABILITIES 0x01E80080
#define ASPEED_SDHCI_NUM_SLOTS 2
#include "qom/object.h"
#define TYPE_BCM2835_SDHOST "bcm2835-sdhost"
-typedef struct BCM2835SDHostState BCM2835SDHostState;
-DECLARE_INSTANCE_CHECKER(BCM2835SDHostState, BCM2835_SDHOST,
- TYPE_BCM2835_SDHOST)
+OBJECT_DECLARE_SIMPLE_TYPE(BCM2835SDHostState, BCM2835_SDHOST)
#define BCM2835_SDHOST_FIFO_LEN 16
uint8_t crc;
} SDRequest;
-typedef struct SDState SDState;
#define TYPE_SD_CARD "sd-card"
-typedef struct SDCardClass SDCardClass;
-DECLARE_OBJ_CHECKERS(SDState, SDCardClass,
- SD_CARD, TYPE_SD_CARD)
+OBJECT_DECLARE_TYPE(SDState, SDCardClass, SD_CARD)
struct SDCardClass {
/*< private >*/
#define TYPE_SD_BUS "sd-bus"
OBJECT_DECLARE_TYPE(SDBus, SDBusClass,
- sd_bus, SD_BUS)
+ SD_BUS)
struct SDBus {
BusState qbus;
#define DMA_REGS 4
#define TYPE_SPARC32_DMA_DEVICE "sparc32-dma-device"
-typedef struct DMADeviceState DMADeviceState;
-DECLARE_INSTANCE_CHECKER(DMADeviceState, SPARC32_DMA_DEVICE,
- TYPE_SPARC32_DMA_DEVICE)
+OBJECT_DECLARE_SIMPLE_TYPE(DMADeviceState, SPARC32_DMA_DEVICE)
struct DMADeviceState {
};
#define TYPE_SPARC32_ESPDMA_DEVICE "sparc32-espdma"
-typedef struct ESPDMADeviceState ESPDMADeviceState;
-DECLARE_INSTANCE_CHECKER(ESPDMADeviceState, SPARC32_ESPDMA_DEVICE,
- TYPE_SPARC32_ESPDMA_DEVICE)
+OBJECT_DECLARE_SIMPLE_TYPE(ESPDMADeviceState, SPARC32_ESPDMA_DEVICE)
struct ESPDMADeviceState {
DMADeviceState parent_obj;
};
#define TYPE_SPARC32_LEDMA_DEVICE "sparc32-ledma"
-typedef struct LEDMADeviceState LEDMADeviceState;
-DECLARE_INSTANCE_CHECKER(LEDMADeviceState, SPARC32_LEDMA_DEVICE,
- TYPE_SPARC32_LEDMA_DEVICE)
+OBJECT_DECLARE_SIMPLE_TYPE(LEDMADeviceState, SPARC32_LEDMA_DEVICE)
struct LEDMADeviceState {
DMADeviceState parent_obj;
};
#define TYPE_SPARC32_DMA "sparc32-dma"
-typedef struct SPARC32DMAState SPARC32DMAState;
-DECLARE_INSTANCE_CHECKER(SPARC32DMAState, SPARC32_DMA,
- TYPE_SPARC32_DMA)
+OBJECT_DECLARE_SIMPLE_TYPE(SPARC32DMAState, SPARC32_DMA)
struct SPARC32DMAState {
SysBusDevice parent_obj;
} AspeedSMCFlash;
#define TYPE_ASPEED_SMC "aspeed.smc"
-typedef struct AspeedSMCClass AspeedSMCClass;
-typedef struct AspeedSMCState AspeedSMCState;
-DECLARE_OBJ_CHECKERS(AspeedSMCState, AspeedSMCClass,
- ASPEED_SMC, TYPE_ASPEED_SMC)
+OBJECT_DECLARE_TYPE(AspeedSMCState, AspeedSMCClass, ASPEED_SMC)
struct AspeedSMCClass {
SysBusDevice parent_obj;
#define EXTRACT(value, name) extract32(value, name##_SHIFT, name##_LENGTH)
#define TYPE_IMX_SPI "imx.spi"
-typedef struct IMXSPIState IMXSPIState;
-DECLARE_INSTANCE_CHECKER(IMXSPIState, IMX_SPI,
- TYPE_IMX_SPI)
+OBJECT_DECLARE_SIMPLE_TYPE(IMXSPIState, IMX_SPI)
struct IMXSPIState {
/* <private> */
#include "qom/object.h"
#define TYPE_MSS_SPI "mss-spi"
-typedef struct MSSSpiState MSSSpiState;
-DECLARE_INSTANCE_CHECKER(MSSSpiState, MSS_SPI,
- TYPE_MSS_SPI)
+OBJECT_DECLARE_SIMPLE_TYPE(MSSSpiState, MSS_SPI)
#define R_SPI_MAX 16
#include "qom/object.h"
#define TYPE_PL022 "pl022"
-typedef struct PL022State PL022State;
-DECLARE_INSTANCE_CHECKER(PL022State, PL022,
- TYPE_PL022)
+OBJECT_DECLARE_SIMPLE_TYPE(PL022State, PL022)
struct PL022State {
SysBusDevice parent_obj;
#define TYPE_SSI_SLAVE "ssi-slave"
OBJECT_DECLARE_TYPE(SSISlave, SSISlaveClass,
- ssi_slave, SSI_SLAVE)
+ SSI_SLAVE)
#define SSI_GPIO_CS "ssi-gpio-cs"
#define STM_SPI_SR_RXNE 1
#define TYPE_STM32F2XX_SPI "stm32f2xx-spi"
-typedef struct STM32F2XXSPIState STM32F2XXSPIState;
-DECLARE_INSTANCE_CHECKER(STM32F2XXSPIState, STM32F2XX_SPI,
- TYPE_STM32F2XX_SPI)
+OBJECT_DECLARE_SIMPLE_TYPE(STM32F2XXSPIState, STM32F2XX_SPI)
struct STM32F2XXSPIState {
/* <private> */
uint32_t dma_burst_size;
uint8_t dma_buf[QSPI_DMA_MAX_BURST_SIZE];
};
-typedef struct XlnxZynqMPQSPIPS XlnxZynqMPQSPIPS;
struct XilinxSPIPSClass {
SysBusDeviceClass parent_class;
uint32_t rx_fifo_size;
uint32_t tx_fifo_size;
};
-typedef struct XilinxSPIPSClass XilinxSPIPSClass;
#define TYPE_XILINX_SPIPS "xlnx.ps7-spi"
#define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi"
#define TYPE_XLNX_ZYNQMP_QSPIPS "xlnx.usmp-gqspi"
-DECLARE_OBJ_CHECKERS(XilinxSPIPS, XilinxSPIPSClass,
- XILINX_SPIPS, TYPE_XILINX_SPIPS)
+OBJECT_DECLARE_TYPE(XilinxSPIPS, XilinxSPIPSClass, XILINX_SPIPS)
-DECLARE_INSTANCE_CHECKER(XilinxQSPIPS, XILINX_QSPIPS,
- TYPE_XILINX_QSPIPS)
+OBJECT_DECLARE_SIMPLE_TYPE(XilinxQSPIPS, XILINX_QSPIPS)
-DECLARE_INSTANCE_CHECKER(XlnxZynqMPQSPIPS, XLNX_ZYNQMP_QSPIPS,
- TYPE_XLNX_ZYNQMP_QSPIPS)
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPQSPIPS, XLNX_ZYNQMP_QSPIPS)
#endif /* XILINX_SPIPS_H */
#define TYPE_SYS_BUS_DEVICE "sys-bus-device"
OBJECT_DECLARE_TYPE(SysBusDevice, SysBusDeviceClass,
- sys_bus_device, SYS_BUS_DEVICE)
+ SYS_BUS_DEVICE)
/**
* SysBusDeviceClass:
#define A9_GTIMER_MAX_CPUS 4
#define TYPE_A9_GTIMER "arm.cortex-a9-global-timer"
-typedef struct A9GTimerState A9GTimerState;
-DECLARE_INSTANCE_CHECKER(A9GTimerState, A9_GTIMER,
- TYPE_A9_GTIMER)
+OBJECT_DECLARE_SIMPLE_TYPE(A9GTimerState, A9_GTIMER)
#define R_COUNTER_LO 0x00
#define R_COUNTER_HI 0x04
#include "qom/object.h"
#define TYPE_AW_A10_PIT "allwinner-A10-timer"
-typedef struct AwA10PITState AwA10PITState;
-DECLARE_INSTANCE_CHECKER(AwA10PITState, AW_A10_PIT,
- TYPE_AW_A10_PIT)
+OBJECT_DECLARE_SIMPLE_TYPE(AwA10PITState, AW_A10_PIT)
#define AW_A10_PIT_TIMER_NR 6
#define AW_A10_PIT_TIMER_IRQ 0x1
} TimerBlock;
#define TYPE_ARM_MPTIMER "arm_mptimer"
-typedef struct ARMMPTimerState ARMMPTimerState;
-DECLARE_INSTANCE_CHECKER(ARMMPTimerState, ARM_MPTIMER,
- TYPE_ARM_MPTIMER)
+OBJECT_DECLARE_SIMPLE_TYPE(ARMMPTimerState, ARM_MPTIMER)
struct ARMMPTimerState {
/*< private >*/
#define TYPE_SYSTICK "armv7m_systick"
-typedef struct SysTickState SysTickState;
-DECLARE_INSTANCE_CHECKER(SysTickState, SYSTICK,
- TYPE_SYSTICK)
+OBJECT_DECLARE_SIMPLE_TYPE(SysTickState, SYSTICK)
struct SysTickState {
/*< private >*/
#include "qom/object.h"
#define TYPE_ASPEED_TIMER "aspeed.timer"
-typedef struct AspeedTimerClass AspeedTimerClass;
-typedef struct AspeedTimerCtrlState AspeedTimerCtrlState;
-DECLARE_OBJ_CHECKERS(AspeedTimerCtrlState, AspeedTimerClass,
- ASPEED_TIMER, TYPE_ASPEED_TIMER)
+OBJECT_DECLARE_TYPE(AspeedTimerCtrlState, AspeedTimerClass, ASPEED_TIMER)
#define TYPE_ASPEED_2400_TIMER TYPE_ASPEED_TIMER "-ast2400"
#define TYPE_ASPEED_2500_TIMER TYPE_ASPEED_TIMER "-ast2500"
#define TYPE_ASPEED_2600_TIMER TYPE_ASPEED_TIMER "-ast2600"
};
#define TYPE_AVR_TIMER16 "avr-timer16"
-typedef struct AVRTimer16State AVRTimer16State;
-DECLARE_INSTANCE_CHECKER(AVRTimer16State, AVR_TIMER16,
- TYPE_AVR_TIMER16)
+OBJECT_DECLARE_SIMPLE_TYPE(AVRTimer16State, AVR_TIMER16)
struct AVRTimer16State {
/* <private> */
#include "qom/object.h"
#define TYPE_BCM2835_SYSTIMER "bcm2835-sys-timer"
-typedef struct BCM2835SystemTimerState BCM2835SystemTimerState;
-DECLARE_INSTANCE_CHECKER(BCM2835SystemTimerState, BCM2835_SYSTIMER,
- TYPE_BCM2835_SYSTIMER)
+OBJECT_DECLARE_SIMPLE_TYPE(BCM2835SystemTimerState, BCM2835_SYSTIMER)
struct BCM2835SystemTimerState {
/*< private >*/
#include "qom/object.h"
#define TYPE_CMSDK_APB_DUALTIMER "cmsdk-apb-dualtimer"
-typedef struct CMSDKAPBDualTimer CMSDKAPBDualTimer;
-DECLARE_INSTANCE_CHECKER(CMSDKAPBDualTimer, CMSDK_APB_DUALTIMER,
- TYPE_CMSDK_APB_DUALTIMER)
+OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBDualTimer, CMSDK_APB_DUALTIMER)
/* One of the two identical timer modules in the dual-timer module */
#include "qom/object.h"
#define TYPE_CMSDK_APB_TIMER "cmsdk-apb-timer"
-typedef struct CMSDKAPBTIMER CMSDKAPBTIMER;
-DECLARE_INSTANCE_CHECKER(CMSDKAPBTIMER, CMSDK_APB_TIMER,
- TYPE_CMSDK_APB_TIMER)
+OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBTIMER, CMSDK_APB_TIMER)
struct CMSDKAPBTIMER {
/*< private >*/
#include "qom/object.h"
#define TYPE_DIGIC_TIMER "digic-timer"
-typedef struct DigicTimerState DigicTimerState;
-DECLARE_INSTANCE_CHECKER(DigicTimerState, DIGIC_TIMER,
- TYPE_DIGIC_TIMER)
+OBJECT_DECLARE_SIMPLE_TYPE(DigicTimerState, DIGIC_TIMER)
#define DIGIC_TIMER_CONTROL 0x00
#define DIGIC_TIMER_CONTROL_RST 0x80000000
} PITChannelInfo;
#define TYPE_PIT_COMMON "pit-common"
-typedef struct PITCommonState PITCommonState;
-typedef struct PITCommonClass PITCommonClass;
-DECLARE_OBJ_CHECKERS(PITCommonState, PITCommonClass,
- PIT_COMMON, TYPE_PIT_COMMON)
+OBJECT_DECLARE_TYPE(PITCommonState, PITCommonClass, PIT_COMMON)
#define TYPE_I8254 "isa-pit"
#define TYPE_KVM_I8254 "kvm-pit"
#define EPIT_TIMER_MAX 0XFFFFFFFFUL
#define TYPE_IMX_EPIT "imx.epit"
-typedef struct IMXEPITState IMXEPITState;
-DECLARE_INSTANCE_CHECKER(IMXEPITState, IMX_EPIT,
- TYPE_IMX_EPIT)
+OBJECT_DECLARE_SIMPLE_TYPE(IMXEPITState, IMX_EPIT)
struct IMXEPITState {
/*< private >*/
#include "qom/object.h"
#define TYPE_MSS_TIMER "mss-timer"
-typedef struct MSSTimerState MSSTimerState;
-DECLARE_INSTANCE_CHECKER(MSSTimerState, MSS_TIMER,
- TYPE_MSS_TIMER)
+OBJECT_DECLARE_SIMPLE_TYPE(MSSTimerState, MSS_TIMER)
/*
* There are two 32-bit down counting timers.
#include "qemu/timer.h"
#include "qom/object.h"
#define TYPE_NRF51_TIMER "nrf51_soc.timer"
-typedef struct NRF51TimerState NRF51TimerState;
-DECLARE_INSTANCE_CHECKER(NRF51TimerState, NRF51_TIMER,
- TYPE_NRF51_TIMER)
+OBJECT_DECLARE_SIMPLE_TYPE(NRF51TimerState, NRF51_TIMER)
#define NRF51_TIMER_REG_COUNT 4
#define USB_INTERFACE_INVALID 255
-typedef struct USBBus USBBus;
typedef struct USBBusOps USBBusOps;
typedef struct USBPort USBPort;
typedef struct USBDevice USBDevice;
};
#define TYPE_USB_DEVICE "usb-device"
-typedef struct USBDeviceClass USBDeviceClass;
-DECLARE_OBJ_CHECKERS(USBDevice, USBDeviceClass,
- USB_DEVICE, TYPE_USB_DEVICE)
+OBJECT_DECLARE_TYPE(USBDevice, USBDeviceClass, USB_DEVICE)
typedef void (*USBDeviceRealize)(USBDevice *dev, Error **errp);
typedef void (*USBDeviceUnrealize)(USBDevice *dev);
/* usb-bus.c */
#define TYPE_USB_BUS "usb-bus"
-DECLARE_INSTANCE_CHECKER(USBBus, USB_BUS,
- TYPE_USB_BUS)
+OBJECT_DECLARE_SIMPLE_TYPE(USBBus, USB_BUS)
struct USBBus {
BusState qbus;
MemoryRegion iomem[3];
};
-typedef struct ChipideaState ChipideaState;
#define TYPE_CHIPIDEA "usb-chipidea"
-DECLARE_INSTANCE_CHECKER(ChipideaState, CHIPIDEA,
- TYPE_CHIPIDEA)
+OBJECT_DECLARE_SIMPLE_TYPE(ChipideaState, CHIPIDEA)
#endif /* CHIPIDEA_H */
#define USBPHY_CTRL_SFTRST BIT(31)
#define TYPE_IMX_USBPHY "imx.usbphy"
-typedef struct IMXUSBPHYState IMXUSBPHYState;
-DECLARE_INSTANCE_CHECKER(IMXUSBPHYState, IMX_USBPHY,
- TYPE_IMX_USBPHY)
+OBJECT_DECLARE_SIMPLE_TYPE(IMXUSBPHYState, IMX_USBPHY)
struct IMXUSBPHYState {
/* <private> */
#include "qom/object.h"
#define TYPE_VHOST_SCSI_COMMON "vhost-scsi-common"
-typedef struct VHostSCSICommon VHostSCSICommon;
-DECLARE_INSTANCE_CHECKER(VHostSCSICommon, VHOST_SCSI_COMMON,
- TYPE_VHOST_SCSI_COMMON)
+OBJECT_DECLARE_SIMPLE_TYPE(VHostSCSICommon, VHOST_SCSI_COMMON)
struct VHostSCSICommon {
VirtIOSCSICommon parent_obj;
};
#define TYPE_VHOST_SCSI "vhost-scsi"
-typedef struct VHostSCSI VHostSCSI;
-DECLARE_INSTANCE_CHECKER(VHostSCSI, VHOST_SCSI,
- TYPE_VHOST_SCSI)
+OBJECT_DECLARE_SIMPLE_TYPE(VHostSCSI, VHOST_SCSI)
struct VHostSCSI {
VHostSCSICommon parent_obj;
#include "qom/object.h"
#define TYPE_VHOST_USER_BLK "vhost-user-blk"
-typedef struct VHostUserBlk VHostUserBlk;
-DECLARE_INSTANCE_CHECKER(VHostUserBlk, VHOST_USER_BLK,
- TYPE_VHOST_USER_BLK)
+OBJECT_DECLARE_SIMPLE_TYPE(VHostUserBlk, VHOST_USER_BLK)
#define VHOST_USER_BLK_AUTO_NUM_QUEUES UINT16_MAX
#include "qom/object.h"
#define TYPE_VHOST_USER_FS "vhost-user-fs-device"
-typedef struct VHostUserFS VHostUserFS;
-DECLARE_INSTANCE_CHECKER(VHostUserFS, VHOST_USER_FS,
- TYPE_VHOST_USER_FS)
+OBJECT_DECLARE_SIMPLE_TYPE(VHostUserFS, VHOST_USER_FS)
typedef struct {
CharBackend chardev;
#include "qom/object.h"
#define TYPE_VHOST_USER_SCSI "vhost-user-scsi"
-typedef struct VHostUserSCSI VHostUserSCSI;
-DECLARE_INSTANCE_CHECKER(VHostUserSCSI, VHOST_USER_SCSI,
- TYPE_VHOST_USER_SCSI)
+OBJECT_DECLARE_SIMPLE_TYPE(VHostUserSCSI, VHOST_USER_SCSI)
struct VHostUserSCSI {
VHostSCSICommon parent_obj;
#include "qom/object.h"
#define TYPE_VHOST_USER_VSOCK "vhost-user-vsock-device"
-typedef struct VHostUserVSock VHostUserVSock;
-DECLARE_INSTANCE_CHECKER(VHostUserVSock, VHOST_USER_VSOCK,
- TYPE_VHOST_USER_VSOCK)
+OBJECT_DECLARE_SIMPLE_TYPE(VHostUserVSock, VHOST_USER_VSOCK)
typedef struct {
CharBackend chardev;
#include "qom/object.h"
#define TYPE_VHOST_VSOCK_COMMON "vhost-vsock-common"
-typedef struct VHostVSockCommon VHostVSockCommon;
-DECLARE_INSTANCE_CHECKER(VHostVSockCommon, VHOST_VSOCK_COMMON,
- TYPE_VHOST_VSOCK_COMMON)
+OBJECT_DECLARE_SIMPLE_TYPE(VHostVSockCommon, VHOST_VSOCK_COMMON)
enum {
VHOST_VSOCK_SAVEVM_VERSION = 0,
#include "qom/object.h"
#define TYPE_VHOST_VSOCK "vhost-vsock-device"
-typedef struct VHostVSock VHostVSock;
-DECLARE_INSTANCE_CHECKER(VHostVSock, VHOST_VSOCK,
- TYPE_VHOST_VSOCK)
+OBJECT_DECLARE_SIMPLE_TYPE(VHostVSock, VHOST_VSOCK)
typedef struct {
uint64_t guest_cid;
#include "qom/object.h"
#define TYPE_VIRTIO_BALLOON "virtio-balloon-device"
-typedef struct VirtIOBalloon VirtIOBalloon;
-DECLARE_INSTANCE_CHECKER(VirtIOBalloon, VIRTIO_BALLOON,
- TYPE_VIRTIO_BALLOON)
+OBJECT_DECLARE_SIMPLE_TYPE(VirtIOBalloon, VIRTIO_BALLOON)
#define VIRTIO_BALLOON_FREE_PAGE_HINT_CMD_ID_MIN 0x80000000
#include "qom/object.h"
#define TYPE_VIRTIO_BLK "virtio-blk-device"
-typedef struct VirtIOBlock VirtIOBlock;
-DECLARE_INSTANCE_CHECKER(VirtIOBlock, VIRTIO_BLK,
- TYPE_VIRTIO_BLK)
+OBJECT_DECLARE_SIMPLE_TYPE(VirtIOBlock, VIRTIO_BLK)
/* This is the last element of the write scatter-gather list */
struct virtio_blk_inhdr
#define TYPE_VIRTIO_CRYPTO "virtio-crypto-device"
-typedef struct VirtIOCrypto VirtIOCrypto;
-DECLARE_INSTANCE_CHECKER(VirtIOCrypto, VIRTIO_CRYPTO,
- TYPE_VIRTIO_CRYPTO)
+OBJECT_DECLARE_SIMPLE_TYPE(VirtIOCrypto, VIRTIO_CRYPTO)
#define VIRTIO_CRYPTO_GET_PARENT_CLASS(obj) \
OBJECT_GET_PARENT_CLASS(obj, TYPE_VIRTIO_CRYPTO)
#include "hw/virtio/virtio-gpu.h"
#include "qom/object.h"
-typedef struct VirtIOGPUPCIBase VirtIOGPUPCIBase;
/*
* virtio-gpu-pci-base: This extends VirtioPCIProxy.
*/
#define TYPE_VIRTIO_GPU_PCI_BASE "virtio-gpu-pci-base"
-DECLARE_INSTANCE_CHECKER(VirtIOGPUPCIBase, VIRTIO_GPU_PCI_BASE,
- TYPE_VIRTIO_GPU_PCI_BASE)
+OBJECT_DECLARE_SIMPLE_TYPE(VirtIOGPUPCIBase, VIRTIO_GPU_PCI_BASE)
struct VirtIOGPUPCIBase {
VirtIOPCIProxy parent_obj;
#define TYPE_VIRTIO_GPU_BASE "virtio-gpu-base"
OBJECT_DECLARE_TYPE(VirtIOGPUBase, VirtIOGPUBaseClass,
- virtio_gpu_base, VIRTIO_GPU_BASE)
+ VIRTIO_GPU_BASE)
#define TYPE_VIRTIO_GPU "virtio-gpu-device"
-typedef struct VirtIOGPU VirtIOGPU;
-DECLARE_INSTANCE_CHECKER(VirtIOGPU, VIRTIO_GPU,
- TYPE_VIRTIO_GPU)
+OBJECT_DECLARE_SIMPLE_TYPE(VirtIOGPU, VIRTIO_GPU)
#define TYPE_VHOST_USER_GPU "vhost-user-gpu"
-typedef struct VhostUserGPU VhostUserGPU;
-DECLARE_INSTANCE_CHECKER(VhostUserGPU, VHOST_USER_GPU,
- TYPE_VHOST_USER_GPU)
+OBJECT_DECLARE_SIMPLE_TYPE(VhostUserGPU, VHOST_USER_GPU)
#define VIRTIO_ID_GPU 16
#define TYPE_VIRTIO_INPUT "virtio-input-device"
OBJECT_DECLARE_TYPE(VirtIOInput, VirtIOInputClass,
- virtio_input, VIRTIO_INPUT)
+ VIRTIO_INPUT)
#define VIRTIO_INPUT_GET_PARENT_CLASS(obj) \
OBJECT_GET_PARENT_CLASS(obj, TYPE_VIRTIO_INPUT)
#define TYPE_VIRTIO_MOUSE "virtio-mouse-device"
#define TYPE_VIRTIO_TABLET "virtio-tablet-device"
-typedef struct VirtIOInputHID VirtIOInputHID;
-DECLARE_INSTANCE_CHECKER(VirtIOInputHID, VIRTIO_INPUT_HID,
- TYPE_VIRTIO_INPUT_HID)
+OBJECT_DECLARE_SIMPLE_TYPE(VirtIOInputHID, VIRTIO_INPUT_HID)
#define VIRTIO_INPUT_HID_GET_PARENT_CLASS(obj) \
OBJECT_GET_PARENT_CLASS(obj, TYPE_VIRTIO_INPUT_HID)
#define TYPE_VIRTIO_INPUT_HOST "virtio-input-host-device"
-typedef struct VirtIOInputHost VirtIOInputHost;
-DECLARE_INSTANCE_CHECKER(VirtIOInputHost, VIRTIO_INPUT_HOST,
- TYPE_VIRTIO_INPUT_HOST)
+OBJECT_DECLARE_SIMPLE_TYPE(VirtIOInputHost, VIRTIO_INPUT_HOST)
#define VIRTIO_INPUT_HOST_GET_PARENT_CLASS(obj) \
OBJECT_GET_PARENT_CLASS(obj, TYPE_VIRTIO_INPUT_HOST)
#define TYPE_VHOST_USER_INPUT "vhost-user-input"
-typedef struct VHostUserInput VHostUserInput;
-DECLARE_INSTANCE_CHECKER(VHostUserInput, VHOST_USER_INPUT,
- TYPE_VHOST_USER_INPUT)
+OBJECT_DECLARE_SIMPLE_TYPE(VHostUserInput, VHOST_USER_INPUT)
#define VHOST_USER_INPUT_GET_PARENT_CLASS(obj) \
OBJECT_GET_PARENT_CLASS(obj, TYPE_VHOST_USER_INPUT)
#define TYPE_VIRTIO_IOMMU "virtio-iommu-device"
#define TYPE_VIRTIO_IOMMU_PCI "virtio-iommu-device-base"
-typedef struct VirtIOIOMMU VirtIOIOMMU;
-DECLARE_INSTANCE_CHECKER(VirtIOIOMMU, VIRTIO_IOMMU,
- TYPE_VIRTIO_IOMMU)
+OBJECT_DECLARE_SIMPLE_TYPE(VirtIOIOMMU, VIRTIO_IOMMU)
#define TYPE_VIRTIO_IOMMU_MEMORY_REGION "virtio-iommu-memory-region"
#define TYPE_VIRTIO_MEM "virtio-mem"
OBJECT_DECLARE_TYPE(VirtIOMEM, VirtIOMEMClass,
- virtio_mem, VIRTIO_MEM)
+ VIRTIO_MEM)
#define VIRTIO_MEM_MEMDEV_PROP "memdev"
#define VIRTIO_MEM_NODE_PROP "node"
/* virtio-mmio */
#define TYPE_VIRTIO_MMIO "virtio-mmio"
-typedef struct VirtIOMMIOProxy VirtIOMMIOProxy;
-DECLARE_INSTANCE_CHECKER(VirtIOMMIOProxy, VIRTIO_MMIO,
- TYPE_VIRTIO_MMIO)
+OBJECT_DECLARE_SIMPLE_TYPE(VirtIOMMIOProxy, VIRTIO_MMIO)
#define VIRT_MAGIC 0x74726976 /* 'virt' */
#define VIRT_VERSION 2
#include "qom/object.h"
#define TYPE_VIRTIO_NET "virtio-net-device"
-typedef struct VirtIONet VirtIONet;
-DECLARE_INSTANCE_CHECKER(VirtIONet, VIRTIO_NET,
- TYPE_VIRTIO_NET)
+OBJECT_DECLARE_SIMPLE_TYPE(VirtIONet, VIRTIO_NET)
#define TX_TIMER_INTERVAL 150000 /* 150 us */
#define TYPE_VIRTIO_PMEM "virtio-pmem"
OBJECT_DECLARE_TYPE(VirtIOPMEM, VirtIOPMEMClass,
- virtio_pmem, VIRTIO_PMEM)
+ VIRTIO_PMEM)
#define VIRTIO_PMEM_ADDR_PROP "memaddr"
#define VIRTIO_PMEM_MEMDEV_PROP "memdev"
#include "qom/object.h"
#define TYPE_VIRTIO_RNG "virtio-rng-device"
-typedef struct VirtIORNG VirtIORNG;
-DECLARE_INSTANCE_CHECKER(VirtIORNG, VIRTIO_RNG,
- TYPE_VIRTIO_RNG)
+OBJECT_DECLARE_SIMPLE_TYPE(VirtIORNG, VIRTIO_RNG)
#define VIRTIO_RNG_GET_PARENT_CLASS(obj) \
OBJECT_GET_PARENT_CLASS(obj, TYPE_VIRTIO_RNG)
#include "sysemu/iothread.h"
#define TYPE_VIRTIO_SCSI_COMMON "virtio-scsi-common"
-typedef struct VirtIOSCSICommon VirtIOSCSICommon;
-DECLARE_INSTANCE_CHECKER(VirtIOSCSICommon, VIRTIO_SCSI_COMMON,
- TYPE_VIRTIO_SCSI_COMMON)
+OBJECT_DECLARE_SIMPLE_TYPE(VirtIOSCSICommon, VIRTIO_SCSI_COMMON)
#define TYPE_VIRTIO_SCSI "virtio-scsi-device"
-typedef struct VirtIOSCSI VirtIOSCSI;
-DECLARE_INSTANCE_CHECKER(VirtIOSCSI, VIRTIO_SCSI,
- TYPE_VIRTIO_SCSI)
+OBJECT_DECLARE_SIMPLE_TYPE(VirtIOSCSI, VIRTIO_SCSI)
#define VIRTIO_SCSI_MAX_CHANNEL 0
#define VIRTIO_SCSI_MAX_TARGET 255
#define TYPE_VIRTIO_SERIAL_PORT "virtio-serial-port"
OBJECT_DECLARE_TYPE(VirtIOSerialPort, VirtIOSerialPortClass,
- virtio_serial_port, VIRTIO_SERIAL_PORT)
+ VIRTIO_SERIAL_PORT)
typedef struct VirtIOSerial VirtIOSerial;
#define TYPE_VIRTIO_SERIAL_BUS "virtio-serial-bus"
-typedef struct VirtIOSerialBus VirtIOSerialBus;
-DECLARE_INSTANCE_CHECKER(VirtIOSerialBus, VIRTIO_SERIAL_BUS,
- TYPE_VIRTIO_SERIAL_BUS)
+OBJECT_DECLARE_SIMPLE_TYPE(VirtIOSerialBus, VIRTIO_SERIAL_BUS)
struct VirtIOSerialPortClass {
void virtio_serial_throttle_port(VirtIOSerialPort *port, bool throttle);
#define TYPE_VIRTIO_SERIAL "virtio-serial-device"
-DECLARE_INSTANCE_CHECKER(VirtIOSerial, VIRTIO_SERIAL,
- TYPE_VIRTIO_SERIAL)
+OBJECT_DECLARE_SIMPLE_TYPE(VirtIOSerial, VIRTIO_SERIAL)
#endif
#define VIRTIO_NO_VECTOR 0xffff
#define TYPE_VIRTIO_DEVICE "virtio-device"
-typedef struct VirtioDeviceClass VirtioDeviceClass;
-DECLARE_OBJ_CHECKERS(VirtIODevice, VirtioDeviceClass,
- VIRTIO_DEVICE, TYPE_VIRTIO_DEVICE)
+OBJECT_DECLARE_TYPE(VirtIODevice, VirtioDeviceClass, VIRTIO_DEVICE)
enum virtio_device_endian {
VIRTIO_DEVICE_ENDIAN_UNKNOWN,
#include "qom/object.h"
#define TYPE_CMSDK_APB_WATCHDOG "cmsdk-apb-watchdog"
-typedef struct CMSDKAPBWatchdog CMSDKAPBWatchdog;
-DECLARE_INSTANCE_CHECKER(CMSDKAPBWatchdog, CMSDK_APB_WATCHDOG,
- TYPE_CMSDK_APB_WATCHDOG)
+OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBWatchdog, CMSDK_APB_WATCHDOG)
/*
* This shares the same struct (and cast macro) as the base
#include "qom/object.h"
#define TYPE_ASPEED_WDT "aspeed.wdt"
-typedef struct AspeedWDTClass AspeedWDTClass;
-typedef struct AspeedWDTState AspeedWDTState;
-DECLARE_OBJ_CHECKERS(AspeedWDTState, AspeedWDTClass,
- ASPEED_WDT, TYPE_ASPEED_WDT)
+OBJECT_DECLARE_TYPE(AspeedWDTState, AspeedWDTClass, ASPEED_WDT)
#define TYPE_ASPEED_2400_WDT TYPE_ASPEED_WDT "-ast2400"
#define TYPE_ASPEED_2500_WDT TYPE_ASPEED_WDT "-ast2500"
#define TYPE_ASPEED_2600_WDT TYPE_ASPEED_WDT "-ast2600"
#include "qom/object.h"
#define TYPE_IMX2_WDT "imx2.wdt"
-typedef struct IMX2WdtState IMX2WdtState;
-DECLARE_INSTANCE_CHECKER(IMX2WdtState, IMX2_WDT,
- TYPE_IMX2_WDT)
+OBJECT_DECLARE_SIMPLE_TYPE(IMX2WdtState, IMX2_WDT)
enum IMX2WdtRegisters {
IMX2_WDT_WCR = 0x0000, /* Control Register */
XenBlockDeviceRealize realize;
XenBlockDeviceUnrealize unrealize;
};
-typedef struct XenBlockDeviceClass XenBlockDeviceClass;
#define TYPE_XEN_BLOCK_DEVICE "xen-block"
-DECLARE_OBJ_CHECKERS(XenBlockDevice, XenBlockDeviceClass,
- XEN_BLOCK_DEVICE, TYPE_XEN_BLOCK_DEVICE)
+OBJECT_DECLARE_TYPE(XenBlockDevice, XenBlockDeviceClass, XEN_BLOCK_DEVICE)
struct XenDiskDevice {
XenBlockDevice blockdev;
};
-typedef struct XenDiskDevice XenDiskDevice;
#define TYPE_XEN_DISK_DEVICE "xen-disk"
-DECLARE_INSTANCE_CHECKER(XenDiskDevice, XEN_DISK_DEVICE,
- TYPE_XEN_DISK_DEVICE)
+OBJECT_DECLARE_SIMPLE_TYPE(XenDiskDevice, XEN_DISK_DEVICE)
struct XenCDRomDevice {
XenBlockDevice blockdev;
};
-typedef struct XenCDRomDevice XenCDRomDevice;
#define TYPE_XEN_CDROM_DEVICE "xen-cdrom"
-DECLARE_INSTANCE_CHECKER(XenCDRomDevice, XEN_CDROM_DEVICE,
- TYPE_XEN_CDROM_DEVICE)
+OBJECT_DECLARE_SIMPLE_TYPE(XenCDRomDevice, XEN_CDROM_DEVICE)
#endif /* HW_XEN_BLOCK_H */
XenDeviceFrontendChanged frontend_changed;
XenDeviceUnrealize unrealize;
};
-typedef struct XenDeviceClass XenDeviceClass;
#define TYPE_XEN_DEVICE "xen-device"
-DECLARE_OBJ_CHECKERS(XenDevice, XenDeviceClass,
- XEN_DEVICE, TYPE_XEN_DEVICE)
+OBJECT_DECLARE_TYPE(XenDevice, XenDeviceClass, XEN_DEVICE)
struct XenBus {
BusState qbus;
#define TYPE_XEN_BUS "xen-bus"
OBJECT_DECLARE_TYPE(XenBus, XenBusClass,
- xen_bus, XEN_BUS)
+ XEN_BUS)
void xen_bus_init(void);
#include "qom/object.h"
#define TYPE_QIO_CHANNEL_BUFFER "qio-channel-buffer"
-typedef struct QIOChannelBuffer QIOChannelBuffer;
-DECLARE_INSTANCE_CHECKER(QIOChannelBuffer, QIO_CHANNEL_BUFFER,
- TYPE_QIO_CHANNEL_BUFFER)
+OBJECT_DECLARE_SIMPLE_TYPE(QIOChannelBuffer, QIO_CHANNEL_BUFFER)
/**
#include "qom/object.h"
#define TYPE_QIO_CHANNEL_COMMAND "qio-channel-command"
-typedef struct QIOChannelCommand QIOChannelCommand;
-DECLARE_INSTANCE_CHECKER(QIOChannelCommand, QIO_CHANNEL_COMMAND,
- TYPE_QIO_CHANNEL_COMMAND)
+OBJECT_DECLARE_SIMPLE_TYPE(QIOChannelCommand, QIO_CHANNEL_COMMAND)
#include "qom/object.h"
#define TYPE_QIO_CHANNEL_FILE "qio-channel-file"
-typedef struct QIOChannelFile QIOChannelFile;
-DECLARE_INSTANCE_CHECKER(QIOChannelFile, QIO_CHANNEL_FILE,
- TYPE_QIO_CHANNEL_FILE)
+OBJECT_DECLARE_SIMPLE_TYPE(QIOChannelFile, QIO_CHANNEL_FILE)
/**
#include "qom/object.h"
#define TYPE_QIO_CHANNEL_SOCKET "qio-channel-socket"
-typedef struct QIOChannelSocket QIOChannelSocket;
-DECLARE_INSTANCE_CHECKER(QIOChannelSocket, QIO_CHANNEL_SOCKET,
- TYPE_QIO_CHANNEL_SOCKET)
+OBJECT_DECLARE_SIMPLE_TYPE(QIOChannelSocket, QIO_CHANNEL_SOCKET)
/**
#include "qom/object.h"
#define TYPE_QIO_CHANNEL_TLS "qio-channel-tls"
-typedef struct QIOChannelTLS QIOChannelTLS;
-DECLARE_INSTANCE_CHECKER(QIOChannelTLS, QIO_CHANNEL_TLS,
- TYPE_QIO_CHANNEL_TLS)
+OBJECT_DECLARE_SIMPLE_TYPE(QIOChannelTLS, QIO_CHANNEL_TLS)
/**
#include "qom/object.h"
#define TYPE_QIO_CHANNEL_WEBSOCK "qio-channel-websock"
-typedef struct QIOChannelWebsock QIOChannelWebsock;
-DECLARE_INSTANCE_CHECKER(QIOChannelWebsock, QIO_CHANNEL_WEBSOCK,
- TYPE_QIO_CHANNEL_WEBSOCK)
+OBJECT_DECLARE_SIMPLE_TYPE(QIOChannelWebsock, QIO_CHANNEL_WEBSOCK)
typedef union QIOChannelWebsockMask QIOChannelWebsockMask;
#define TYPE_QIO_CHANNEL "qio-channel"
OBJECT_DECLARE_TYPE(QIOChannel, QIOChannelClass,
- qio_channel, QIO_CHANNEL)
+ QIO_CHANNEL)
#define QIO_CHANNEL_ERR_BLOCK -2
#include "io/task.h"
#define TYPE_QIO_DNS_RESOLVER "qio-dns-resolver"
-OBJECT_DECLARE_SIMPLE_TYPE(QIODNSResolver, qio_dns_resolver,
- QIO_DNS_RESOLVER, ObjectClass)
+OBJECT_DECLARE_SIMPLE_TYPE(QIODNSResolver,
+ QIO_DNS_RESOLVER)
/**
#include "qom/object.h"
#define TYPE_QIO_NET_LISTENER "qio-net-listener"
-OBJECT_DECLARE_SIMPLE_TYPE(QIONetListener, qio_net_listener,
- QIO_NET_LISTENER, ObjectClass)
+OBJECT_DECLARE_SIMPLE_TYPE(QIONetListener,
+ QIO_NET_LISTENER)
typedef void (*QIONetListenerClientFunc)(QIONetListener *listener,
};
#define TYPE_CAN_BUS "can-bus"
-DECLARE_INSTANCE_CHECKER(CanBusState, CAN_BUS,
- TYPE_CAN_BUS)
+OBJECT_DECLARE_SIMPLE_TYPE(CanBusState, CAN_BUS)
int can_bus_filter_match(struct qemu_can_filter *filter, qemu_canid_t can_id);
#include "qom/object.h"
#define TYPE_CAN_HOST "can-host"
-typedef struct CanHostClass CanHostClass;
-typedef struct CanHostState CanHostState;
-DECLARE_OBJ_CHECKERS(CanHostState, CanHostClass,
- CAN_HOST, TYPE_CAN_HOST)
+OBJECT_DECLARE_TYPE(CanHostState, CanHostClass, CAN_HOST)
struct CanHostState {
ObjectClass oc;
#include "net/queue.h"
#define TYPE_NETFILTER "netfilter"
-typedef struct NetFilterClass NetFilterClass;
-DECLARE_OBJ_CHECKERS(NetFilterState, NetFilterClass,
- NETFILTER, TYPE_NETFILTER)
+OBJECT_DECLARE_TYPE(NetFilterState, NetFilterClass, NETFILTER)
typedef void (FilterSetup) (NetFilterState *nf, Error **errp);
typedef void (FilterCleanup) (NetFilterState *nf);
* OBJECT_DECLARE_TYPE:
* @InstanceType: instance struct name
* @ClassType: class struct name
- * @module_obj_name: the object name in lowercase with underscore separators
* @MODULE_OBJ_NAME: the object name in uppercase with underscore separators
*
* This macro is typically used in a header file, and will:
*
* The object struct and class struct need to be declared manually.
*/
-#define OBJECT_DECLARE_TYPE(InstanceType, ClassType, module_obj_name, MODULE_OBJ_NAME) \
+#define OBJECT_DECLARE_TYPE(InstanceType, ClassType, MODULE_OBJ_NAME) \
typedef struct InstanceType InstanceType; \
typedef struct ClassType ClassType; \
\
/**
* OBJECT_DECLARE_SIMPLE_TYPE:
* @InstanceType: instance struct name
- * @module_obj_name: the object name in lowercase with underscore separators
* @MODULE_OBJ_NAME: the object name in uppercase with underscore separators
- * @ParentClassType: class struct name of parent type
*
- * This does the same as OBJECT_DECLARE_TYPE(), but also declares
- * the class struct, thus only the object struct needs to be declare
- * manually.
+ * This does the same as OBJECT_DECLARE_TYPE(), but with no class struct
+ * declared.
*
* This macro should be used unless the class struct needs to have
* virtual methods declared.
*/
-#define OBJECT_DECLARE_SIMPLE_TYPE(InstanceType, module_obj_name, \
- MODULE_OBJ_NAME, ParentClassType) \
- OBJECT_DECLARE_TYPE(InstanceType, InstanceType##Class, module_obj_name, MODULE_OBJ_NAME) \
- struct InstanceType##Class { ParentClassType parent_class; };
+#define OBJECT_DECLARE_SIMPLE_TYPE(InstanceType, MODULE_OBJ_NAME) \
+ typedef struct InstanceType InstanceType; \
+ \
+ G_DEFINE_AUTOPTR_CLEANUP_FUNC(InstanceType, object_unref) \
+ \
+ DECLARE_INSTANCE_CHECKER(InstanceType, MODULE_OBJ_NAME, TYPE_##MODULE_OBJ_NAME)
/**
.parent = TYPE_##PARENT_MODULE_OBJ_NAME, \
.name = TYPE_##MODULE_OBJ_NAME, \
.instance_size = sizeof(ModuleObjName), \
+ .instance_align = __alignof__(ModuleObjName), \
.instance_init = module_obj_name##_init, \
.instance_finalize = module_obj_name##_finalize, \
.class_size = sizeof(ModuleObjName##Class), \
* @instance_size: The size of the object (derivative of #Object). If
* @instance_size is 0, then the size of the object will be the size of the
* parent object.
+ * @instance_align: The required alignment of the object. If @instance_align
+ * is 0, then normal malloc alignment is sufficient; if non-zero, then we
+ * must use qemu_memalign for allocation.
* @instance_init: This function is called to initialize an object. The parent
* class will have already been initialized so the type is only responsible
* for initializing its own members.
const char *parent;
size_t instance_size;
+ size_t instance_align;
void (*instance_init)(Object *obj);
void (*instance_post_init)(Object *obj);
void (*instance_finalize)(Object *obj);
* of this function. The only difference in behavior is that this function
* asserts instead of returning #NULL on failure if QOM cast debugging is
* enabled. This function is not meant to be called directly, but only through
- * the wrapper macros OBJECT_CLASS_CHECK and INTERFACE_CHECK.
+ * the wrapper macro OBJECT_CLASS_CHECK.
*/
ObjectClass *object_class_dynamic_cast_assert(ObjectClass *klass,
const char *typename,
* @name: the name of the property
* @errp: returns an error if this function fails
*
- * Returns: the value of the property, converted to a boolean, or NULL if
+ * Returns: the value of the property, converted to a boolean, or false if
* an error occurs (including when the property value is not a bool).
*/
bool object_property_get_bool(Object *obj, const char *name,
* @name: the name of the property
* @errp: returns an error if this function fails
*
- * Returns: the value of the property, converted to an integer, or negative if
+ * Returns: the value of the property, converted to an integer, or -1 if
* an error occurs (including when the property value is not an integer).
*/
int64_t object_property_get_int(Object *obj, const char *name,
* @typename: the name of the enum data type
* @errp: returns an error if this function fails
*
- * Returns: the value of the property, converted to an integer, or
- * undefined if an error occurs (including when the property value is not
- * an enum).
+ * Returns: the value of the property, converted to an integer (which
+ * can't be negative), or -1 on error (including when the property
+ * value is not an enum).
*/
int object_property_get_enum(Object *obj, const char *name,
const char *typename, Error **errp);
#define TYPE_PR_MANAGER "pr-manager"
OBJECT_DECLARE_TYPE(PRManager, PRManagerClass,
- pr_manager, PR_MANAGER)
+ PR_MANAGER)
struct sg_io_hdr;
#define TYPE_CRYPTODEV_BACKEND "cryptodev-backend"
OBJECT_DECLARE_TYPE(CryptoDevBackend, CryptoDevBackendClass,
- cryptodev_backend, CRYPTODEV_BACKEND)
+ CRYPTODEV_BACKEND)
#define MAX_CRYPTO_QUEUE_NUM 64
#define TYPE_MEMORY_BACKEND "memory-backend"
OBJECT_DECLARE_TYPE(HostMemoryBackend, HostMemoryBackendClass,
- memory_backend, MEMORY_BACKEND)
+ MEMORY_BACKEND)
/* hostmem-ram.c */
/**
#include "qom/object.h"
#define TYPE_RNG_RANDOM "rng-random"
-typedef struct RngRandom RngRandom;
-DECLARE_INSTANCE_CHECKER(RngRandom, RNG_RANDOM,
- TYPE_RNG_RANDOM)
+OBJECT_DECLARE_SIMPLE_TYPE(RngRandom, RNG_RANDOM)
#endif
#define TYPE_RNG_BACKEND "rng-backend"
OBJECT_DECLARE_TYPE(RngBackend, RngBackendClass,
- rng_backend, RNG_BACKEND)
+ RNG_BACKEND)
#define TYPE_RNG_BUILTIN "rng-builtin"
#define TYPE_TPM_BACKEND "tpm-backend"
OBJECT_DECLARE_TYPE(TPMBackend, TPMBackendClass,
- tpm_backend, TPM_BACKEND)
+ TPM_BACKEND)
typedef struct TPMBackendCmd {
#include "io/channel.h"
#define TYPE_VHOST_USER_BACKEND "vhost-user-backend"
-OBJECT_DECLARE_SIMPLE_TYPE(VhostUserBackend, vhost_user_backend,
- VHOST_USER_BACKEND, ObjectClass)
+OBJECT_DECLARE_SIMPLE_TYPE(VhostUserBackend,
+ VHOST_USER_BACKEND)
/* consoles */
#define TYPE_QEMU_CONSOLE "qemu-console"
-typedef struct QemuConsoleClass QemuConsoleClass;
-DECLARE_OBJ_CHECKERS(QemuConsole, QemuConsoleClass,
- QEMU_CONSOLE, TYPE_QEMU_CONSOLE)
+OBJECT_DECLARE_TYPE(QemuConsole, QemuConsoleClass, QEMU_CONSOLE)
struct QemuConsoleClass {
.parent = TYPE_OBJECT,
.name = TYPE_QIO_DNS_RESOLVER,
.instance_size = sizeof(QIODNSResolver),
- .class_size = sizeof(QIODNSResolverClass),
};
.name = TYPE_QIO_NET_LISTENER,
.instance_size = sizeof(QIONetListener),
.instance_finalize = qio_net_listener_finalize,
- .class_size = sizeof(QIONetListenerClass),
};
/* would certainly save at least one if it were made ten times */
/* bigger, too (for truncated fractions 0.100 through 0.999). */
/* However, for most practical evaluations, at least four or five */
-/* iterations will be neede -- so this would only speed up by */
+/* iterations will be needed -- so this would only speed up by */
/* 20-25% and that probably does not justify increasing the table */
/* size. */
/* */
struct target_aarch64_ctx head;
uint16_t vl;
uint16_t reserved[3];
- /* The actual SVE data immediately follows. It is layed out
+ /* The actual SVE data immediately follows. It is laid out
* according to TARGET_SVE_SIG_{Z,P}REG_OFFSET, based off of
* the original struct pointer.
*/
#define UNAME_MACHINE "cris"
#define UNAME_MINIMUM_RELEASE "2.6.32"
-/* pt_regs not only specifices the format in the user-struct during
+/* pt_regs not only specifies the format in the user-struct during
* ptrace but is also the frame format used in the kernel prologue/epilogues
* themselves
*/
unsigned long spc;
unsigned long ccs;
unsigned long srp;
- unsigned long erp; /* This is actually the debugged process' PC */
+ unsigned long erp; /* This is actually the debugged process's PC */
/* For debugging purposes; saved only when needed. */
unsigned long exs;
unsigned long eda;
abi_ulong reloc_count; /* Number of relocation records */
abi_ulong flags;
abi_ulong build_date; /* When the program/library was built */
- abi_ulong filler[5]; /* Reservered, set to zero */
+ abi_ulong filler[5]; /* Reserved, set to zero */
};
#define FLAT_FLAG_RAM 0x0001 /* load program entirely into RAM */
indx_len = (indx_len + 15) & ~(abi_ulong)15;
/*
- * Alloate the address space.
+ * Allocate the address space.
*/
probe_guest_base(bprm->filename, 0,
text_len + data_len + extra + indx_len);
#error here
for (i = MAX_SHARED_LIBS-1; i>0; i--) {
if (libinfo[i].loaded) {
- /* Push previos first to call address */
+ /* Push previous first to call address */
--sp;
if (put_user_ual(start_addr, sp))
return -EFAULT;
/* code path when we didn't execute the syscall */
0: addi 3, 0, -TARGET_ERESTARTSYS
- ld 14, 16(1) /* restore r14 to its orginal value */
+ ld 14, 16(1) /* restore r14 to its original value */
blr
.cfi_endproc
#if defined(TARGET_NR_timer_create)
-/* Maxiumum of 32 active POSIX timers allowed at any one time. */
+/* Maximum of 32 active POSIX timers allowed at any one time. */
static timer_t g_posix_timers[32] = { 0, } ;
static inline int next_free_host_timer(void)
switch(num) {
case TARGET_NR_exit:
/* In old applications this may be used to implement _exit(2).
- However in threaded applictions it is used for thread termination,
+ However in threaded applications it is used for thread termination,
and _exit_group is used for application termination.
Do thread termination if we have more then one thread. */
{
if (failover_set_state(FAILOVER_STATUS_NONE,
FAILOVER_STATUS_REQUIRE) != FAILOVER_STATUS_NONE) {
- error_setg(errp, "COLO failover is already actived");
+ error_setg(errp, "COLO failover is already activated");
return;
}
failover_bh = qemu_bh_new(colo_failover_bh, NULL);
/*
* It is safe to unregister notifier after failover finished.
* Besides, colo_delay_timer and colo_checkpoint_sem can't be
- * released befor unregister notifier, or there will be use-after-free
+ * released before unregister notifier, or there will be use-after-free
* error.
*/
colo_compare_unregister_notifier(&packets_compare_notifier);
qemu_sem_post(&p->sem_sync);
/*
* Although multifd_send_thread is not created, but main migration
- * thread neet to judge whether it is running, so we need to mark
+ * thread needs to judge whether it is running, so we need to mark
* its status.
*/
p->quit = true;
/*
* Try to receive all multifd channels to get ready for the migration.
- * - Return true and do not set @errp when correctly receving all channels;
+ * - Return true and do not set @errp when correctly receiving all channels;
* - Return false and do not set @errp when correctly receiving the current one;
* - Return false and set @errp when failing to receive the current channel.
*/
* request_ufd_features: this function should be called only once on a newly
* opened ufd, subsequent calls will lead to error.
*
- * Returns: true on succes
+ * Returns: true on success
*
* @ufd: fd obtained from userfaultfd syscall
* @features: bit mask see UFFD_API_FEATURES
low_time_offset = get_low_time_offset(dc);
/* lookup cpu, to clear it,
- * that algorithm looks straighforward, but it's not
+ * that algorithm looks straightforward, but it's not
* optimal, more optimal algorithm is keeping tree or hash
* where key is address value is a list of */
for (i = 0; i < smp_cpus; i++) {
*/
void postcopy_register_shared_ufd(struct PostCopyFD *pcfd);
void postcopy_unregister_shared_ufd(struct PostCopyFD *pcfd);
-/* Call each of the shared 'waker's registerd telling them of
+/* Call each of the shared 'waker's registered telling them of
* availability of a block.
*/
int postcopy_notify_shared_wake(RAMBlock *rb, uint64_t offset);
/*
* Always use little endian when sending the bitmap. This is
* required that when source and destination VMs are not using the
- * same endianess. (Note: big endian won't work.)
+ * same endianness. (Note: big endian won't work.)
*/
bitmap_to_le(le_bitmap, block->receivedmap, nbits);
qemu_put_buffer(file, (const uint8_t *)le_bitmap, size);
/*
* Mark as an end, in case the middle part is screwed up due to
- * some "misterious" reason.
+ * some "mysterious" reason.
*/
qemu_put_be64(file, RAMBLOCK_RECV_BITMAP_ENDING);
qemu_fflush(file);
/*
* Reaching here means the page has hit the xbzrle cache, no matter what
* encoding result it is (normal encoding, overflow or skipping the page),
- * count the page as encoded. This is used to caculate the encoding rate.
+ * count the page as encoded. This is used to calculate the encoding rate.
*
* Example: 2 pages (8KB) being encoded, first page encoding generates 2KB,
* 2nd page turns out to be skipped (i.e. no new bytes written to the
/*
* Note: see comments in ramblock_recv_bitmap_send() on why we
- * need the endianess convertion, and the paddings.
+ * need the endianness conversion, and the paddings.
*/
local_size = ROUND_UP(local_size, 8);
}
/*
- * Endianess convertion. We are during postcopy (though paused).
+ * Endianness conversion. We are during postcopy (though paused).
* The dirty bitmap won't change. We can directly modify it.
*/
bitmap_from_le(block->bmap, le_bitmap, nbits);
} RDMAContext;
#define TYPE_QIO_CHANNEL_RDMA "qio-channel-rdma"
-typedef struct QIOChannelRDMA QIOChannelRDMA;
-DECLARE_INSTANCE_CHECKER(QIOChannelRDMA, QIO_CHANNEL_RDMA,
- TYPE_QIO_CHANNEL_RDMA)
+OBJECT_DECLARE_SIMPLE_TYPE(QIOChannelRDMA, QIO_CHANNEL_RDMA)
} else {
/* This is the source side, we're in a separate thread
* or destination prior to migration_fd_process_incoming()
- * after postcopy, the destination also in a seprate thread.
+ * after postcopy, the destination also in a separate thread.
* we can't yield; so we have to poll the fd.
* But we need to be able to handle 'cancel' or an error
* without hanging forever.
* chunk, then start a new chunk and flush() the old chunk.
* 3. To keep the hardware busy, we also group chunks into batches
* and only require that a batch gets acknowledged in the completion
- * qeueue instead of each individual chunk.
+ * queue instead of each individual chunk.
*/
static int qemu_rdma_write(QEMUFile *f, RDMAContext *rdma,
uint64_t block_offset, uint64_t offset,
if (size > 0) {
/*
* Add this page to the current 'chunk'. If the chunk
- * is full, or the page doen't belong to the current chunk,
+ * is full, or the page doesn't belong to the current chunk,
* an actual RDMA write will occur and a new chunk will be formed.
*/
ret = qemu_rdma_write(f, rdma, block_offset, offset, size);
goto err;
}
- /* RDMA postcopy need a seprate queue pair for return path */
+ /* RDMA postcopy need a separate queue pair for return path */
if (migrate_postcopy()) {
rdma_return_path = qemu_rdma_data_init(host_port, errp);
if (!has_live) {
/* live default to true so old version of Xen tool stack can have a
- * successfull live migration */
+ * successful live migration */
live = true;
}
* "xen-save-devices-state" and in case of migration failure, libxl
* would call "cont".
* So call bdrv_inactivate_all (release locks) here to let the other
- * side of the migration take controle of the images.
+ * side of the migration take control of the images.
*/
if (live && !saved_vm_running) {
ret = bdrv_inactivate_all();
#endif /*DEBUG_CAN*/
#define TYPE_CAN_HOST_SOCKETCAN "can-host-socketcan"
-typedef struct CanHostSocketCAN CanHostSocketCAN;
-DECLARE_INSTANCE_CHECKER(CanHostSocketCAN, CAN_HOST_SOCKETCAN,
- TYPE_CAN_HOST_SOCKETCAN)
+OBJECT_DECLARE_SIMPLE_TYPE(CanHostSocketCAN, CAN_HOST_SOCKETCAN)
#define CAN_READ_BUF_LEN 5
struct CanHostSocketCAN {
#define TYPE_FILTER_DUMP "filter-dump"
-typedef struct NetFilterDumpState NetFilterDumpState;
-DECLARE_INSTANCE_CHECKER(NetFilterDumpState, FILTER_DUMP,
- TYPE_FILTER_DUMP)
+OBJECT_DECLARE_SIMPLE_TYPE(NetFilterDumpState, FILTER_DUMP)
struct NetFilterDumpState {
NetFilterState nfs;
#define TYPE_FILTER_BUFFER "filter-buffer"
-typedef struct FilterBufferState FilterBufferState;
-DECLARE_INSTANCE_CHECKER(FilterBufferState, FILTER_BUFFER,
- TYPE_FILTER_BUFFER)
+OBJECT_DECLARE_SIMPLE_TYPE(FilterBufferState, FILTER_BUFFER)
struct FilterBufferState {
NetFilterState parent_obj;
#define TYPE_FILTER_REPLAY "filter-replay"
-typedef struct NetFilterReplayState NetFilterReplayState;
-DECLARE_INSTANCE_CHECKER(NetFilterReplayState, FILTER_REPLAY,
- TYPE_FILTER_REPLAY)
+OBJECT_DECLARE_SIMPLE_TYPE(NetFilterReplayState, FILTER_REPLAY)
struct NetFilterReplayState {
NetFilterState nfs;
#include "util.h"
#define TYPE_FILTER_REWRITER "filter-rewriter"
-typedef struct RewriterState RewriterState;
-DECLARE_INSTANCE_CHECKER(RewriterState, FILTER_REWRITER,
- TYPE_FILTER_REWRITER)
+OBJECT_DECLARE_SIMPLE_TYPE(RewriterState, FILTER_REWRITER)
#define FAILOVER_MODE_ON true
#define FAILOVER_MODE_OFF false
#
# @block-backend: corresponds to BlockBackend
#
-# @block-job: corresonds to BlockJob
+# @block-job: corresponds to BlockJob
#
# @block-driver: corresponds to BlockDriverState
#
# @target: name of the destination dirty bitmap
#
# @bitmaps: name(s) of the source dirty bitmap(s) at @node and/or fully
-# specifed BlockDirtyBitmap elements. The latter are supported
+# specified BlockDirtyBitmap elements. The latter are supported
# since 4.1.
#
# Since: 4.0
# written into added active keyslots
#
# @old-secret: Optional (for deactivation only)
-# If given will deactive all keyslots that
+# If given will deactivate all keyslots that
# match password located in QCryptoSecret with this ID
#
# @iter-time: Optional (for activation only)
# keyslot to deactivate
#
# @secret: Optional. The ID of a QCryptoSecret object providing the
-# password to use to retrive current master key.
+# password to use to retrieve current master key.
# Defaults to the same secret that was used to open the image
#
#
* 'pnum' is set to the number of sectors (including and immediately following
* the first one) that are known to be in the same allocated/unallocated state.
* The function will try to align the end offset to alignment boundaries so
- * that the request will at least end aligned and consequtive requests will
+ * that the request will at least end aligned and consecutive requests will
* also start at an aligned offset.
*/
static int is_allocated_sectors(const uint8_t *buf, int n, int *pnum,
.. parsed-literal::
- |qemu_system| \
- -add-fd fd=3,set=2,opaque="rdwr:/path/to/file" \
- -add-fd fd=4,set=2,opaque="rdonly:/path/to/file" \
+ |qemu_system| \\
+ -add-fd fd=3,set=2,opaque="rdwr:/path/to/file" \\
+ -add-fd fd=4,set=2,opaque="rdonly:/path/to/file" \\
-drive file=/dev/fdset/2,index=0,media=disk
ERST
.. parsed-literal::
- |qemu_system| \
- -add-fd fd=3,set=2,opaque="rdwr:/path/to/file" \
- -add-fd fd=4,set=2,opaque="rdonly:/path/to/file" \
+ |qemu_system| \\
+ -add-fd fd=3,set=2,opaque="rdwr:/path/to/file" \\
+ -add-fd fd=4,set=2,opaque="rdonly:/path/to/file" \\
-drive file=/dev/fdset/2,index=0,media=disk
You can connect a CDROM to the slave of ide0:
.. parsed-literal::
- |qemu_system| -hda linux.img -boot n -device e1000,netdev=n1 \
+ |qemu_system| -hda linux.img -boot n -device e1000,netdev=n1 \\
-netdev user,id=n1,tftp=/path/to/tftp/files,bootfile=/pxelinux.0
``smb=dir[,smbserver=addr]``
#launch a QEMU instance with two NICs, each one connected
#to a TAP device
- |qemu_system| linux.img \
- -netdev tap,id=nd0,ifname=tap0 -device e1000,netdev=nd0 \
+ |qemu_system| linux.img \\
+ -netdev tap,id=nd0,ifname=tap0 -device e1000,netdev=nd0 \\
-netdev tap,id=nd1,ifname=tap1 -device rtl8139,netdev=nd1
.. parsed-literal::
#launch a QEMU instance with the default network helper to
#connect a TAP device to bridge br0
- |qemu_system| linux.img -device virtio-net-pci,netdev=n1 \
+ |qemu_system| linux.img -device virtio-net-pci,netdev=n1 \\
-netdev tap,id=n1,"helper=/path/to/qemu-bridge-helper"
``-netdev bridge,id=id[,br=bridge][,helper=helper]``
.. parsed-literal::
# launch a first QEMU instance
- |qemu_system| linux.img \
- -device e1000,netdev=n1,mac=52:54:00:12:34:56 \
+ |qemu_system| linux.img \\
+ -device e1000,netdev=n1,mac=52:54:00:12:34:56 \\
-netdev socket,id=n1,listen=:1234
# connect the network of this instance to the network of the first instance
- |qemu_system| linux.img \
- -device e1000,netdev=n2,mac=52:54:00:12:34:57 \
+ |qemu_system| linux.img \\
+ -device e1000,netdev=n2,mac=52:54:00:12:34:57 \\
-netdev socket,id=n2,connect=127.0.0.1:1234
``-netdev socket,id=id[,fd=h][,mcast=maddr:port[,localaddr=addr]]``
.. parsed-literal::
# launch one QEMU instance
- |qemu_system| linux.img \
- -device e1000,netdev=n1,mac=52:54:00:12:34:56 \
+ |qemu_system| linux.img \\
+ -device e1000,netdev=n1,mac=52:54:00:12:34:56 \\
-netdev socket,id=n1,mcast=230.0.0.1:1234
# launch another QEMU instance on same "bus"
- |qemu_system| linux.img \
- -device e1000,netdev=n2,mac=52:54:00:12:34:57 \
+ |qemu_system| linux.img \\
+ -device e1000,netdev=n2,mac=52:54:00:12:34:57 \\
-netdev socket,id=n2,mcast=230.0.0.1:1234
# launch yet another QEMU instance on same "bus"
- |qemu_system| linux.img \
- -device e1000,netdev=n3,mac=52:54:00:12:34:58 \
+ |qemu_system| linux.img \\
+ -device e1000,netdev=n3,mac=52:54:00:12:34:58 \\
-netdev socket,id=n3,mcast=230.0.0.1:1234
Example (User Mode Linux compat.):
.. parsed-literal::
# launch QEMU instance (note mcast address selected is UML's default)
- |qemu_system| linux.img \
- -device e1000,netdev=n1,mac=52:54:00:12:34:56 \
+ |qemu_system| linux.img \\
+ -device e1000,netdev=n1,mac=52:54:00:12:34:56 \\
-netdev socket,id=n1,mcast=239.192.168.1:1102
# launch UML
/path/to/linux ubd0=/path/to/root_fs eth0=mcast
.. parsed-literal::
- |qemu_system| linux.img \
- -device e1000,netdev=n1,mac=52:54:00:12:34:56 \
+ |qemu_system| linux.img \\
+ -device e1000,netdev=n1,mac=52:54:00:12:34:56 \\
-netdev socket,id=n1,mcast=239.192.168.1:1102,localaddr=1.2.3.4
``-netdev l2tpv3,id=id,src=srcaddr,dst=dstaddr[,srcport=srcport][,dstport=dstport],txsession=txsession[,rxsession=rxsession][,ipv6][,udp][,cookie64][,counter][,pincounter][,txcookie=txcookie][,rxcookie=rxcookie][,offset=offset]``
# Setup tunnel on linux host using raw ip as encapsulation
# on 1.2.3.4
- ip l2tp add tunnel remote 4.3.2.1 local 1.2.3.4 tunnel_id 1 peer_tunnel_id 1 \
+ ip l2tp add tunnel remote 4.3.2.1 local 1.2.3.4 tunnel_id 1 peer_tunnel_id 1 \\
encap udp udp_sport 16384 udp_dport 16384
- ip l2tp add session tunnel_id 1 name vmtunnel0 session_id \
+ ip l2tp add session tunnel_id 1 name vmtunnel0 session_id \\
0xFFFFFFFF peer_session_id 0xFFFFFFFF
ifconfig vmtunnel0 mtu 1500
ifconfig vmtunnel0 up
# on 4.3.2.1
# launch QEMU instance - if your network has reorder or is very lossy add ,pincounter
- |qemu_system| linux.img -device e1000,netdev=n1 \
+ |qemu_system| linux.img -device e1000,netdev=n1 \\
-netdev l2tpv3,id=n1,src=4.2.3.1,dst=1.2.3.4,udp,srcport=16384,dstport=16384,rxsession=0xffffffff,txsession=0xffffffff,counter
``-netdev vde,id=id[,sock=socketpath][,port=n][,group=groupname][,mode=octalmode]``
.. parsed-literal::
- # |qemu_system| \
- -object tls-cipher-suites,id=mysuite0,priority=@SYSTEM \
+ # |qemu_system| \\
+ -object tls-cipher-suites,id=mysuite0,priority=@SYSTEM \\
-fw_cfg name=etc/edk2/https/ciphers,gen_id=mysuite0
``-object filter-buffer,id=id,netdev=netdevid,interval=t[,queue=all|rx|tx][,status=on|off][,position=head|tail|id=<id>][,insert=behind|before]``
.. parsed-literal::
- # |qemu_system| \
- [...] \
- -object cryptodev-backend-builtin,id=cryptodev0 \
- -device virtio-crypto-pci,id=crypto0,cryptodev=cryptodev0 \
+ # |qemu_system| \\
+ [...] \\
+ -object cryptodev-backend-builtin,id=cryptodev0 \\
+ -device virtio-crypto-pci,id=crypto0,cryptodev=cryptodev0 \\
[...]
``-object cryptodev-vhost-user,id=id,chardev=chardevid[,queues=queues]``
.. parsed-literal::
- # |qemu_system| \
- [...] \
- -chardev socket,id=chardev0,path=/path/to/socket \
- -object cryptodev-vhost-user,id=cryptodev0,chardev=chardev0 \
- -device virtio-crypto-pci,id=crypto0,cryptodev=cryptodev0 \
+ # |qemu_system| \\
+ [...] \\
+ -chardev socket,id=chardev0,path=/path/to/socket \\
+ -object cryptodev-vhost-user,id=cryptodev0,chardev=chardev0 \\
+ -device virtio-crypto-pci,id=crypto0,cryptodev=cryptodev0 \\
[...]
``-object secret,id=id,data=string,format=raw|base64[,keyid=secretid,iv=string]``
.. parsed-literal::
- # |qemu_system| \
- -object secret,id=secmaster0,format=base64,file=key.b64 \
- -object secret,id=sec0,keyid=secmaster0,format=base64,\
+ # |qemu_system| \\
+ -object secret,id=secmaster0,format=base64,file=key.b64 \\
+ -object secret,id=sec0,keyid=secmaster0,format=base64,\\
data=$SECRET,iv=$(<iv.b64)
``-object sev-guest,id=id,cbitpos=cbitpos,reduced-phys-bits=val,[sev-device=string,policy=policy,handle=handle,dh-cert-file=file,session-file=file]``
.. parsed-literal::
- # |qemu_system_x86| \
- ......
- -object sev-guest,id=sev0,cbitpos=47,reduced-phys-bits=5 \
- -machine ...,memory-encryption=sev0
+ # |qemu_system_x86| \\
+ ...... \\
+ -object sev-guest,id=sev0,cbitpos=47,reduced-phys-bits=5 \\
+ -machine ...,memory-encryption=sev0 \\
.....
``-object authz-simple,id=id,identity=string``
.. parsed-literal::
- # |qemu_system| \
- ...
- -object 'authz-simple,id=auth0,identity=CN=laptop.example.com,,O=Example Org,,L=London,,ST=London,,C=GB' \
+ # |qemu_system| \\
+ ... \\
+ -object 'authz-simple,id=auth0,identity=CN=laptop.example.com,,O=Example Org,,L=London,,ST=London,,C=GB' \\
...
Note the use of quotes due to the x509 distinguished name
.. parsed-literal::
- # |qemu_system| \
- ...
- -object authz-simple,id=auth0,filename=/etc/qemu/vnc-sasl.acl,refresh=yes
+ # |qemu_system| \\
+ ... \\
+ -object authz-simple,id=auth0,filename=/etc/qemu/vnc-sasl.acl,refresh=yes \\
...
``-object authz-pam,id=id,service=string``
.. parsed-literal::
- # |qemu_system| \
- ...
- -object authz-pam,id=auth0,service=qemu-vnc
+ # |qemu_system| \\
+ ... \\
+ -object authz-pam,id=auth0,service=qemu-vnc \\
...
There would then be a corresponding config file for PAM at
}
/**
- * tdb_hash(): based on the hash agorithm from gdbm, via tdb
+ * tdb_hash(): based on the hash algorithm from gdbm, via tdb
* (from module-init-tools)
*/
static unsigned int tdb_hash(const char *name)
size_t class_size;
size_t instance_size;
+ size_t instance_align;
void (*class_init)(ObjectClass *klass, void *data);
void (*class_base_init)(ObjectClass *klass, void *data);
ti->class_size = info->class_size;
ti->instance_size = info->instance_size;
+ ti->instance_align = info->instance_align;
ti->class_init = info->class_init;
ti->class_base_init = info->class_base_init;
}
}
+/* Find the minimum alignment guaranteed by the system malloc. */
+#if __STDC_VERSION__ >= 201112L
+typddef max_align_t qemu_max_align_t;
+#else
+typedef union {
+ long l;
+ void *p;
+ double d;
+ long double ld;
+} qemu_max_align_t;
+#endif
+
static Object *object_new_with_type(Type type)
{
Object *obj;
+ size_t size, align;
+ void (*obj_free)(void *);
g_assert(type != NULL);
type_initialize(type);
- obj = g_malloc(type->instance_size);
- object_initialize_with_type(obj, type->instance_size, type);
- obj->free = g_free;
+ size = type->instance_size;
+ align = type->instance_align;
+
+ /*
+ * Do not use qemu_memalign unless required. Depending on the
+ * implementation, extra alignment implies extra overhead.
+ */
+ if (likely(align <= __alignof__(qemu_max_align_t))) {
+ obj = g_malloc(size);
+ obj_free = g_free;
+ } else {
+ obj = qemu_memalign(align, size);
+ obj_free = qemu_vfree;
+ }
+
+ object_initialize_with_type(obj, size, type);
+ obj->free = obj_free;
return obj;
}
EnumProperty *enumprop;
if (prop == NULL) {
- return 0;
+ return -1;
}
if (!g_str_equal(prop->type, typename)) {
error_setg(errp, "Property %s on %s is not '%s' enum type",
name, object_class_get_name(
object_get_class(obj)), typename);
- return 0;
+ return -1;
}
enumprop = prop->opaque;
str = object_property_get_str(obj, name, errp);
if (!str) {
- return 0;
+ return -1;
}
ret = qapi_enum_parse(enumprop->lookup, str, -1, errp);
# Seek back to where we were at the beginning
self.file.seek(entrypos, 0)
- return data[jsonpos:jsonpos + jsonlen]
+ # explicit decode() needed for Python 3.5 compatibility
+ return data[jsonpos:jsonpos + jsonlen].decode("utf-8")
def close(self):
self.file.close()
substr($s, 0, length($c), '');
# Make sure we remove the line prefixes as we have
- # none on the first line, and are going to readd them
+ # none on the first line, and are going to re-add them
# where necessary.
$s =~ s/\n./\n/gs;
# Does the following:
# - Header files without a recognizable header guard are skipped.
# - Clean up any untidy header guards in-place. Warn if the cleanup
-# renames guard symbols, and explain how to find occurences of these
+# renames guard symbols, and explain how to find occurrences of these
# symbols that may have to be updated manually.
# - Warn about duplicate header guard symbols. To make full use of
# this warning, you should clean up *all* headers in one run.
#
# This work is licensed under the terms of the GNU GPL, version 2. See
# the COPYING file in the top-level directory.
-from typing import IO, Match, NamedTuple, Optional, Literal, Iterable, Type, Dict, List, Any, TypeVar, NewType, Tuple
+from typing import IO, Match, NamedTuple, Optional, Literal, Iterable, Type, Dict, List, Any, TypeVar, NewType, Tuple, Union
from pathlib import Path
from itertools import chain
from tempfile import NamedTemporaryFile
def __init__(self, f: 'FileInfo', m: Match) -> None:
self.file: 'FileInfo' = f
- self.match: Match = m
+ self.match: Match[str] = m
@property
def name(self) -> str:
def line_col(self) -> LineAndColumn:
return self.file.line_col(self.start())
- def group(self, *args):
- return self.match.group(*args)
+ def group(self, group: Union[int, str]) -> str:
+ return self.match.group(group)
+
+ def getgroup(self, group: str) -> Optional[str]:
+ if group not in self.match.groupdict():
+ return None
+ return self.match.group(group)
def log(self, level, fmt, *args) -> None:
pos = self.line_col()
raise NotImplementedError()
@classmethod
- def find_matches(klass, content: str) -> Iterable[Match]:
- """Generate match objects for class
+ def finditer(klass, content: str, pos=0, endpos=-1) -> Iterable[Match]:
+ """Helper for re.finditer()"""
+ if endpos >= 0:
+ content = content[:endpos]
+ return klass.compiled_re().finditer(content, pos)
- Might be reimplemented by subclasses if they
- intend to look for matches using a different method.
- """
- return klass.compiled_re().finditer(content)
+ @classmethod
+ def domatch(klass, content: str, pos=0, endpos=-1) -> Optional[Match]:
+ """Helper for re.match()"""
+ if endpos >= 0:
+ content = content[:endpos]
+ return klass.compiled_re().match(content, pos)
+
+ def group_finditer(self, klass: Type['FileMatch'], group: Union[str, int]) -> Iterable['FileMatch']:
+ assert self.file.original_content
+ return (klass(self.file, m)
+ for m in klass.finditer(self.file.original_content,
+ self.match.start(group),
+ self.match.end(group)))
+
+ def try_group_match(self, klass: Type['FileMatch'], group: Union[str, int]) -> Optional['FileMatch']:
+ assert self.file.original_content
+ m = klass.domatch(self.file.original_content,
+ self.match.start(group),
+ self.match.end(group))
+ if not m:
+ return None
+ else:
+ return klass(self.file, m)
+
+ def group_match(self, group: Union[str, int]) -> 'FileMatch':
+ m = self.try_group_match(FullMatch, group)
+ assert m
+ return m
@property
def allfiles(self) -> 'FileList':
return self.file.allfiles
+class FullMatch(FileMatch):
+ """Regexp that will match all contents of string
+ Useful when used with group_match()
+ """
+ regexp = r'(?s).*' # (?s) is re.DOTALL
+
def all_subclasses(c: Type[FileMatch]) -> Iterable[Type[FileMatch]]:
for sc in c.__subclasses__():
yield sc
"""
r = StringIO()
last = 0
- for p in sorted(patches):
+ def patch_sort_key(item: Tuple[int, Patch]) -> Tuple[int, int, int]:
+ """Patches are sorted by byte position,
+ patches at the same byte position are applied in the order
+ they were generated.
+ """
+ i,p = item
+ return (p.start, p.end, i)
+
+ for i,p in sorted(enumerate(patches), key=patch_sort_key):
DBG("Applying patch at position %d (%s) - %d (%s): %r",
p.start, line_col(s, p.start),
p.end, line_col(s, p.end),
self.match_index: Dict[Type[Any], List[FileMatch]] = {}
self.match_name_index: Dict[Tuple[Type[Any], str, str], Optional[FileMatch]] = {}
- def _find_matches(self, klass: Type[Any]) -> Iterable[FileMatch]:
+ def _matches_of_type(self, klass: Type[Any]) -> Iterable[FileMatch]:
raise NotImplementedError()
def matches_of_type(self, t: Type[T]) -> List[T]:
if t not in self.match_index:
- self.match_index[t] = list(self._find_matches(t))
- return self.match_index[t] # type: ignore
+ self.match_index[t] = list(self._matches_of_type(t))
+ return self.match_index[t] # type: ignore
- def find_match(self, t: Type[T], name: str, group: str='name') -> Optional[T]:
+ def find_matches(self, t: Type[T], name: str, group: str='name') -> List[T]:
indexkey = (t, name, group)
if indexkey in self.match_name_index:
return self.match_name_index[indexkey] # type: ignore
- r: Optional[T] = None
+ r: List[T] = []
for m in self.matches_of_type(t):
assert isinstance(m, FileMatch)
- if m.group(group) == name:
- r = m # type: ignore
+ if m.getgroup(group) == name:
+ r.append(m) # type: ignore
self.match_name_index[indexkey] = r # type: ignore
return r
+ def find_match(self, t: Type[T], name: str, group: str='name') -> Optional[T]:
+ l = self.find_matches(t, name, group)
+ if not l:
+ return None
+ if len(l) > 1:
+ logger.warn("multiple matches found for %r (%s=%r)", t, group, name)
+ return None
+ return l[0]
+
def reset_index(self) -> None:
self.match_index.clear()
self.match_name_index.clear()
def __repr__(self) -> str:
return f'<FileInfo {repr(self.filename)}>'
+ def filename_matches(self, name: str) -> bool:
+ nameparts = Path(name).parts
+ return self.filename.parts[-len(nameparts):] == nameparts
+
def line_col(self, start: int) -> LineAndColumn:
"""Return line and column for a match object inside original_content"""
return line_col(self.original_content, start)
- def _find_matches(self, klass: Type[Any]) -> List[FileMatch]:
+ def _matches_of_type(self, klass: Type[Any]) -> List[FileMatch]:
"""Build FileMatch objects for each match of regexp"""
if not hasattr(klass, 'regexp') or klass.regexp is None:
return []
assert hasattr(klass, 'regexp')
DBG("%s: scanning for %s", self.filename, klass.__name__)
DBG("regexp: %s", klass.regexp)
- matches = [klass(self, m) for m in klass.find_matches(self.original_content)]
+ matches = [klass(self, m) for m in klass.finditer(self.original_content)]
DBG('%s: %d matches found for %s: %s', self.filename, len(matches),
klass.__name__,' '.join(names(matches)))
return matches
def find_match(self, t: Type[T], name: str, group: str='name') -> Optional[T]:
for m in self.matches_of_type(t):
assert isinstance(m, FileMatch)
- if m.group(group) == name:
+ if m.getgroup(group) == name:
return m # type: ignore
return None
return (m for l in lists
for m in l)
- def scan_for_matches(self, class_names: Optional[List[str]]=None) -> None:
+ def gen_patches(self, matches: List[FileMatch]) -> None:
+ for m in matches:
+ DBG("Generating patches for %r", m)
+ for i,p in enumerate(m.gen_patches()):
+ DBG("patch %d generated by %r:", i, m)
+ DBG("replace contents at %s-%s with %r",
+ self.line_col(p.start), self.line_col(p.end), p.replacement)
+ self.patches.append(p)
+
+ def scan_for_matches(self, class_names: Optional[List[str]]=None) -> Iterable[FileMatch]:
DBG("class names: %r", class_names)
class_dict = match_class_dict()
if class_names is None:
DBG("class_names: %r", class_names)
for cn in class_names:
matches = self.matches_of_type(class_dict[cn])
- if len(matches) > 0:
- DBG('%s: %d matches found for %s: %s', self.filename,
- len(matches), cn, ' '.join(names(matches)))
-
- def gen_patches(self) -> None:
- for m in self.all_matches:
- for i,p in enumerate(m.gen_patches()):
- DBG("patch %d generated by %r:", i, m)
- DBG("replace contents at %s-%s with %r",
- self.line_col(p.start), self.line_col(p.end), p.replacement)
- self.patches.append(p)
-
- def patch_content(self, max_passes=0, class_names: Optional[List[str]]=None) -> None:
- """Multi-pass content patching loop
-
- We run multiple passes because there are rules that will
- delete init functions once they become empty.
- """
- passes = 0
- total_patches = 0
- DBG("max_passes: %r", max_passes)
- while not max_passes or max_passes <= 0 or passes < max_passes:
- passes += 1
- self.scan_for_matches(class_names)
- self.gen_patches()
- DBG("patch content: pass %d: %d patches generated", passes, len(self.patches))
- total_patches += len(self.patches)
- if not self.patches:
- break
- try:
- self.apply_patches()
- except PatchingError:
- logger.exception("%s: failed to patch file", self.filename)
- DBG("%s: %d patches applied total in %d passes", self.filename, total_patches, passes)
+ DBG('%d matches found for %s: %s',
+ len(matches), cn, ' '.join(names(matches)))
+ yield from matches
def apply_patches(self) -> None:
"""Replace self.original_content after applying patches from self.patches"""
def __iter__(self):
return iter(self.files)
- def _find_matches(self, klass: Type[Any]) -> Iterable[FileMatch]:
- return chain(*(f._find_matches(klass) for f in self.files))
+ def _matches_of_type(self, klass: Type[Any]) -> Iterable[FileMatch]:
+ return chain(*(f._matches_of_type(klass) for f in self.files))
- def find_file(self, name) -> Optional[FileInfo]:
+ def find_file(self, name: str) -> Optional[FileInfo]:
"""Get file with path ending with @name"""
- nameparts = Path(name).parts
for f in self.files:
- if f.filename.parts[:len(nameparts)] == nameparts:
+ if f.filename_matches(name):
return f
else:
- return None
\ No newline at end of file
+ return None
+
+ def one_pass(self, class_names: List[str]) -> int:
+ total_patches = 0
+ for f in self.files:
+ INFO("Scanning file %s", f.filename)
+ matches = list(f.scan_for_matches(class_names))
+ INFO("Generating patches for file %s", f.filename)
+ f.gen_patches(matches)
+ total_patches += len(f.patches)
+ if total_patches:
+ for f in self.files:
+ try:
+ f.apply_patches()
+ except PatchingError:
+ logger.exception("%s: failed to patch file", f.filename)
+ return total_patches
+
+ def patch_content(self, max_passes, class_names: List[str]) -> None:
+ """Multi-pass content patching loop
+
+ We run multiple passes because there are rules that will
+ delete init functions once they become empty.
+ """
+ passes = 0
+ total_patches = 0
+ DBG("max_passes: %r", max_passes)
+ while not max_passes or max_passes <= 0 or passes < max_passes:
+ passes += 1
+ INFO("Running pass: %d", passes)
+ count = self.one_pass(class_names)
+ DBG("patch content: pass %d: %d patches generated", passes, count)
+ total_patches += count
+ DBG("%d patches applied total in %d passes", total_patches, passes)
RE_CONSTANT = OR(RE_STRING, RE_NUMBER)
-class ConstantDefine(FileMatch):
- """Simple #define preprocessor directive for a constant"""
- # if the macro contents are very simple, it might be included
- # in the match group 'value'
+class DefineDirective(FileMatch):
+ """Match any #define directive"""
+ regexp = S(r'^[ \t]*#[ \t]*define', CPP_SPACE, NAMED('name', RE_IDENTIFIER), r'\b')
+
+class ExpressionDefine(FileMatch):
+ """Simple #define preprocessor directive for an expression"""
regexp = S(r'^[ \t]*#[ \t]*define', CPP_SPACE, NAMED('name', RE_IDENTIFIER),
- CPP_SPACE, NAMED('value', RE_CONSTANT), r'[ \t]*\n')
+ CPP_SPACE, NAMED('value', RE_EXPRESSION), r'[ \t]*\n')
def provided_identifiers(self) -> Iterable[RequiredIdentifier]:
yield RequiredIdentifier('constant', self.group('name'))
+class ConstantDefine(ExpressionDefine):
+ """Simple #define preprocessor directive for a number or string constant"""
+ regexp = S(r'^[ \t]*#[ \t]*define', CPP_SPACE, NAMED('name', RE_IDENTIFIER),
+ CPP_SPACE, NAMED('value', RE_CONSTANT), r'[ \t]*\n')
+
+
class TypeIdentifiers(NamedTuple):
"""Type names found in type declarations"""
# TYPE_MYDEVICE
"""OBJECT_CHECK/OBJECT_CLASS_CHECK/OBJECT_GET_CLASS macro definitions
Will be replaced by DECLARE_*_CHECKERS macro
"""
- #TODO: handle and convert INTERFACE_CHECK macros
regexp = RE_CHECK_MACRO
@property
def checker(self) -> CheckerMacroName:
"""Name of checker macro being used"""
- return self.group('checker')
+ return self.group('checker') # type: ignore
@property
def typedefname(self) -> Optional[str]:
instancetype=instancetype, uppercase=uppercase)
def gen_patches(self) -> Iterable[Patch]:
+ # the implementation is a bit tricky because we need to group
+ # macros dealing with the same type into a single declaration
if self.type_identifiers is None:
self.warn("couldn't extract type information from macro %s", self.name)
return
yield self.prepend("/* FIXME: %s */\n" % (issue))
yield self.append(new_decl)
-class DeclareInstanceChecker(FileMatch):
- """DECLARE_INSTANCE_CHECKER use
- Will be replaced with DECLARE_OBJ_CHECKERS if possible
+class InterfaceCheckMacro(FileMatch):
+ """Type checking macro using INTERFACE_CHECK
+ Will be replaced by DECLARE_INTERFACE_CHECKER
"""
+ regexp = S(RE_MACRO_DEFINE,
+ 'INTERFACE_CHECK',
+ r'\s*\(\s*', OR(NAMED('instancetype', RE_IDENTIFIER), RE_TYPE, name='c_type'),
+ r'\s*,', CPP_SPACE,
+ OPTIONAL_PARS(RE_IDENTIFIER), r',', CPP_SPACE,
+ NAMED('qom_typename', RE_IDENTIFIER), r'\s*\)\n')
+
+ def required_identifiers(self) -> Iterable[RequiredIdentifier]:
+ yield RequiredIdentifier('include', '"qom/object.h"')
+ yield RequiredIdentifier('type', self.group('instancetype'))
+ yield RequiredIdentifier('constant', self.group('qom_typename'))
+
+ def gen_patches(self) -> Iterable[Patch]:
+ if self.file.filename_matches('qom/object.h'):
+ self.debug("skipping object.h")
+ return
+
+ typename = self.group('qom_typename')
+ uppercase = self.name
+ instancetype = self.group('instancetype')
+ c = f"DECLARE_INTERFACE_CHECKER({instancetype}, {uppercase},\n"+\
+ f" {typename})\n"
+ yield self.make_patch(c)
+
+
+class TypeDeclaration(FileMatch):
+ """Parent class to all type declarations"""
+ @property
+ def instancetype(self) -> Optional[str]:
+ return self.getgroup('instancetype')
+
+ @property
+ def classtype(self) -> Optional[str]:
+ return self.getgroup('classtype')
+
+ @property
+ def typename(self) -> Optional[str]:
+ return self.getgroup('typename')
+
+class TypeCheckerDeclaration(TypeDeclaration):
+ """Parent class to all type checker declarations"""
+ @property
+ def typename(self) -> str:
+ return self.group('typename')
+
+ @property
+ def uppercase(self) -> str:
+ return self.group('uppercase')
+
+class DeclareInstanceChecker(TypeCheckerDeclaration):
+ """DECLARE_INSTANCE_CHECKER use"""
#TODO: replace lonely DECLARE_INSTANCE_CHECKER with DECLARE_OBJ_CHECKERS
# if all types are found.
# This will require looking up the correct class type in the TypeInfo
yield RequiredIdentifier('constant', self.group('typename'))
yield RequiredIdentifier('type', self.group('instancetype'))
-class DeclareClassCheckers(FileMatch):
- """DECLARE_INSTANCE_CHECKER use"""
+class DeclareInterfaceChecker(TypeCheckerDeclaration):
+ """DECLARE_INTERFACE_CHECKER use"""
+ regexp = S(r'^[ \t]*DECLARE_INTERFACE_CHECKER\s*\(\s*',
+ NAMED('instancetype', RE_TYPE), r'\s*,\s*',
+ NAMED('uppercase', RE_IDENTIFIER), r'\s*,\s*',
+ OR(RE_IDENTIFIER, RE_STRING, RE_MACRO_CONCAT, RE_FUN_CALL, name='typename'), SP,
+ r'\)[ \t]*;?[ \t]*\n')
+
+ def required_identifiers(self) -> Iterable[RequiredIdentifier]:
+ yield RequiredIdentifier('include', '"qom/object.h"')
+ yield RequiredIdentifier('constant', self.group('typename'))
+ yield RequiredIdentifier('type', self.group('instancetype'))
+
+class DeclareInstanceType(TypeDeclaration):
+ """DECLARE_INSTANCE_TYPE use"""
+ regexp = S(r'^[ \t]*DECLARE_INSTANCE_TYPE\s*\(\s*',
+ NAMED('uppercase', RE_IDENTIFIER), r'\s*,\s*',
+ NAMED('instancetype', RE_TYPE), SP,
+ r'\)[ \t]*;?[ \t]*\n')
+
+ def required_identifiers(self) -> Iterable[RequiredIdentifier]:
+ yield RequiredIdentifier('include', '"qom/object.h"')
+ yield RequiredIdentifier('type', self.group('instancetype'))
+
+class DeclareClassType(TypeDeclaration):
+ """DECLARE_CLASS_TYPE use"""
+ regexp = S(r'^[ \t]*DECLARE_CLASS_TYPE\s*\(\s*',
+ NAMED('uppercase', RE_IDENTIFIER), r'\s*,\s*',
+ NAMED('classtype', RE_TYPE), SP,
+ r'\)[ \t]*;?[ \t]*\n')
+
+ def required_identifiers(self) -> Iterable[RequiredIdentifier]:
+ yield RequiredIdentifier('include', '"qom/object.h"')
+ yield RequiredIdentifier('type', self.group('classtype'))
+
+
+
+class DeclareClassCheckers(TypeCheckerDeclaration):
+ """DECLARE_CLASS_CHECKER use"""
regexp = S(r'^[ \t]*DECLARE_CLASS_CHECKERS\s*\(\s*',
NAMED('classtype', RE_TYPE), r'\s*,\s*',
NAMED('uppercase', RE_IDENTIFIER), r'\s*,\s*',
yield RequiredIdentifier('constant', self.group('typename'))
yield RequiredIdentifier('type', self.group('classtype'))
-class DeclareObjCheckers(FileMatch):
- """DECLARE_OBJ_CHECKERS use
- Will be replaced with OBJECT_DECLARE_TYPE if possible
- """
+class DeclareObjCheckers(TypeCheckerDeclaration):
+ """DECLARE_OBJ_CHECKERS use"""
#TODO: detect when OBJECT_DECLARE_SIMPLE_TYPE can be used
regexp = S(r'^[ \t]*DECLARE_OBJ_CHECKERS\s*\(\s*',
NAMED('instancetype', RE_TYPE), r'\s*,\s*',
yield RequiredIdentifier('type', self.group('classtype'))
yield RequiredIdentifier('type', self.group('instancetype'))
- def gen_patches(self):
- ids = TypeIdentifiers(uppercase=self.group('uppercase'),
- typename=self.group('typename'),
- classtype=self.group('classtype'),
- instancetype=self.group('instancetype'))
- issues = ids.check_consistency()
- if issues:
- for i in issues:
- self.warn("inconsistent identifiers: %s", i)
+class TypeDeclarationFixup(FileMatch):
+ """Common base class for code that will look at a set of type declarations"""
+ regexp = RE_FILE_BEGIN
+ def gen_patches(self) -> Iterable[Patch]:
+ if self.file.filename_matches('qom/object.h'):
+ self.debug("skipping object.h")
return
- if self.group('typename') != 'TYPE_'+self.group('uppercase'):
- self.warn("type %s mismatch with uppercase name %s", ids.typename, ids.uppercase)
- return
+ # group checkers by uppercase name:
+ decl_types: List[Type[TypeDeclaration]] = [DeclareInstanceChecker, DeclareInstanceType,
+ DeclareClassCheckers, DeclareClassType,
+ DeclareObjCheckers]
+ checker_dict: Dict[str, List[TypeDeclaration]] = {}
+ for t in decl_types:
+ for m in self.file.matches_of_type(t):
+ checker_dict.setdefault(m.group('uppercase'), []).append(m)
+ self.debug("checker_dict: %r", checker_dict)
+ for uppercase,checkers in checker_dict.items():
+ fields = ('instancetype', 'classtype', 'uppercase', 'typename')
+ fvalues = dict((field, set(getattr(m, field) for m in checkers
+ if getattr(m, field, None) is not None))
+ for field in fields)
+ for field,values in fvalues.items():
+ if len(values) > 1:
+ for c in checkers:
+ c.warn("%s mismatch (%s)", field, ' '.join(values))
+ return
- typedefs = [(t,self.file.find_match(SimpleTypedefMatch, t))
- for t in (ids.instancetype, ids.classtype)]
- for t,td in typedefs:
- if td is None:
- self.warn("typedef %s not found", t)
- break
- if td.start() > self.start():
- self.warn("typedef %s needs to be move earlier in the file", t)
- break
- #HACK: check if typedef is used between its definition and the macro
- #TODO: check if the only match is inside the "struct { ... }" declaration
- if re.search(r'\b'+t+r'\b', self.file.original_content[td.end():self.start()]):
- self.warn("typedef %s can't be moved, it is used before the macro", t)
- break
- else:
- for t,td in typedefs:
- yield td.make_removal_patch()
+ field_dict = dict((f, v.pop() if v else None) for f,v in fvalues.items())
+ yield from self.gen_patches_for_type(uppercase, checkers, field_dict)
+
+ def find_conflicts(self, uppercase: str, checkers: List[TypeDeclaration]) -> bool:
+ """Look for conflicting declarations that would make it unsafe to add new ones"""
+ conflicting: List[FileMatch] = []
+ # conflicts in the same file:
+ conflicting.extend(chain(self.file.find_matches(DefineDirective, uppercase),
+ self.file.find_matches(DeclareInterfaceChecker, uppercase, 'uppercase'),
+ self.file.find_matches(DeclareClassType, uppercase, 'uppercase'),
+ self.file.find_matches(DeclareInstanceType, uppercase, 'uppercase')))
+
+ # conflicts in another file:
+ conflicting.extend(o for o in chain(self.allfiles.find_matches(DeclareInstanceChecker, uppercase, 'uppercase'),
+ self.allfiles.find_matches(DeclareClassCheckers, uppercase, 'uppercase'),
+ self.allfiles.find_matches(DeclareInterfaceChecker, uppercase, 'uppercase'),
+ self.allfiles.find_matches(DefineDirective, uppercase))
+ if o is not None and o.file != self.file
+ # if both are .c files, there's no conflict at all:
+ and not (o.file.filename.suffix == '.c' and
+ self.file.filename.suffix == '.c'))
+
+ if conflicting:
+ for c in checkers:
+ c.warn("skipping due to conflicting %s macro", uppercase)
+ for o in conflicting:
+ if o is None:
+ continue
+ o.warn("conflicting %s macro is here", uppercase)
+ return True
- lowercase = ids.uppercase.lower()
- # all is OK, we can replace the macro!
- c = (f'OBJECT_DECLARE_TYPE({ids.instancetype}, {ids.classtype},\n'
- f' {lowercase}, {ids.uppercase})\n')
- yield self.make_patch(c)
+ return False
+
+ def gen_patches_for_type(self, uppercase: str,
+ checkers: List[TypeDeclaration],
+ fields: Dict[str, Optional[str]]) -> Iterable[Patch]:
+ """Should be reimplemented by subclasses"""
+ return
+ yield
+
+class DeclareVoidTypes(TypeDeclarationFixup):
+ """Add DECLARE_*_TYPE(..., void) when there's no declared type"""
+ regexp = RE_FILE_BEGIN
+ def gen_patches_for_type(self, uppercase: str,
+ checkers: List[TypeDeclaration],
+ fields: Dict[str, Optional[str]]) -> Iterable[Patch]:
+ if self.find_conflicts(uppercase, checkers):
+ return
+
+ #_,last_checker = max((m.start(), m) for m in checkers)
+ _,first_checker = min((m.start(), m) for m in checkers)
+
+ if not any(m.instancetype for m in checkers):
+ yield first_checker.prepend(f'DECLARE_INSTANCE_TYPE({uppercase}, void)\n')
+ if not any(m.classtype for m in checkers):
+ yield first_checker.prepend(f'DECLARE_CLASS_TYPE({uppercase}, void)\n')
+
+ #if not all(len(v) == 1 for v in fvalues.values()):
+ # return
+ #
+ #final_values = dict((field, values.pop())
+ # for field,values in fvalues.items())
+ #s = (f"DECLARE_OBJ_CHECKERS({final_values['instancetype']}, {final_values['classtype']},\n"+
+ # f" {final_values['uppercase']}, {final_values['typename']})\n")
+ #for c in checkers:
+ # yield c.make_removal_patch()
+ #yield last_checker.append(s)
+
+
+class AddDeclareTypeName(TypeDeclarationFixup):
+ """Add DECLARE_TYPE_NAME declarations if necessary"""
+ def gen_patches_for_type(self, uppercase: str,
+ checkers: List[TypeDeclaration],
+ fields: Dict[str, Optional[str]]) -> Iterable[Patch]:
+ typename = fields.get('typename')
+ if typename is None:
+ self.warn("typename unavailable")
+ return
+ if typename == f'TYPE_{uppercase}':
+ self.info("already using TYPE_%s as type name", uppercase)
+ return
+ if self.file.find_match(DeclareTypeName, uppercase, 'uppercase'):
+ self.info("type name for %s already declared", uppercase)
+ return
+ _,first_checker = min((m.start(), m) for m in checkers)
+ s = f'DECLARE_TYPE_NAME({uppercase}, {typename})\n'
+ yield first_checker.prepend(s)
class TrivialClassStruct(FileMatch):
"""Trivial class struct"""
OR(RE_IDENTIFIER, RE_STRING, RE_MACRO_CONCAT, RE_FUN_CALL, name='typename'),
r'\s*\);?[ \t]*\n')
-class ObjectDeclareType(FileMatch):
+class ObjectDeclareType(TypeCheckerDeclaration):
"""OBJECT_DECLARE_TYPE usage
Will be replaced with OBJECT_DECLARE_SIMPLE_TYPE if possible
"""
regexp = S(r'^[ \t]*OBJECT_DECLARE_TYPE\s*\(',
NAMED('instancetype', RE_TYPE), r'\s*,\s*',
NAMED('classtype', RE_TYPE), r'\s*,\s*',
- NAMED('lowercase', RE_IDENTIFIER), r'\s*,\s*',
NAMED('uppercase', RE_IDENTIFIER), SP,
r'\)[ \t]*;?[ \t]*\n')
" %(uppercase)s, %(parent_struct)s)\n" % d)
yield self.make_patch(c)
-def find_type_declaration(files: FileList, typename: str) -> Optional[FileMatch]:
- """Find usage of DECLARE*CHECKER macro"""
- for c in (DeclareInstanceChecker, DeclareClassCheckers, DeclareObjCheckers, DeclareTypeName):
- d = files.find_match(c, name=typename, group='typename')
- if d:
- return d
+class ObjectDeclareSimpleType(TypeCheckerDeclaration):
+ """OBJECT_DECLARE_SIMPLE_TYPE usage"""
+ regexp = S(r'^[ \t]*OBJECT_DECLARE_SIMPLE_TYPE\s*\(',
+ NAMED('instancetype', RE_TYPE), r'\s*,\s*',
+ NAMED('uppercase', RE_IDENTIFIER), SP,
+ r'\)[ \t]*;?[ \t]*\n')
+
+class OldStyleObjectDeclareSimpleType(TypeCheckerDeclaration):
+ """OBJECT_DECLARE_SIMPLE_TYPE usage (old API)"""
+ regexp = S(r'^[ \t]*OBJECT_DECLARE_SIMPLE_TYPE\s*\(',
+ NAMED('instancetype', RE_TYPE), r'\s*,\s*',
+ NAMED('lowercase', RE_IDENTIFIER), r'\s*,\s*',
+ NAMED('uppercase', RE_IDENTIFIER), r'\s*,\s*',
+ NAMED('parent_classtype', RE_TYPE), SP,
+ r'\)[ \t]*;?[ \t]*\n')
+
+ @property
+ def classtype(self) -> Optional[str]:
+ instancetype = self.instancetype
+ assert instancetype
+ return f"{instancetype}Class"
+
+def find_typename_uppercase(files: FileList, typename: str) -> Optional[str]:
+ """Try to find what's the right MODULE_OBJ_NAME for a given type name"""
+ decl = files.find_match(DeclareTypeName, name=typename, group='typename')
+ if decl:
+ return decl.group('uppercase')
+ if typename.startswith('TYPE_'):
+ return typename[len('TYPE_'):]
return None
+def find_type_checkers(files:FileList, name:str, group:str='uppercase') -> Iterable[TypeCheckerDeclaration]:
+ """Find usage of DECLARE*CHECKER macro"""
+ c: Type[TypeCheckerDeclaration]
+ for c in (DeclareInstanceChecker, DeclareClassCheckers, DeclareObjCheckers, ObjectDeclareType, ObjectDeclareSimpleType):
+ yield from files.find_matches(c, name=name, group=group)
class Include(FileMatch):
"""#include directive"""
regexp = RE_FILE_BEGIN
def gen_patches(self) -> Iterator[Patch]:
+ if self.file.filename_matches('qom/object.h'):
+ self.debug("skipping object.h")
+ return
+
index: Dict[RequiredIdentifier, SymbolUserList] = {}
definition_classes = [SimpleTypedefMatch, FullStructTypedefMatch, ConstantDefine, Include]
- user_classes = [TypeCheckMacro, DeclareObjCheckers, DeclareInstanceChecker, DeclareClassCheckers]
+ user_classes = [TypeCheckMacro, DeclareObjCheckers, DeclareInstanceChecker, DeclareClassCheckers, InterfaceCheckMacro]
# first we scan for all symbol definitions and usage:
for dc in definition_classes:
definition.warn("definition of %s %s needs to be moved earlier in the file", i.type, i.name)
earliest.warn("definition of %s %s is used here", i.type, i.name)
+
+class EmptyPreprocessorConditional(FileMatch):
+ """Delete empty preprocessor conditionals"""
+ regexp = r'^[ \t]*#(if|ifdef)[ \t].*\n+[ \t]*#endif[ \t]*\n'
+ def gen_patches(self) -> Iterable[Patch]:
+ yield self.make_removal_patch()
RE_TYPEINFO_START = S(r'^[ \t]*', M(r'(static|const)\s+', name='modifiers'), r'TypeInfo\s+',
NAMED('name', RE_IDENTIFIER), r'\s*=\s*{[ \t]*\n')
-RE_TYPEINFO_DEF = S(RE_TYPEINFO_START,
- M(NAMED('fields', RE_TI_FIELDS),
- SP, NAMED('endcomments', RE_COMMENTS),
- r'};?\n',
- n='?', name='fullspec'))
ParsedArray = List[str]
ParsedInitializerValue = Union[str, ParsedArray]
raw: str
parsed: Optional[ParsedInitializerValue]
match: Optional[Match]
-TypeInfoInitializers = Dict[str, InitializerValue]
-
-def parse_array(m: Match) -> ParsedArray:
- #DBG('parse_array: %r', m.group(0))
- return [m.group('arrayitem') for m in re.finditer(RE_ARRAY_ITEM, m.group('arrayitems'))]
-
-def parse_initializer_value(m: Match, s: str) -> InitializerValue:
- parsed: Optional[ParsedInitializerValue] = None
- #DBG("parse_initializer_value: %r", s)
- array = re.match(RE_ARRAY, s)
- if array:
- parsed = parse_array(array)
- return InitializerValue(s, parsed, m)
-
-class TypeInfoVar(FileMatch):
- """TypeInfo variable declaration with initializer
- Will be replaced by OBJECT_DEFINE_TYPE_EXTENDED macro
- (not implemented yet)
+
+class ArrayItem(FileMatch):
+ regexp = RE_ARRAY_ITEM
+
+class ArrayInitializer(FileMatch):
+ regexp = RE_ARRAY
+
+ def parsed(self) -> ParsedArray:
+ #DBG('parse_array: %r', m.group(0))
+ return [m.group('arrayitem') for m in self.group_finditer(ArrayItem, 'arrayitems')]
+
+class FieldInitializer(FileMatch):
+ regexp = RE_TI_FIELD_INIT
+
+ @property
+ def raw(self) -> str:
+ return self.group('value')
+
+ @property
+ def parsed(self) -> ParsedInitializerValue:
+ parsed: ParsedInitializerValue = self.raw
+ #DBG("parse_initializer_value: %r", s)
+ array = self.try_group_match(ArrayInitializer, 'value')
+ if array:
+ assert isinstance(array, ArrayInitializer)
+ return array.parsed()
+ return parsed
+
+TypeInfoInitializers = Dict[str, FieldInitializer]
+
+class TypeDefinition(FileMatch):
+ """
+ Common base class for type definitions (TypeInfo variables or OBJECT_DEFINE* macros)
"""
- regexp = RE_TYPEINFO_DEF
+ @property
+ def instancetype(self) -> Optional[str]:
+ return self.group('instancetype')
+
+ @property
+ def classtype(self) -> Optional[str]:
+ return self.group('classtype')
+
+ @property
+ def uppercase(self) -> Optional[str]:
+ return self.group('uppercase')
+
+ @property
+ def parent_uppercase(self) -> str:
+ return self.group('parent_uppercase')
@property
def initializers(self) -> Optional[TypeInfoInitializers]:
fields = self.group('fields')
if fields is None:
return None
- d = dict((fm.group('field'), parse_initializer_value(fm, fm.group('value')))
- for fm in re.finditer(RE_TI_FIELD_INIT, fields))
- self._initializers = d
- return d
+ d = dict((fm.group('field'), fm)
+ for fm in self.group_finditer(FieldInitializer, 'fields'))
+ self._initializers = d # type: ignore
+ return self._initializers
+
+
+class TypeInfoVar(TypeDefinition):
+ """TypeInfo variable declaration with initializer"""
+ regexp = S(NAMED('begin', RE_TYPEINFO_START),
+ M(NAMED('fields', RE_TI_FIELDS),
+ NAMED('endcomments', SP, RE_COMMENTS),
+ NAMED('end', r'};?\n'),
+ n='?', name='fullspec'))
def is_static(self) -> bool:
return 'static' in self.group('modifiers')
+ def is_const(self) -> bool:
+ return 'const' in self.group('modifiers')
+
def is_full(self) -> bool:
return bool(self.group('fullspec'))
return {}
return self.initializers
- def get_initializer_value(self, field: str) -> InitializerValue:
- return self.get_initializers().get(field, InitializerValue('', '', None))
+ def get_raw_initializer_value(self, field: str, default: str = '') -> str:
+ initializers = self.get_initializers()
+ if field in initializers:
+ return initializers[field].raw
+ else:
+ return default
+
+ @property
+ def typename(self) -> Optional[str]:
+ return self.get_raw_initializer_value('name')
+
+ @property
+ def uppercase(self) -> Optional[str]:
+ typename = self.typename
+ if not typename:
+ return None
+ if not typename.startswith('TYPE_'):
+ return None
+ return typename[len('TYPE_'):]
+
+ @property
+ def classtype(self) -> Optional[str]:
+ class_size = self.get_raw_initializer_value('class_size')
+ if not class_size:
+ return None
+ m = re.fullmatch(RE_SIZEOF, class_size)
+ if not m:
+ return None
+ return m.group('sizeoftype')
+
+ @property
+ def instancetype(self) -> Optional[str]:
+ instance_size = self.get_raw_initializer_value('instance_size')
+ if not instance_size:
+ return None
+ m = re.fullmatch(RE_SIZEOF, instance_size)
+ if not m:
+ return None
+ return m.group('sizeoftype')
+
#def extract_identifiers(self) -> Optional[TypeIdentifiers]:
# """Try to extract identifiers from names being used"""
# uppercase=uppercase, lowercase=lowercase,
# instancetype=instancetype, classtype=classtype)
- def append_field(self, field, value) -> Patch:
+ def append_field(self, field: str, value: str) -> Patch:
"""Generate patch appending a field initializer"""
content = f' .{field} = {value},\n'
- return Patch(self.match.end('fields'), self.match.end('fields'),
- content)
+ fm = self.group_match('fields')
+ assert fm
+ return fm.append(content)
def patch_field(self, field: str, replacement: str) -> Patch:
"""Generate patch replacing a field initializer"""
- values = self.initializers
- assert values
- value = values.get(field)
+ initializers = self.initializers
+ assert initializers
+ value = initializers.get(field)
assert value
- fm = value.match
- assert fm
- fstart = self.match.start('fields') + fm.start()
- fend = self.match.start('fields') + fm.end()
- return Patch(fstart, fend, replacement)
+ return value.make_patch(replacement)
+
+ def remove_field(self, field: str) -> Iterable[Patch]:
+ initializers = self.initializers
+ assert initializers
+ if field in initializers:
+ yield self.patch_field(field, '')
+
+ def remove_fields(self, *fields: str) -> Iterable[Patch]:
+ for f in fields:
+ yield from self.remove_field(f)
+
+ def patch_field_value(self, field: str, replacement: str) -> Patch:
+ """Replace just the value of a field initializer"""
+ initializers = self.initializers
+ assert initializers
+ value = initializers.get(field)
+ assert value
+ vm = value.group_match('value')
+ assert vm
+ return vm.make_patch(replacement)
+
+
+class RemoveRedundantClassSize(TypeInfoVar):
+ """Remove class_size when using OBJECT_DECLARE_SIMPLE_TYPE"""
+ def gen_patches(self) -> Iterable[Patch]:
+ initializers = self.initializers
+ if initializers is None:
+ return
+ if 'class_size' not in initializers:
+ return
+
+ self.debug("Handling %s", self.name)
+ m = re.fullmatch(RE_SIZEOF, initializers['class_size'].raw)
+ if not m:
+ self.warn("%s class_size is not sizeof?", self.name)
+ return
+ classtype = m.group('sizeoftype')
+ if not classtype.endswith('Class'):
+ self.warn("%s class size type (%s) is not *Class?", self.name, classtype)
+ return
+ self.debug("classtype is %s", classtype)
+ instancetype = classtype[:-len('Class')]
+ self.debug("intanceypte is %s", instancetype)
+ self.debug("searching for simpletype declaration using %s as InstanceType", instancetype)
+ decl = self.allfiles.find_match(OldStyleObjectDeclareSimpleType,
+ instancetype, 'instancetype')
+ if not decl:
+ self.debug("No simpletype declaration found for %s", instancetype)
+ return
+ self.debug("Found simple type declaration")
+ decl.debug("declaration is here")
+ yield from self.remove_field('class_size')
+class RemoveDeclareSimpleTypeArg(OldStyleObjectDeclareSimpleType):
+ """Remove class_size when using OBJECT_DECLARE_SIMPLE_TYPE"""
def gen_patches(self) -> Iterable[Patch]:
+ c = (f'OBJECT_DECLARE_SIMPLE_TYPE({self.group("instancetype")}, {self.group("lowercase")},\n'
+ f' {self.group("uppercase")})\n')
+ yield self.make_patch(c)
+
+class UseDeclareTypeExtended(TypeInfoVar):
+ """Replace TypeInfo variable with OBJECT_DEFINE_TYPE_EXTENDED"""
+ def gen_patches(self) -> Iterable[Patch]:
+ # this will just ensure the caches for find_match() and matches_for_type()
+ # will be loaded in advance:
+ find_type_checkers(self.allfiles, 'xxxxxxxxxxxxxxxxx')
+
+ if not self.is_static():
+ self.info("Skipping non-static TypeInfo variable")
+ return
+
+ type_info_macro = self.file.find_match(TypeInfoMacro, self.name)
+ if not type_info_macro:
+ self.warn("TYPE_INFO(%s) line not found", self.name)
+ return
+
values = self.initializers
if values is None:
return
if 'name' not in values:
self.warn("name not set in TypeInfo variable %s", self.name)
return
+
typename = values['name'].raw
+
if 'parent' not in values:
self.warn("parent not set in TypeInfo variable %s", self.name)
return
self.warn("class_size is set to: %r", values['class_size'].raw)
return
- #NOTE: this will NOT work after declarations are converted
- # to OBJECT_DECLARE*
+ #for t in (typename, parent_typename):
+ # if not re.fullmatch(RE_IDENTIFIER, t):
+ # self.info("type name is not a macro/constant")
+ # if instancetype or classtype:
+ # self.warn("macro/constant type name is required for instance/class type")
+ # if not self.file.force:
+ # return
# Now, the challenge is to find out the right MODULE_OBJ_NAME for the
# type and for the parent type
- instance_decl = find_type_declaration(self.allfiles, typename)
- parent_decl = find_type_declaration(self.allfiles, parent_typename)
-
self.info("TypeInfo variable for %s is here", typename)
- if instance_decl:
- instance_decl.info("instance type declaration (%s) is here", instance_decl.match.group('uppercase'))
- if parent_decl:
- parent_decl.info("parent type declaration (%s) is here", parent_decl.match.group('uppercase'))
+ uppercase = find_typename_uppercase(self.allfiles, typename)
+ if not uppercase:
+ self.info("Can't find right uppercase name for %s", typename)
+ if instancetype or classtype:
+ self.warn("Can't find right uppercase name for %s", typename)
+ self.warn("This will make type validation difficult in the future")
+ return
- ok = True
- if (instance_decl is None and (instancetype or classtype)):
- self.warn("Can't find where type checkers for %s are declared. We need them to validate sizes of %s", typename, self.name)
- ok = False
-
- if (instance_decl is not None
- and 'instancetype' in instance_decl.match.groupdict()
- and instancetype != instance_decl.group('instancetype')):
- self.warn("type at instance_size is %r. Should instance_size be set to sizeof(%s) ?",
- instancetype, instance_decl.group('instancetype'))
- instance_decl.warn("Type checker declaration for %s is here", typename)
- ok = False
- if (instance_decl is not None
- and 'classtype' in instance_decl.match.groupdict()
- and classtype != instance_decl.group('classtype')):
- self.warn("type at class_size is %r. Should class_size be set to sizeof(%s) ?",
- classtype, instance_decl.group('classtype'))
- instance_decl.warn("Type checker declaration for %s is here", typename)
- ok = False
-
- if not ok:
+ parent_uppercase = find_typename_uppercase(self.allfiles, parent_typename)
+ if not parent_uppercase:
+ self.info("Can't find right uppercase name for parent type (%s)", parent_typename)
+ if instancetype or classtype:
+ self.warn("Can't find right uppercase name for parent type (%s)", parent_typename)
+ self.warn("This will make type validation difficult in the future")
return
+ ok = True
+
+ #checkers: List[TypeCheckerDeclaration] = list(find_type_checkers(self.allfiles, uppercase))
+ #for c in checkers:
+ # c.info("instance type checker declaration (%s) is here", c.group('uppercase'))
+ #if not checkers:
+ # self.info("No type checkers declared for %s", uppercase)
+ # if instancetype or classtype:
+ # self.warn("Can't find where type checkers for %s (%s) are declared. We will need them to validate sizes of %s",
+ # typename, uppercase, self.name)
+
+ if not instancetype:
+ instancetype = 'void'
+ if not classtype:
+ classtype = 'void'
+
+ #checker_instancetypes = set(c.instancetype for c in checkers
+ # if c.instancetype is not None)
+ #if len(checker_instancetypes) > 1:
+ # self.warn("ambiguous set of type checkers")
+ # for c in checkers:
+ # c.warn("instancetype is %s here", c.instancetype)
+ # ok = False
+ #elif len(checker_instancetypes) == 1:
+ # checker_instancetype = checker_instancetypes.pop()
+ # DBG("checker instance type: %r", checker_instancetype)
+ # if instancetype != checker_instancetype:
+ # self.warn("type at instance_size is %r. Should instance_size be set to sizeof(%s) ?",
+ # instancetype, checker_instancetype)
+ # ok = False
+ #else:
+ # if instancetype != 'void':
+ # self.warn("instance type checker for %s (%s) not found", typename, instancetype)
+ # ok = False
+
+ #checker_classtypes = set(c.classtype for c in checkers
+ # if c.classtype is not None)
+ #if len(checker_classtypes) > 1:
+ # self.warn("ambiguous set of type checkers")
+ # for c in checkers:
+ # c.warn("classtype is %s here", c.classtype)
+ # ok = False
+ #elif len(checker_classtypes) == 1:
+ # checker_classtype = checker_classtypes.pop()
+ # DBG("checker class type: %r", checker_classtype)
+ # if classtype != checker_classtype:
+ # self.warn("type at class_size is %r. Should class_size be set to sizeof(%s) ?",
+ # classtype, checker_classtype)
+ # ok = False
+ #else:
+ # if classtype != 'void':
+ # self.warn("class type checker for %s (%s) not found", typename, classtype)
+ # ok = False
+
+ #if not ok:
+ # for c in checkers:
+ # c.warn("Type checker declaration for %s (%s) is here",
+ # typename, type(c).__name__)
+ # return
+
#if parent_decl is None:
# self.warn("Can't find where parent type %s is declared", parent_typename)
+ #yield self.prepend(f'DECLARE_TYPE_NAME({uppercase}, {typename})\n')
+ #if not instancetype:
+ # yield self.prepend(f'DECLARE_INSTANCE_TYPE({uppercase}, void)\n')
+ #if not classtype:
+ # yield self.prepend(f'DECLARE_CLASS_TYPE({uppercase}, void)\n')
self.info("%s can be patched!", self.name)
- return
- yield
+ replaced_fields = ['name', 'parent', 'instance_size', 'class_size']
+ begin = self.group_match('begin')
+ newbegin = f'OBJECT_DEFINE_TYPE_EXTENDED({self.name},\n'
+ newbegin += f' {instancetype}, {classtype},\n'
+ newbegin += f' {uppercase}, {parent_uppercase}'
+ if set(values.keys()) - set(replaced_fields):
+ newbegin += ',\n'
+ yield begin.make_patch(newbegin)
+ yield from self.remove_fields(*replaced_fields)
+ end = self.group_match('end')
+ yield end.make_patch(')\n')
+ yield type_info_macro.make_removal_patch()
+
+class ObjectDefineTypeExtended(TypeDefinition):
+ """OBJECT_DEFINE_TYPE_EXTENDED usage"""
+ regexp = S(r'^[ \t]*OBJECT_DEFINE_TYPE_EXTENDED\s*\(\s*',
+ NAMED('name', RE_IDENTIFIER), r'\s*,\s*',
+ NAMED('instancetype', RE_IDENTIFIER), r'\s*,\s*',
+ NAMED('classtype', RE_IDENTIFIER), r'\s*,\s*',
+ NAMED('uppercase', RE_IDENTIFIER), r'\s*,\s*',
+ NAMED('parent_uppercase', RE_IDENTIFIER),
+ M(r',\s*\n',
+ NAMED('fields', RE_TI_FIELDS),
+ n='?'),
+ r'\s*\);?\n?')
+
+class ObjectDefineType(TypeDefinition):
+ """OBJECT_DEFINE_TYPE usage"""
+ regexp = S(r'^[ \t]*OBJECT_DEFINE_TYPE\s*\(\s*',
+ NAMED('lowercase', RE_IDENTIFIER), r'\s*,\s*',
+ NAMED('uppercase', RE_IDENTIFIER), r'\s*,\s*',
+ NAMED('parent_uppercase', RE_IDENTIFIER),
+ M(r',\s*\n',
+ NAMED('fields', RE_TI_FIELDS),
+ n='?'),
+ r'\s*\);?\n?')
+
+def find_type_definitions(files: FileList, uppercase: str) -> Iterable[TypeDefinition]:
+ types: List[Type[TypeDefinition]] = [TypeInfoVar, ObjectDefineType, ObjectDefineTypeExtended]
+ for t in types:
+ for m in files.matches_of_type(t):
+ m.debug("uppercase: %s", m.uppercase)
+ yield from (m for t in types
+ for m in files.matches_of_type(t)
+ if m.uppercase == uppercase)
+
+class AddDeclareVoidClassType(TypeDeclarationFixup):
+ """Will add DECLARE_CLASS_TYPE(..., void) if possible"""
+ def gen_patches_for_type(self, uppercase: str,
+ checkers: List[TypeDeclaration],
+ fields: Dict[str, Optional[str]]) -> Iterable[Patch]:
+ defs = list(find_type_definitions(self.allfiles, uppercase))
+ if len(defs) > 1:
+ self.warn("multiple definitions for %s", uppercase)
+ for d in defs:
+ d.warn("definition found here")
+ return
+ elif len(defs) == 0:
+ self.warn("type definition for %s not found", uppercase)
+ return
+ d = defs[0]
+ if d.classtype is None:
+ d.info("definition for %s has classtype, skipping", uppercase)
+ return
+ class_type_checkers = [c for c in checkers
+ if c.classtype is not None]
+ if class_type_checkers:
+ for c in class_type_checkers:
+ c.warn("class type checker for %s is present here", uppercase)
+ return
+
+ _,last_checker = max((m.start(), m) for m in checkers)
+ s = f'DECLARE_CLASS_TYPE({uppercase}, void)\n'
+ yield last_checker.append(s)
+
+class AddDeclareVoidInstanceType(FileMatch):
+ """Will add DECLARE_INSTANCE_TYPE(..., void) if possible"""
+ regexp = S(r'^[ \t]*#[ \t]*define', CPP_SPACE,
+ NAMED('name', r'TYPE_[a-zA-Z0-9_]+\b'),
+ CPP_SPACE, r'.*\n')
+
+ def gen_patches(self) -> Iterable[Patch]:
+ assert self.name.startswith('TYPE_')
+ uppercase = self.name[len('TYPE_'):]
+ defs = list(find_type_definitions(self.allfiles, uppercase))
+ if len(defs) > 1:
+ self.warn("multiple definitions for %s", uppercase)
+ for d in defs:
+ d.warn("definition found here")
+ return
+ elif len(defs) == 0:
+ self.warn("type definition for %s not found", uppercase)
+ return
+ d = defs[0]
+ instancetype = d.instancetype
+ if instancetype is not None and instancetype != 'void':
+ return
+
+ instance_checkers = [c for c in find_type_checkers(self.allfiles, uppercase)
+ if c.instancetype]
+ if instance_checkers:
+ d.warn("instance type checker for %s already declared", uppercase)
+ for c in instance_checkers:
+ c.warn("instance checker for %s is here", uppercase)
+ return
+
+ s = f'DECLARE_INSTANCE_TYPE({uppercase}, void)\n'
+ yield self.append(s)
+
+class AddObjectDeclareType(DeclareObjCheckers):
+ """Will add OBJECT_DECLARE_TYPE(...) if possible"""
+ def gen_patches(self) -> Iterable[Patch]:
+ uppercase = self.uppercase
+ typename = self.group('typename')
+ instancetype = self.group('instancetype')
+ classtype = self.group('classtype')
+
+ if typename != f'TYPE_{uppercase}':
+ self.warn("type name mismatch: %s vs %s", typename, uppercase)
+ return
+
+ typedefs = [(t,self.allfiles.find_matches(SimpleTypedefMatch, t))
+ for t in (instancetype, classtype)]
+ for t,tds in typedefs:
+ if not tds:
+ self.warn("typedef %s not found", t)
+ return
+ for td in tds:
+ td_type = td.group('typedef_type')
+ if td_type != f'struct {t}':
+ self.warn("typedef mismatch: %s is defined as %s", t, td_type)
+ td.warn("typedef is here")
+ return
+
+ # look for reuse of same struct type
+ other_instance_checkers = [c for c in find_type_checkers(self.allfiles, instancetype, 'instancetype')
+ if c.uppercase != uppercase]
+ if other_instance_checkers:
+ self.warn("typedef %s is being reused", instancetype)
+ for ic in other_instance_checkers:
+ ic.warn("%s is reused here", instancetype)
+ if not self.file.force:
+ return
+
+ decl_types: List[Type[TypeDeclaration]] = [DeclareClassCheckers, DeclareObjCheckers]
+ class_decls = [m for t in decl_types
+ for m in self.allfiles.find_matches(t, uppercase, 'uppercase')]
+
+ defs = list(find_type_definitions(self.allfiles, uppercase))
+ if len(defs) > 1:
+ self.warn("multiple definitions for %s", uppercase)
+ for d in defs:
+ d.warn("definition found here")
+ if not self.file.force:
+ return
+ elif len(defs) == 0:
+ self.warn("type definition for %s not found", uppercase)
+ if not self.file.force:
+ return
+ else:
+ d = defs[0]
+ if d.instancetype != instancetype:
+ self.warn("mismatching instance type for %s (%s)", uppercase, instancetype)
+ d.warn("instance type declared here (%s)", d.instancetype)
+ if not self.file.force:
+ return
+ if d.classtype != classtype:
+ self.warn("mismatching class type for %s (%s)", uppercase, classtype)
+ d.warn("class type declared here (%s)", d.classtype)
+ if not self.file.force:
+ return
+
+ assert self.file.original_content
+ for t,tds in typedefs:
+ assert tds
+ for td in tds:
+ if td.file is not self.file:
+ continue
+
+ # delete typedefs that are truly redundant:
+ # 1) defined after DECLARE_OBJ_CHECKERS
+ if td.start() > self.start():
+ yield td.make_removal_patch()
+ # 2) defined before DECLARE_OBJ_CHECKERS, but unused
+ elif not re.search(r'\b'+t+r'\b', self.file.original_content[td.end():self.start()]):
+ yield td.make_removal_patch()
+
+ c = (f'OBJECT_DECLARE_TYPE({instancetype}, {classtype}, {uppercase})\n')
+ yield self.make_patch(c)
+
+class AddObjectDeclareSimpleType(DeclareInstanceChecker):
+ """Will add OBJECT_DECLARE_SIMPLE_TYPE(...) if possible"""
+ def gen_patches(self) -> Iterable[Patch]:
+ uppercase = self.uppercase
+ typename = self.group('typename')
+ instancetype = self.group('instancetype')
+
+ if typename != f'TYPE_{uppercase}':
+ self.warn("type name mismatch: %s vs %s", typename, uppercase)
+ return
+
+ typedefs = [(t,self.allfiles.find_matches(SimpleTypedefMatch, t))
+ for t in (instancetype,)]
+ for t,tds in typedefs:
+ if not tds:
+ self.warn("typedef %s not found", t)
+ return
+ for td in tds:
+ td_type = td.group('typedef_type')
+ if td_type != f'struct {t}':
+ self.warn("typedef mismatch: %s is defined as %s", t, td_type)
+ td.warn("typedef is here")
+ return
+
+ # look for reuse of same struct type
+ other_instance_checkers = [c for c in find_type_checkers(self.allfiles, instancetype, 'instancetype')
+ if c.uppercase != uppercase]
+ if other_instance_checkers:
+ self.warn("typedef %s is being reused", instancetype)
+ for ic in other_instance_checkers:
+ ic.warn("%s is reused here", instancetype)
+ if not self.file.force:
+ return
+
+ decl_types: List[Type[TypeDeclaration]] = [DeclareClassCheckers, DeclareObjCheckers]
+ class_decls = [m for t in decl_types
+ for m in self.allfiles.find_matches(t, uppercase, 'uppercase')]
+ if class_decls:
+ self.warn("class type declared for %s", uppercase)
+ for cd in class_decls:
+ cd.warn("class declaration found here")
+ return
+
+ defs = list(find_type_definitions(self.allfiles, uppercase))
+ if len(defs) > 1:
+ self.warn("multiple definitions for %s", uppercase)
+ for d in defs:
+ d.warn("definition found here")
+ if not self.file.force:
+ return
+ elif len(defs) == 0:
+ self.warn("type definition for %s not found", uppercase)
+ if not self.file.force:
+ return
+ else:
+ d = defs[0]
+ if d.instancetype != instancetype:
+ self.warn("mismatching instance type for %s (%s)", uppercase, instancetype)
+ d.warn("instance type declared here (%s)", d.instancetype)
+ if not self.file.force:
+ return
+ if d.classtype:
+ self.warn("class type set for %s", uppercase)
+ d.warn("class type declared here")
+ if not self.file.force:
+ return
+
+ assert self.file.original_content
+ for t,tds in typedefs:
+ assert tds
+ for td in tds:
+ if td.file is not self.file:
+ continue
+
+ # delete typedefs that are truly redundant:
+ # 1) defined after DECLARE_OBJ_CHECKERS
+ if td.start() > self.start():
+ yield td.make_removal_patch()
+ # 2) defined before DECLARE_OBJ_CHECKERS, but unused
+ elif not re.search(r'\b'+t+r'\b', self.file.original_content[td.end():self.start()]):
+ yield td.make_removal_patch()
+
+ c = (f'OBJECT_DECLARE_SIMPLE_TYPE({instancetype}, {uppercase})\n')
+ yield self.make_patch(c)
+
+
+class TypeInfoStringName(TypeInfoVar):
+ """Replace hardcoded type names with TYPE_ constant"""
+ def gen_patches(self) -> Iterable[Patch]:
+ values = self.initializers
+ if values is None:
+ return
+ if 'name' not in values:
+ self.warn("name not set in TypeInfo variable %s", self.name)
+ return
+ typename = values['name'].raw
+ if re.fullmatch(RE_IDENTIFIER, typename):
+ return
+
+ self.warn("name %s is not an identifier", typename)
+ #all_defines = [m for m in self.allfiles.matches_of_type(ExpressionDefine)]
+ #self.debug("all_defines: %r", all_defines)
+ constants = [m for m in self.allfiles.matches_of_type(ExpressionDefine)
+ if m.group('value').strip() == typename.strip()]
+ if not constants:
+ self.warn("No macro for %s found", typename)
+ return
+ if len(constants) > 1:
+ self.warn("I don't know which macro to use: %r", constants)
+ return
+ yield self.patch_field_value('name', constants[0].name)
class RedundantTypeSizes(TypeInfoVar):
"""Remove redundant instance_size/class_size from TypeInfo vars"""
self.debug("no need to validate %s", self.name)
return
- instance_decl = find_type_declaration(self.allfiles, typename)
- if instance_decl:
+ instance_decls = find_type_checkers(self.allfiles, typename)
+ if instance_decls:
self.debug("won't touch TypeInfo var that has type checkers")
return
self.warn("Can't find TypeInfo for %s", parent_typename)
return
- if 'instance_size' in values and parent.get_initializer_value('instance_size').raw != values['instance_size'].raw:
+ if 'instance_size' in values and parent.get_raw_initializer_value('instance_size') != values['instance_size'].raw:
self.info("instance_size mismatch")
parent.info("parent type declared here")
return
- if 'class_size' in values and parent.get_initializer_value('class_size').raw != values['class_size'].raw:
+ if 'class_size' in values and parent.get_raw_initializer_value('class_size') != values['class_size'].raw:
self.info("class_size mismatch")
parent.info("parent type declared here")
return
# yield self.append_field('class_init', ids.lowercase+'_class_init')
class TypeInitMacro(FileMatch):
- """type_init(...) macro use
- Will be deleted if function is empty
- """
+ """Use of type_init(...) macro"""
regexp = S(r'^[ \t]*type_init\s*\(\s*', NAMED('name', RE_IDENTIFIER), r'\s*\);?[ \t]*\n')
+
+class DeleteEmptyTypeInitFunc(TypeInitMacro):
+ """Delete empty function declared using type_init(...)"""
def gen_patches(self) -> Iterable[Patch]:
fn = self.file.find_match(StaticVoidFunction, self.name)
DBG("function for %s: %s", self.name, fn)
r'#[^\n]*\n',
r'\n',
repeat='*')),
- r'}\n')
+ r'};?\n')
@property
def body(self) -> str:
def has_preprocessor_directive(self) -> bool:
return bool(re.search(r'^[ \t]*#', self.body, re.MULTILINE))
-class TypeRegisterCall(FileMatch):
+def find_containing_func(m: FileMatch) -> Optional['StaticVoidFunction']:
+ """Return function containing this match"""
+ for fn in m.file.matches_of_type(StaticVoidFunction):
+ if fn.contains(m):
+ return fn
+ return None
+
+class TypeRegisterStaticCall(FileMatch):
"""type_register_static() call
Will be replaced by TYPE_INFO() macro
"""
- regexp = S(r'^[ \t]*type_register_static\s*\(&\s*', NAMED('name', RE_IDENTIFIER), r'\s*\);[ \t]*\n')
-
- def function(self) -> Optional['StaticVoidFunction']:
- """Return function containing this call"""
- for m in self.file.matches_of_type(StaticVoidFunction):
- if m.contains(self):
- return m
- return None
+ regexp = S(r'^[ \t]*', NAMED('func_name', 'type_register_static'),
+ r'\s*\(&\s*', NAMED('name', RE_IDENTIFIER), r'\s*\);[ \t]*\n')
+class UseTypeInfo(TypeRegisterStaticCall):
+ """Replace type_register_static() call with TYPE_INFO declaration"""
def gen_patches(self) -> Iterable[Patch]:
- fn = self.function()
- if fn is None:
- self.warn("can't find function where type_register_static(&%s) is called", self.name)
- return
+ fn = find_containing_func(self)
+ if fn:
+ DBG("%r is inside %r", self, fn)
+ type_init = self.file.find_match(TypeInitMacro, fn.name)
+ if type_init is None:
+ self.warn("can't find type_init(%s) line", fn.name)
+ if not self.file.force:
+ return
+ else:
+ self.warn("can't identify the function where type_register_static(&%s) is called", self.name)
+ if not self.file.force:
+ return
#if fn.has_preprocessor_directive() and not self.file.force:
# self.warn("function %s has preprocessor directives, this requires --force", fn.name)
# return
- type_init = self.file.find_match(TypeInitMacro, fn.name)
- if type_init is None:
- self.warn("can't find type_init(%s) line", fn.name)
- return
-
var = self.file.find_match(TypeInfoVar, self.name)
if var is None:
self.warn("can't find TypeInfo var declaration for %s", self.name)
if not var.is_full():
self.warn("variable declaration %s wasn't parsed fully", var.name)
- return
+ if not self.file.force:
+ return
- if fn.contains(var):
+ if fn and fn.contains(var):
self.warn("TypeInfo %s variable is inside a function", self.name)
- return
+ if not self.file.force:
+ return
# delete type_register_static() call:
yield self.make_patch('')
# append TYPE_REGISTER(...) after variable declaration:
yield var.append(f'TYPE_INFO({self.name})\n')
+class TypeRegisterCall(FileMatch):
+ """type_register_static() call"""
+ regexp = S(r'^[ \t]*', NAMED('func_name', 'type_register'),
+ r'\s*\(&\s*', NAMED('name', RE_IDENTIFIER), r'\s*\);[ \t]*\n')
+
+class MakeTypeRegisterStatic(TypeRegisterCall):
+ """Make type_register() call static if variable is static const"""
+ def gen_patches(self):
+ var = self.file.find_match(TypeInfoVar, self.name)
+ if var is None:
+ self.warn("can't find TypeInfo var declaration for %s", self.name)
+ return
+ if var.is_static() and var.is_const():
+ yield self.group_match('func_name').make_patch('type_register_static')
+
+class MakeTypeRegisterNotStatic(TypeRegisterStaticCall):
+ """Make type_register() call static if variable is static const"""
+ def gen_patches(self):
+ var = self.file.find_match(TypeInfoVar, self.name)
+ if var is None:
+ self.warn("can't find TypeInfo var declaration for %s", self.name)
+ return
+ if not var.is_static() or not var.is_const():
+ yield self.group_match('func_name').make_patch('type_register')
+
class TypeInfoMacro(FileMatch):
"""TYPE_INFO macro usage"""
regexp = S(r'^[ \t]*TYPE_INFO\s*\(\s*', NAMED('name', RE_IDENTIFIER), r'\s*\)[ \t]*;?[ \t]*\n')
def find_type_info(files: RegexpScanner, name: str) -> Optional[TypeInfoVar]:
ti = [ti for ti in files.matches_of_type(TypeInfoVar)
- if ti.get_initializer_value('name').raw == name]
+ if ti.get_raw_initializer_value('name') == name]
DBG("type info vars: %r", ti)
if len(ti) > 1:
DBG("multiple TypeInfo vars found for %s", name)
files = FileList()
f = FileInfo(files, of.name)
f.load()
- f.scan_for_matches()
matches = f.matches_of_type(BasicPattern)
assert len(matches) == 2
p2 = matches[1]
f.patches.append(p2.append('XXX'))
# apply all patches:
- f.gen_patches()
+ f.gen_patches(matches)
patched = f.get_patched_content()
assert patched == ('one line\n'+
'this pattern will be patched: defBBBBBhij\n'+
from .qom_macros import *
from .qom_type_info import *
-def test_res():
+def test_res() -> None:
def fullmatch(regexp, s):
return re.fullmatch(regexp, s, re.MULTILINE)
* need to set up reset or vmstate, and has no realize method.
*/''')
- print(RE_TYPEINFO_DEF)
+ print(TypeInfoVar.regexp)
test_empty = 'static const TypeInfo x86_base_cpu_type_info = {\n'+\
'};\n';
- assert fullmatch(RE_TYPEINFO_DEF, test_empty)
+ assert fullmatch(TypeInfoVar.regexp, test_empty)
test_simple = r'''
static const TypeInfo x86_base_cpu_type_info = {
.class_init = x86_cpu_base_class_init,
};
'''
- assert re.search(RE_TYPEINFO_DEF, test_simple, re.MULTILINE)
+ assert re.search(TypeInfoVar.regexp, test_simple, re.MULTILINE)
test_interfaces = r'''
static const TypeInfo acpi_ged_info = {
}
};
'''
- assert re.search(RE_TYPEINFO_DEF, test_interfaces, re.MULTILINE)
+ assert re.search(TypeInfoVar.regexp, test_interfaces, re.MULTILINE)
test_comments = r'''
static const TypeInfo palm_misc_gpio_info = {
*/
};
'''
- assert re.search(RE_TYPEINFO_DEF, test_comments, re.MULTILINE)
+ assert re.search(TypeInfoVar.regexp, test_comments, re.MULTILINE)
test_comments = r'''
static const TypeInfo tpm_crb_info = {
}
};
'''
- assert re.search(RE_TYPEINFO_DEF, test_comments, re.MULTILINE)
+ assert re.search(TypeInfoVar.regexp, test_comments, re.MULTILINE)
def test_struct_re():
print('---')
/* pflash_cfi01.c */
'''
- print(repr(list(m.groupdict() for m in re.finditer(InitialIncludes.regexp, c, re.MULTILINE))))
- m = re.match(InitialIncludes.regexp, c, re.MULTILINE)
+ print(repr(list(m.groupdict() for m in InitialIncludes.finditer(c))))
+ m = InitialIncludes.domatch(c)
assert m
print(repr(m.group(0)))
assert m.group(0).endswith('#include "exec/hwaddr.h"\n')
'''
- print(repr(list(m.groupdict() for m in re.finditer(InitialIncludes.regexp, c, re.MULTILINE))))
- m = re.match(InitialIncludes.regexp, c, re.MULTILINE)
+ print(repr(list(m.groupdict() for m in InitialIncludes.finditer(c))))
+ m = InitialIncludes.domatch(c)
assert m
print(repr(m.group(0)))
assert m.group(0).endswith('#include "9p.h"\n')
/* Missing stuff:
SCTRL_P[12](END|ST)INC
'''
- print(repr(list(m.groupdict() for m in re.finditer(InitialIncludes.regexp, c, re.MULTILINE))))
- m = re.match(InitialIncludes.regexp, c, re.MULTILINE)
+ print(repr(list(m.groupdict() for m in InitialIncludes.finditer(c))))
+ m = InitialIncludes.domatch(c)
assert m
print(repr(m.group(0)))
assert m.group(0).endswith('#include "sysemu/dma.h"\n')
for t in f.matches_of_type(TypeInfoVar):
assert isinstance(t, TypeInfoVar)
values = [f.filename, t.name] + \
- [t.get_initializer_value(f).raw
+ [t.get_raw_initializer_value(f)
for f in TI_FIELDS]
DBG('values: %r', values)
assert all('\t' not in v for v in values)
parser.error("--pattern is required")
classes = [p for arg in args.patterns
- for p in re.split(r'[\s,]', arg)]
+ for p in re.split(r'[\s,]', arg)
+ if p.strip()]
for c in classes:
- if c not in match_classes:
+ if c not in match_classes \
+ or not match_classes[c].regexp:
print("Invalid pattern name: %s" % (c), file=sys.stderr)
print("Valid patterns:", file=sys.stderr)
print(PATTERN_HELP, file=sys.stderr)
sys.exit(1)
DBG("classes: %r", classes)
- for f in files:
- DBG("patching contents of %s", f.filename)
- f.patch_content(max_passes=args.passes, class_names=classes)
+ files.patch_content(max_passes=args.passes, class_names=classes)
for f in files:
#alltypes.extend(f.type_infos)
def str_fields(fields):
- """Return a string uniquely identifing FIELDS"""
+ """Return a string uniquely identifying FIELDS"""
r = ''
for n in sorted(fields.keys()):
r += '_' + n
arg = None
fmt = None
for t in toks:
- # '&Foo' gives a format an explcit argument set.
+ # '&Foo' gives a format an explicit argument set.
if re.fullmatch(re_arg_ident, t):
tt = t[1:]
if arg:
elif not (is_format and width == 0) and width != insnwidth:
error(lineno, 'definition has {0} bits'.format(width))
- # Do not check for fields overlaping fields; one valid usage
+ # Do not check for fields overlapping fields; one valid usage
# is to be able to duplicate fields via import.
fieldmask = 0
for f in flds.values():
configure
Makefile*
*.mak
+meson.build
# qapi schema
qapi/*.json
if ! make "-j$(nproc)" qemu-fuzz-i386; then
fatal "Build failed. Please specify a compiler with fuzzing support"\
- "using the \$CC and \$CXX environemnt variables"\
+ "using the \$CC and \$CXX environment variables"\
"\nFor example: CC=clang CXX=clang++ $0"
fi
--- /dev/null
+#!/usr/bin/env python3
+#
+# Test to compare performance of write requests for two qemu-img binary files.
+#
+# The idea of the test comes from intention to check the benefit of c8bb23cbdbe
+# "qcow2: skip writing zero buffers to empty COW areas".
+#
+# Copyright (c) 2020 Virtuozzo International GmbH.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+
+import sys
+import os
+import subprocess
+import simplebench
+
+
+def bench_func(env, case):
+ """ Handle one "cell" of benchmarking table. """
+ return bench_write_req(env['qemu_img'], env['image_name'],
+ case['block_size'], case['block_offset'],
+ case['cluster_size'])
+
+
+def qemu_img_pipe(*args):
+ '''Run qemu-img and return its output'''
+ subp = subprocess.Popen(list(args),
+ stdout=subprocess.PIPE,
+ stderr=subprocess.STDOUT,
+ universal_newlines=True)
+ exitcode = subp.wait()
+ if exitcode < 0:
+ sys.stderr.write('qemu-img received signal %i: %s\n'
+ % (-exitcode, ' '.join(list(args))))
+ return subp.communicate()[0]
+
+
+def bench_write_req(qemu_img, image_name, block_size, block_offset,
+ cluster_size):
+ """Benchmark write requests
+
+ The function creates a QCOW2 image with the given path/name. Then it runs
+ the 'qemu-img bench' command and makes series of write requests on the
+ image clusters. Finally, it returns the total time of the write operations
+ on the disk.
+
+ qemu_img -- path to qemu_img executable file
+ image_name -- QCOW2 image name to create
+ block_size -- size of a block to write to clusters
+ block_offset -- offset of the block in clusters
+ cluster_size -- size of the image cluster
+
+ Returns {'seconds': int} on success and {'error': str} on failure.
+ Return value is compatible with simplebench lib.
+ """
+
+ if not os.path.isfile(qemu_img):
+ print(f'File not found: {qemu_img}')
+ sys.exit(1)
+
+ image_dir = os.path.dirname(os.path.abspath(image_name))
+ if not os.path.isdir(image_dir):
+ print(f'Path not found: {image_name}')
+ sys.exit(1)
+
+ image_size = 1024 * 1024 * 1024
+
+ args_create = [qemu_img, 'create', '-f', 'qcow2', '-o',
+ f'cluster_size={cluster_size}',
+ image_name, str(image_size)]
+
+ count = int(image_size / cluster_size) - 1
+ step = str(cluster_size)
+
+ args_bench = [qemu_img, 'bench', '-w', '-n', '-t', 'none', '-c',
+ str(count), '-s', f'{block_size}', '-o', str(block_offset),
+ '-S', step, '-f', 'qcow2', image_name]
+
+ try:
+ qemu_img_pipe(*args_create)
+ except OSError as e:
+ os.remove(image_name)
+ return {'error': 'qemu_img create failed: ' + str(e)}
+
+ try:
+ ret = qemu_img_pipe(*args_bench)
+ except OSError as e:
+ os.remove(image_name)
+ return {'error': 'qemu_img bench failed: ' + str(e)}
+
+ os.remove(image_name)
+
+ if 'seconds' in ret:
+ ret_list = ret.split()
+ index = ret_list.index('seconds.')
+ return {'seconds': float(ret_list[index-1])}
+ else:
+ return {'error': 'qemu_img bench failed: ' + ret}
+
+
+if __name__ == '__main__':
+
+ if len(sys.argv) < 4:
+ program = os.path.basename(sys.argv[0])
+ print(f'USAGE: {program} <path to qemu-img binary file> '
+ '<path to another qemu-img to compare performance with> '
+ '<full or relative name for QCOW2 image to create>')
+ exit(1)
+
+ # Test-cases are "rows" in benchmark resulting table, 'id' is a caption
+ # for the row, other fields are handled by bench_func.
+ test_cases = [
+ {
+ 'id': '<cluster front>',
+ 'block_size': 4096,
+ 'block_offset': 0,
+ 'cluster_size': 1048576
+ },
+ {
+ 'id': '<cluster middle>',
+ 'block_size': 4096,
+ 'block_offset': 524288,
+ 'cluster_size': 1048576
+ },
+ {
+ 'id': '<cross cluster>',
+ 'block_size': 1048576,
+ 'block_offset': 4096,
+ 'cluster_size': 1048576
+ },
+ {
+ 'id': '<cluster 64K>',
+ 'block_size': 4096,
+ 'block_offset': 0,
+ 'cluster_size': 65536
+ },
+ ]
+
+ # Test-envs are "columns" in benchmark resulting table, 'id is a caption
+ # for the column, other fields are handled by bench_func.
+ # Set the paths below to desired values
+ test_envs = [
+ {
+ 'id': '<qemu-img binary 1>',
+ 'qemu_img': f'{sys.argv[1]}',
+ 'image_name': f'{sys.argv[3]}'
+ },
+ {
+ 'id': '<qemu-img binary 2>',
+ 'qemu_img': f'{sys.argv[2]}',
+ 'image_name': f'{sys.argv[3]}'
+ },
+ ]
+
+ result = simplebench.bench(bench_func, test_envs, test_cases, count=3,
+ initial_run=False)
+ print(simplebench.ascii(result))
def out(*lines, **kwargs):
"""Write a set of output lines.
- You can use kwargs as a shorthand for mapping variables when formating all
+ You can use kwargs as a shorthand for mapping variables when formatting all
the strings in lines.
"""
lines = [ l % kwargs for l in lines ]
#define TYPE_PR_MANAGER_HELPER "pr-manager-helper"
-typedef struct PRManagerHelper PRManagerHelper;
-DECLARE_INSTANCE_CHECKER(PRManagerHelper, PR_MANAGER_HELPER,
- TYPE_PR_MANAGER_HELPER)
+OBJECT_DECLARE_SIMPLE_TYPE(PRManagerHelper, PR_MANAGER_HELPER)
struct PRManagerHelper {
/* <private> */
qio_channel_set_delay(QIO_CHANNEL(sioc), false);
pr_mgr->ioc = QIO_CHANNEL(sioc);
- /* A simple feature negotation protocol, even though there is
+ /* A simple feature negotiation protocol, even though there is
* no optional feature right now.
*/
r = pr_manager_helper_read(pr_mgr, &flags, sizeof(flags), errp);
#define TYPE_ALPHA_CPU "alpha-cpu"
OBJECT_DECLARE_TYPE(AlphaCPU, AlphaCPUClass,
- alpha_cpu, ALPHA_CPU)
+ ALPHA_CPU)
/**
* AlphaCPUClass:
#define TYPE_ARM_CPU "arm-cpu"
OBJECT_DECLARE_TYPE(ARMCPU, ARMCPUClass,
- arm_cpu, ARM_CPU)
+ ARM_CPU)
#define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU
TypeInfo type_info = {
.parent = TYPE_ARM_CPU,
.instance_size = sizeof(ARMCPU),
+ .instance_align = __alignof__(ARMCPU),
.instance_init = arm_cpu_instance_init,
.class_size = sizeof(ARMCPUClass),
.class_init = info->class_init ?: cpu_register_class_init,
.name = TYPE_ARM_CPU,
.parent = TYPE_CPU,
.instance_size = sizeof(ARMCPU),
+ .instance_align = __alignof__(ARMCPU),
.instance_init = arm_cpu_initfn,
.instance_finalize = arm_cpu_finalizefn,
.abstract = true,
#define TYPE_AVR_CPU "avr-cpu"
OBJECT_DECLARE_TYPE(AVRCPU, AVRCPUClass,
- avr_cpu, AVR_CPU)
+ AVR_CPU)
/**
* AVRCPUClass:
#define TYPE_CRIS_CPU "cris-cpu"
OBJECT_DECLARE_TYPE(CRISCPU, CRISCPUClass,
- cris_cpu, CRIS_CPU)
+ CRIS_CPU)
/**
* CRISCPUClass:
#define TYPE_HPPA_CPU "hppa-cpu"
OBJECT_DECLARE_TYPE(HPPACPU, HPPACPUClass,
- hppa_cpu, HPPA_CPU)
+ HPPA_CPU)
/**
* HPPACPUClass:
#endif
OBJECT_DECLARE_TYPE(X86CPU, X86CPUClass,
- x86_cpu, X86_CPU)
+ X86_CPU)
typedef struct X86CPUModel X86CPUModel;
}
}
-/*
- * Definitions used for building CPUID Leaf 0x8000001D and 0x8000001E
- * Please refer to the AMD64 Architecture Programmer’s Manual Volume 3.
- * Define the constants to build the cpu topology. Right now, TOPOEXT
- * feature is enabled only on EPYC. So, these constants are based on
- * EPYC supported configurations. We may need to handle the cases if
- * these values change in future.
- */
-/* Maximum core complexes in a node */
-#define MAX_CCX 2
-/* Maximum cores in a core complex */
-#define MAX_CORES_IN_CCX 4
-/* Maximum cores in a node */
-#define MAX_CORES_IN_NODE 8
-/* Maximum nodes in a socket */
-#define MAX_NODES_PER_SOCKET 4
-
-/*
- * Figure out the number of nodes required to build this config.
- * Max cores in a node is 8
- */
-static int nodes_in_socket(int nr_cores)
-{
- int nodes;
-
- nodes = DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE);
-
- /* Hardware does not support config with 3 nodes, return 4 in that case */
- return (nodes == 3) ? 4 : nodes;
-}
-
-/*
- * Decide the number of cores in a core complex with the given nr_cores using
- * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and
- * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible
- * L3 cache is shared across all cores in a core complex. So, this will also
- * tell us how many cores are sharing the L3 cache.
- */
-static int cores_in_core_complex(int nr_cores)
-{
- int nodes;
-
- /* Check if we can fit all the cores in one core complex */
- if (nr_cores <= MAX_CORES_IN_CCX) {
- return nr_cores;
- }
- /* Get the number of nodes required to build this config */
- nodes = nodes_in_socket(nr_cores);
-
- /*
- * Divide the cores accros all the core complexes
- * Return rounded up value
- */
- return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX);
-}
-
/* Encode cache info for CPUID[8000001D] */
-static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs,
- uint32_t *eax, uint32_t *ebx,
- uint32_t *ecx, uint32_t *edx)
+static void encode_cache_cpuid8000001d(CPUCacheInfo *cache,
+ X86CPUTopoInfo *topo_info,
+ uint32_t *eax, uint32_t *ebx,
+ uint32_t *ecx, uint32_t *edx)
{
- uint32_t l3_cores;
+ uint32_t l3_threads;
assert(cache->size == cache->line_size * cache->associativity *
cache->partitions * cache->sets);
/* L3 is shared among multiple cores */
if (cache->level == 3) {
- l3_cores = cores_in_core_complex(cs->nr_cores);
- *eax |= ((l3_cores * cs->nr_threads) - 1) << 14;
+ l3_threads = topo_info->cores_per_die * topo_info->threads_per_core;
+ *eax |= (l3_threads - 1) << 14;
} else {
- *eax |= ((cs->nr_threads - 1) << 14);
+ *eax |= ((topo_info->threads_per_core - 1) << 14);
}
assert(cache->line_size > 0);
(cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
}
-/* Data structure to hold the configuration info for a given core index */
-struct core_topology {
- /* core complex id of the current core index */
- int ccx_id;
- /*
- * Adjusted core index for this core in the topology
- * This can be 0,1,2,3 with max 4 cores in a core complex
- */
- int core_id;
- /* Node id for this core index */
- int node_id;
- /* Number of nodes in this config */
- int num_nodes;
-};
-
-/*
- * Build the configuration closely match the EPYC hardware. Using the EPYC
- * hardware configuration values (MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE)
- * right now. This could change in future.
- * nr_cores : Total number of cores in the config
- * core_id : Core index of the current CPU
- * topo : Data structure to hold all the config info for this core index
- */
-static void build_core_topology(int nr_cores, int core_id,
- struct core_topology *topo)
-{
- int nodes, cores_in_ccx;
-
- /* First get the number of nodes required */
- nodes = nodes_in_socket(nr_cores);
-
- cores_in_ccx = cores_in_core_complex(nr_cores);
-
- topo->node_id = core_id / (cores_in_ccx * MAX_CCX);
- topo->ccx_id = (core_id % (cores_in_ccx * MAX_CCX)) / cores_in_ccx;
- topo->core_id = core_id % cores_in_ccx;
- topo->num_nodes = nodes;
-}
-
/* Encode cache info for CPUID[8000001E] */
-static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu,
- uint32_t *eax, uint32_t *ebx,
- uint32_t *ecx, uint32_t *edx)
+static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info,
+ uint32_t *eax, uint32_t *ebx,
+ uint32_t *ecx, uint32_t *edx)
{
- struct core_topology topo = {0};
- unsigned long nodes;
- int shift;
+ X86CPUTopoIDs topo_ids;
+
+ x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids);
- build_core_topology(cs->nr_cores, cpu->core_id, &topo);
*eax = cpu->apic_id;
+
/*
- * CPUID_Fn8000001E_EBX
- * 31:16 Reserved
- * 15:8 Threads per core (The number of threads per core is
- * Threads per core + 1)
- * 7:0 Core id (see bit decoding below)
- * SMT:
- * 4:3 node id
- * 2 Core complex id
- * 1:0 Core id
- * Non SMT:
- * 5:4 node id
- * 3 Core complex id
- * 1:0 Core id
+ * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId)
+ * Read-only. Reset: 0000_XXXXh.
+ * See Core::X86::Cpuid::ExtApicId.
+ * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0];
+ * Bits Description
+ * 31:16 Reserved.
+ * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh.
+ * The number of threads per core is ThreadsPerCore+1.
+ * 7:0 CoreId: core ID. Read-only. Reset: XXh.
+ *
+ * NOTE: CoreId is already part of apic_id. Just use it. We can
+ * use all the 8 bits to represent the core_id here.
*/
- if (cs->nr_threads - 1) {
- *ebx = ((cs->nr_threads - 1) << 8) | (topo.node_id << 3) |
- (topo.ccx_id << 2) | topo.core_id;
- } else {
- *ebx = (topo.node_id << 4) | (topo.ccx_id << 3) | topo.core_id;
- }
+ *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF);
+
/*
- * CPUID_Fn8000001E_ECX
- * 31:11 Reserved
- * 10:8 Nodes per processor (Nodes per processor is number of nodes + 1)
- * 7:0 Node id (see bit decoding below)
- * 2 Socket id
- * 1:0 Node id
+ * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId)
+ * Read-only. Reset: 0000_0XXXh.
+ * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0];
+ * Bits Description
+ * 31:11 Reserved.
+ * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb.
+ * ValidValues:
+ * Value Description
+ * 000b 1 node per processor.
+ * 001b 2 nodes per processor.
+ * 010b Reserved.
+ * 011b 4 nodes per processor.
+ * 111b-100b Reserved.
+ * 7:0 NodeId: Node ID. Read-only. Reset: XXh.
+ *
+ * NOTE: Hardware reserves 3 bits for number of nodes per processor.
+ * But users can create more nodes than the actual hardware can
+ * support. To genaralize we can use all the upper 8 bits for nodes.
+ * NodeId is combination of node and socket_id which is already decoded
+ * in apic_id. Just use it by shifting.
*/
- if (topo.num_nodes <= 4) {
- *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << 2) |
- topo.node_id;
- } else {
- /*
- * Node id fix up. Actual hardware supports up to 4 nodes. But with
- * more than 32 cores, we may end up with more than 4 nodes.
- * Node id is a combination of socket id and node id. Only requirement
- * here is that this number should be unique accross the system.
- * Shift the socket id to accommodate more nodes. We dont expect both
- * socket id and node id to be big number at the same time. This is not
- * an ideal config but we need to to support it. Max nodes we can have
- * is 32 (255/8) with 8 cores per node and 255 max cores. We only need
- * 5 bits for nodes. Find the left most set bit to represent the total
- * number of nodes. find_last_bit returns last set bit(0 based). Left
- * shift(+1) the socket id to represent all the nodes.
- */
- nodes = topo.num_nodes - 1;
- shift = find_last_bit(&nodes, 8);
- *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << (shift + 1)) |
- topo.node_id;
- }
+ *ecx = ((topo_info->dies_per_pkg - 1) << 8) |
+ ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF);
+
*edx = 0;
}
}
switch (count) {
case 0: /* L1 dcache info */
- encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, cs,
- eax, ebx, ecx, edx);
+ encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache,
+ &topo_info, eax, ebx, ecx, edx);
break;
case 1: /* L1 icache info */
- encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, cs,
- eax, ebx, ecx, edx);
+ encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache,
+ &topo_info, eax, ebx, ecx, edx);
break;
case 2: /* L2 cache info */
- encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, cs,
- eax, ebx, ecx, edx);
+ encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache,
+ &topo_info, eax, ebx, ecx, edx);
break;
case 3: /* L3 cache info */
- encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, cs,
- eax, ebx, ecx, edx);
+ encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache,
+ &topo_info, eax, ebx, ecx, edx);
break;
default: /* end of info */
*eax = *ebx = *ecx = *edx = 0;
break;
case 0x8000001E:
assert(cpu->core_id <= 255);
- encode_topo_cpuid8000001e(cs, cpu,
+ encode_topo_cpuid8000001e(cpu, &topo_info,
eax, ebx, ecx, edx);
break;
case 0xC0000000:
DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts,
- HYPERV_SPINLOCK_NEVER_RETRY),
+ HYPERV_SPINLOCK_NEVER_NOTIFY),
DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features,
HYPERV_FEAT_RELAXED, 0),
DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features,
#define HYPERV_FEAT_IPI 13
#define HYPERV_FEAT_STIMER_DIRECT 14
-#ifndef HYPERV_SPINLOCK_NEVER_RETRY
-#define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF
+#ifndef HYPERV_SPINLOCK_NEVER_NOTIFY
+#define HYPERV_SPINLOCK_NEVER_NOTIFY 0xFFFFFFFF
#endif
#define EXCP00_DIVZ 0
{
CPUState *cs = CPU(cpu);
return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
- ((cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY) ||
+ ((cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_NOTIFY) ||
cpu->hyperv_features || cpu->hyperv_passthrough);
}
env->features[FEAT_HV_RECOMM_EAX] = c->eax;
/* hv-spinlocks may have been overriden */
- if (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY) {
+ if (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_NOTIFY) {
c->ebx = cpu->hyperv_spinlock_attempts;
}
}
#include "qom/object.h"
#define TYPE_SEV_GUEST "sev-guest"
-typedef struct SevGuestState SevGuestState;
-DECLARE_INSTANCE_CHECKER(SevGuestState, SEV_GUEST,
- TYPE_SEV_GUEST)
+OBJECT_DECLARE_SIMPLE_TYPE(SevGuestState, SEV_GUEST)
/**
#define TYPE_LM32_CPU "lm32-cpu"
OBJECT_DECLARE_TYPE(LM32CPU, LM32CPUClass,
- lm32_cpu, LM32_CPU)
+ LM32_CPU)
/**
* LM32CPUClass:
#define TYPE_M68K_CPU "m68k-cpu"
OBJECT_DECLARE_TYPE(M68kCPU, M68kCPUClass,
- m68k_cpu, M68K_CPU)
+ M68K_CPU)
/*
* M68kCPUClass:
#define TYPE_MICROBLAZE_CPU "microblaze-cpu"
OBJECT_DECLARE_TYPE(MicroBlazeCPU, MicroBlazeCPUClass,
- microblaze_cpu, MICROBLAZE_CPU)
+ MICROBLAZE_CPU)
/**
* MicroBlazeCPUClass:
#endif
OBJECT_DECLARE_TYPE(MIPSCPU, MIPSCPUClass,
- mips_cpu, MIPS_CPU)
+ MIPS_CPU)
/**
* MIPSCPUClass:
#define TYPE_MOXIE_CPU "moxie-cpu"
OBJECT_DECLARE_TYPE(MoxieCPU, MoxieCPUClass,
- moxie_cpu, MOXIE_CPU)
+ MOXIE_CPU)
/**
* MoxieCPUClass:
#define TYPE_NIOS2_CPU "nios2-cpu"
OBJECT_DECLARE_TYPE(Nios2CPU, Nios2CPUClass,
- nios2_cpu, NIOS2_CPU)
+ NIOS2_CPU)
/**
* Nios2CPUClass:
#define TYPE_OPENRISC_CPU "or1k-cpu"
OBJECT_DECLARE_TYPE(OpenRISCCPU, OpenRISCCPUClass,
- openrisc_cpu, OPENRISC_CPU)
+ OPENRISC_CPU)
/**
* OpenRISCCPUClass:
#endif
OBJECT_DECLARE_TYPE(PowerPCCPU, PowerPCCPUClass,
- powerpc_cpu, POWERPC_CPU)
+ POWERPC_CPU)
typedef struct CPUPPCState CPUPPCState;
typedef struct ppc_tb_t ppc_tb_t;
.name = TYPE_POWERPC_CPU,
.parent = TYPE_CPU,
.instance_size = sizeof(PowerPCCPU),
+ .instance_align = __alignof__(PowerPCCPU),
.instance_init = ppc_cpu_instance_init,
.instance_finalize = ppc_cpu_instance_finalize,
.abstract = true,
.name = TYPE_RISCV_CPU,
.parent = TYPE_CPU,
.instance_size = sizeof(RISCVCPU),
+ .instance_align = __alignof__(RISCVCPU),
.instance_init = riscv_cpu_init,
.abstract = true,
.class_size = sizeof(RISCVCPUClass),
};
OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass,
- riscv_cpu, RISCV_CPU)
+ RISCV_CPU)
/**
* RISCVCPUClass:
#define TYPE_RX62N_CPU RX_CPU_TYPE_NAME("rx62n")
OBJECT_DECLARE_TYPE(RXCPU, RXCPUClass,
- rx_cpu, RX_CPU)
+ RX_CPU)
/*
* RXCPUClass:
#define TYPE_S390_CPU "s390x-cpu"
OBJECT_DECLARE_TYPE(S390CPU, S390CPUClass,
- s390_cpu, S390_CPU)
+ S390_CPU)
typedef struct S390CPUModel S390CPUModel;
typedef struct S390CPUDef S390CPUDef;
.name = TYPE_S390_CPU,
.parent = TYPE_CPU,
.instance_size = sizeof(S390CPU),
+ .instance_align = __alignof__(S390CPU),
.instance_init = s390_cpu_initfn,
.instance_finalize = s390_cpu_finalize,
.abstract = true,
#define TYPE_SH7785_CPU SUPERH_CPU_TYPE_NAME("sh7785")
OBJECT_DECLARE_TYPE(SuperHCPU, SuperHCPUClass,
- superh_cpu, SUPERH_CPU)
+ SUPERH_CPU)
/**
* SuperHCPUClass:
#endif
OBJECT_DECLARE_TYPE(SPARCCPU, SPARCCPUClass,
- sparc_cpu, SPARC_CPU)
+ SPARC_CPU)
typedef struct sparc_def_t sparc_def_t;
/**
#define TYPE_TILEGX_CPU "tilegx-cpu"
OBJECT_DECLARE_TYPE(TileGXCPU, TileGXCPUClass,
- tilegx_cpu, TILEGX_CPU)
+ TILEGX_CPU)
/**
* TileGXCPUClass:
#define TYPE_TRICORE_CPU "tricore-cpu"
OBJECT_DECLARE_TYPE(TriCoreCPU, TriCoreCPUClass,
- tricore_cpu, TRICORE_CPU)
+ TRICORE_CPU)
struct TriCoreCPUClass {
/*< private >*/
#define TYPE_UNICORE32_CPU "unicore32-cpu"
OBJECT_DECLARE_TYPE(UniCore32CPU, UniCore32CPUClass,
- unicore32_cpu, UNICORE32_CPU)
+ UNICORE32_CPU)
/**
* UniCore32CPUClass:
#define TYPE_XTENSA_CPU "xtensa-cpu"
OBJECT_DECLARE_TYPE(XtensaCPU, XtensaCPUClass,
- xtensa_cpu, XTENSA_CPU)
+ XTENSA_CPU)
typedef struct XtensaConfig XtensaConfig;
self.wait_for_console_pattern('Boot successful.')
# TODO user command, for now the uart is stuck
+ @skipUnless(os.getenv('ARMBIAN_ARTIFACTS_CACHED'),
+ 'Test artifacts fetched from unreliable apt.armbian.com')
def test_arm_cubieboard_initrd(self):
"""
:avocado: tags=arch:arm
'system-control@1c00000')
# cubieboard's reboot is not functioning; omit reboot test.
+ @skipUnless(os.getenv('ARMBIAN_ARTIFACTS_CACHED'),
+ 'Test artifacts fetched from unreliable apt.armbian.com')
def test_arm_cubieboard_sata(self):
"""
:avocado: tags=arch:arm
'sda')
# cubieboard's reboot is not functioning; omit reboot test.
+ @skipUnless(os.getenv('AVOCADO_TIMEOUT_EXPECTED'), 'Test might timeout')
def test_arm_quanta_gsj(self):
"""
:avocado: tags=arch:arm
self.wait_for_console_pattern(
'Give root password for system maintenance')
+ @skipUnless(os.getenv('ARMBIAN_ARTIFACTS_CACHED'),
+ 'Test artifacts fetched from unreliable apt.armbian.com')
def test_arm_orangepi(self):
"""
:avocado: tags=arch:arm
console_pattern = 'Kernel command line: %s' % kernel_command_line
self.wait_for_console_pattern(console_pattern)
+ @skipUnless(os.getenv('ARMBIAN_ARTIFACTS_CACHED'),
+ 'Test artifacts fetched from unreliable apt.armbian.com')
def test_arm_orangepi_initrd(self):
"""
:avocado: tags=arch:arm
# Wait for VM to shut down gracefully
self.vm.wait()
+ @skipUnless(os.getenv('ARMBIAN_ARTIFACTS_CACHED'),
+ 'Test artifacts fetched from unreliable apt.armbian.com')
def test_arm_orangepi_sd(self):
"""
:avocado: tags=arch:arm
import time
from avocado import skipIf
+from avocado import skipUnless
from avocado_qemu import wait_for_console_pattern
from avocado.utils import archive
from avocado.utils import process
self.run_rr(kernel_path, kernel_command_line, console_pattern, shift=1)
@skipIf(os.getenv('GITLAB_CI'), 'Running on GitLab')
+ @skipUnless(os.getenv('ARMBIAN_ARTIFACTS_CACHED'),
+ 'Test artifacts fetched from unreliable apt.armbian.com')
def test_arm_cubieboard_initrd(self):
"""
:avocado: tags=arch:arm
"av",
"BadAnimal",
&err);
+ g_assert(val == -1);
error_free_or_abort(&err);
/* A non-enum property name */
"iv",
"DummyAnimal",
&err);
+ g_assert(val == -1);
error_free_or_abort(&err);
object_unparent(OBJECT(dobj));
#include "input-barrier.h"
#define TYPE_INPUT_BARRIER "input-barrier"
-OBJECT_DECLARE_SIMPLE_TYPE(InputBarrier, input_barrier,
- INPUT_BARRIER, ObjectClass)
+OBJECT_DECLARE_SIMPLE_TYPE(InputBarrier,
+ INPUT_BARRIER)
#define MAX_HELLO_LENGTH 1024
static const TypeInfo input_barrier_info = {
.name = TYPE_INPUT_BARRIER,
.parent = TYPE_OBJECT,
- .class_size = sizeof(InputBarrierClass),
.class_init = input_barrier_class_init,
.instance_size = sizeof(InputBarrier),
.instance_init = input_barrier_instance_init,
}
#define TYPE_INPUT_LINUX "input-linux"
-OBJECT_DECLARE_SIMPLE_TYPE(InputLinux, input_linux,
- INPUT_LINUX, ObjectClass)
+OBJECT_DECLARE_SIMPLE_TYPE(InputLinux,
+ INPUT_LINUX)
struct InputLinux {
static const TypeInfo input_linux_info = {
.name = TYPE_INPUT_LINUX,
.parent = TYPE_OBJECT,
- .class_size = sizeof(InputLinuxClass),
.class_init = input_linux_class_init,
.instance_size = sizeof(InputLinux),
.instance_init = input_linux_instance_init,
static void kbd_push_key(SpiceKbdInstance *sin, uint8_t frag);
static uint8_t kbd_get_leds(SpiceKbdInstance *sin);
-static void kbd_leds(void *opaque, int l);
static const SpiceKbdInterface kbd_interface = {
.base.type = SPICE_INTERFACE_KEYBOARD,
* Set errno if fewer than `count' bytes are written.
*
* This function don't work with non-blocking fd's.
- * Any of the possibilities with non-bloking fd's is bad:
+ * Any of the possibilities with non-blocking fd's is bad:
* - return a short write (then name is wrong)
* - busy wait adding (errno == EAGAIN) to the loop
*/
/*
* Report progress.
* @delta is how much progress we made.
- * If @max is zero, @delta is an absolut value of the total job done.
+ * If @max is zero, @delta is an absolute value of the total job done.
* Else, @delta is a progress delta since the last call, as a fraction
* of @max. I.e. the delta is @delta * @max / 100. This allows
* relative accounting of functions which may be a different fraction of
/* At least FreeBSD and OS-X 10.6 declare AI_V4MAPPED but
* then don't implement it in their getaddrinfo(). Detect
- * this and retry without the flag since that's preferrable
+ * this and retry without the flag since that's preferable
* to a fatal error
*/
if (rc == EAI_BADFLAGS &&
ResetEvent(ev->event);
/* Tell qemu_event_set that there are waiters. No need to retry
- * because there cannot be a concurent busy->free transition.
+ * because there cannot be a concurrent busy->free transition.
* After the CAS, the event will be either set or busy.
*/
if (atomic_cmpxchg(&ev->value, EV_FREE, EV_BUSY) == EV_SET) {
* it anymore.
*
* Writers check for concurrent resizes by comparing ht->map before and after
- * acquiring their bucket lock. If they don't match, a resize has occured
+ * acquiring their bucket lock. If they don't match, a resize has occurred
* while the bucket spinlock was being acquired.
*
* Related Work:
qemu_file_monitor_remove_watch(void *mon, const char *dirpath, int64_t id) "File monitor %p remove watch dir='%s' id=%" PRId64
qemu_file_monitor_new(void *mon, int fd) "File monitor %p created fd=%d"
qemu_file_monitor_enable_watch(void *mon, const char *dirpath, int id) "File monitor %p enable watch dir='%s' id=%u"
-qemu_file_monitor_disable_watch(void *mon, const char *dirpath, int id) "Fle monitor %p disable watch dir='%s' id=%u"
+qemu_file_monitor_disable_watch(void *mon, const char *dirpath, int id) "File monitor %p disable watch dir='%s' id=%u"
qemu_file_monitor_event(void *mon, const char *dirpath, const char *filename, int mask, unsigned int id) "File monitor %p event dir='%s' file='%s' mask=0x%x id=%u"
qemu_file_monitor_dispatch(void *mon, const char *dirpath, const char *filename, int ev, void *cb, void *opaque, int64_t id) "File monitor %p dispatch dir='%s' file='%s' ev=%d cb=%p opaque=%p id=%" PRId64
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