bus: ti-sysc: Enable interconnect target module autoidle bit on enable

For interconnect target modules with autoidle bit wired, we need to manage
it for enable and disable.

Tested-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c
index 412973829adcd380859a29e6342821b1860b1506..46a8eb469cb2e0d905148dd06f9a35e7306d4148 100644 (file)
--- a/drivers/bus/ti-sysc.c
+++ b/drivers/bus/ti-sysc.c
@@ -893,7 +893,7 @@ set_midle:
        /* Set MIDLE mode */
        idlemodes = ddata->cfg.midlemodes;
        if (!idlemodes || regbits->midle_shift < 0)
-               return 0;
+               goto set_autoidle;
 
        best_mode = fls(ddata->cfg.midlemodes) - 1;
        if (best_mode > SYSC_IDLE_MASK) {
@@ -905,6 +905,14 @@ set_midle:
        reg |= best_mode << regbits->midle_shift;
        sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
 
+set_autoidle:
+       /* Autoidle bit must enabled separately if available */
+       if (regbits->autoidle_shift >= 0 &&
+           ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) {
+               reg |= 1 << regbits->autoidle_shift;
+               sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
+       }
+
        return 0;
 }
 
@@ -966,6 +974,9 @@ set_sidle:
 
        reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
        reg |= best_mode << regbits->sidle_shift;
+       if (regbits->autoidle_shift >= 0 &&
+           ddata->cfg.sysc_val & BIT(regbits->autoidle_shift))
+               reg |= 1 << regbits->autoidle_shift;
        sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
 
        return 0;