arm64: Add support for ACPI based firmware tables

BugLink: https://bugs.launchpad.net/bugs/1770231
The /sys cache entries should support ACPI/PPTT generated cache
topology information.  For arm64, if ACPI is enabled, determine
the max number of cache levels and populate them using the PPTT
table if one is available.

Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Vijaya Kumar K <vkilari@codeaurora.org>
Tested-by: Xiongfeng Wang <wangxiongfeng2@huawei.com>
Tested-by: Tomasz Nowicki <Tomasz.Nowicki@cavium.com>
Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
(cherry picked from commit 8571890e1513bc6768495b6541fb8064e046a61c linux-next)
Signed-off-by: dann frazier <dann.frazier@canonical.com>
Acked-by: Stefan Bader <stefan.bader@canonical.com>
Acked-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
Signed-off-by: Khalid Elmously <khalid.elmously@canonical.com>

diff --git a/arch/arm64/kernel/cacheinfo.c b/arch/arm64/kernel/cacheinfo.c
index 380f2e2fbed5bfa09d556d5d9ec019e8e18e4fac..0bf0a835122f8d64b4e90e736c277e357d4f1084 100644 (file)
--- a/arch/arm64/kernel/cacheinfo.c
+++ b/arch/arm64/kernel/cacheinfo.c
@@ -17,6 +17,7 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+#include <linux/acpi.h>
 #include <linux/cacheinfo.h>
 #include <linux/of.h>
 
@@ -46,7 +47,7 @@ static void ci_leaf_init(struct cacheinfo *this_leaf,
 
 static int __init_cache_level(unsigned int cpu)
 {
-       unsigned int ctype, level, leaves, of_level;
+       unsigned int ctype, level, leaves, fw_level;
        struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
 
        for (level = 1, leaves = 0; level <= MAX_CACHE_LEVEL; level++) {
@@ -59,15 +60,19 @@ static int __init_cache_level(unsigned int cpu)
                leaves += (ctype == CACHE_TYPE_SEPARATE) ? 2 : 1;
        }
 
-       of_level = of_find_last_cache_level(cpu);
-       if (level < of_level) {
+       if (acpi_disabled)
+               fw_level = of_find_last_cache_level(cpu);
+       else
+               fw_level = acpi_find_last_cache_level(cpu);
+
+       if (level < fw_level) {
                /*
                 * some external caches not specified in CLIDR_EL1
                 * the information may be available in the device tree
                 * only unified external caches are considered here
                 */
-               leaves += (of_level - level);
-               level = of_level;
+               leaves += (fw_level - level);
+               level = fw_level;
        }
 
        this_cpu_ci->num_levels = level;