drm/i915: add WRPLL divider programming bits

Those are used to program the WRPLL dividers correctly for each gives
frequency.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bc1a5c60822ebe5fa55499f3fc673325c85ecd41..0668815d05d762298712e408b8f3a71ae52ca9ff 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4191,6 +4191,10 @@
 #define  WRPLL_PLL_SELECT_SSC                  (0x01<<28)
 #define  WRPLL_PLL_SELECT_NON_SCC              (0x02<<28)
 #define  WRPLL_PLL_SELECT_LCPLL_2700   (0x03<<28)
+/* WRPLL divider programming */
+#define  WRPLL_DIVIDER_REFERENCE(x)            ((x)<<0)
+#define  WRPLL_DIVIDER_POST(x)                 ((x)<<8)
+#define  WRPLL_DIVIDER_FEEDBACK(x)             ((x)<<16)
 
 /* Port clock selection */
 #define PORT_CLK_SEL_A                 0x46100