net: ethernet: mtk_eth_soc: fix RSTCTRL_PPE{0,1} definitions

Fix RSTCTRL_PPE0 and RSTCTRL_PPE1 register mask definitions for
MTK_NETSYS_V2.
Remove duplicated definitions.

Fixes: 160d3a9b1929 ("net: ethernet: mtk_eth_soc: introduce MTK_NETSYS_V2 support")
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 41eca4887f18d812e466a6949567f8259f94112d..4c9972a94451656042ecee0b10b01d80cc9b51c5 100644 (file)
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -3506,16 +3506,17 @@ static int mtk_hw_init(struct mtk_eth *eth)
                return 0;
        }
 
-       val = RSTCTRL_FE | RSTCTRL_PPE;
        if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
                regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0);
-
-               val |= RSTCTRL_ETH;
-               if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
-                       val |= RSTCTRL_PPE1;
+               val = RSTCTRL_PPE0_V2;
+       } else {
+               val = RSTCTRL_PPE0;
        }
 
-       ethsys_reset(eth, val);
+       if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
+               val |= RSTCTRL_PPE1;
+
+       ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val);
 
        if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
                regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,

diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 1581eba053ab32c48582210fbd573afceaa0ea49..18a50529ce7b499dccd853d2a60eb0ee52b31597 100644 (file)
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -474,18 +474,14 @@
 /* ethernet reset control register */
 #define ETHSYS_RSTCTRL                 0x34
 #define RSTCTRL_FE                     BIT(6)
-#define RSTCTRL_PPE                    BIT(31)
-#define RSTCTRL_PPE1                   BIT(30)
+#define RSTCTRL_PPE0                   BIT(31)
+#define RSTCTRL_PPE0_V2                        BIT(30)
+#define RSTCTRL_PPE1                   BIT(31)
 #define RSTCTRL_ETH                    BIT(23)
 
 /* ethernet reset check idle register */
 #define ETHSYS_FE_RST_CHK_IDLE_EN      0x28
 
-/* ethernet reset control register */
-#define ETHSYS_RSTCTRL         0x34
-#define RSTCTRL_FE             BIT(6)
-#define RSTCTRL_PPE            BIT(31)
-
 /* ethernet dma channel agent map */
 #define ETHSYS_DMA_AG_MAP      0x408
 #define ETHSYS_DMA_AG_MAP_PDMA BIT(0)