Move cpu_has_work and cpu_pc_from_tb to cpu.h

Move functions cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h. This is
needed by later patches.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>

diff --git a/exec-all.h b/exec-all.h
index efef1cd8ba64027a08f5076006a9ae9521c95c9f..21a69d68adedb8fdb6f7c8c224c3c8d42026ad21 100644 (file)
--- a/exec-all.h
+++ b/exec-all.h
@@ -40,6 +40,7 @@ typedef ram_addr_t tb_page_addr_t;
 #define DISAS_UPDATE  2 /* cpu state was modified dynamically */
 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
 
+struct TranslationBlock;
 typedef struct TranslationBlock TranslationBlock;
 
 /* XXX: make safe guess about sizes */

diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
index e98b32513cccf28eba147d327931d07a99826e95..411bd55328818023c7b591277d7d770a976d98e9 100644 (file)
--- a/target-alpha/cpu.h
+++ b/target-alpha/cpu.h
@@ -492,4 +492,26 @@ static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
 }
 #endif
 
+static inline bool cpu_has_work(CPUState *env)
+{
+    /* Here we are checking to see if the CPU should wake up from HALT.
+       We will have gotten into this state only for WTINT from PALmode.  */
+    /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU
+       asleep even if (some) interrupts have been asserted.  For now,
+       assume that if a CPU really wants to stay asleep, it will mask
+       interrupts at the chipset level, which will prevent these bits
+       from being set in the first place.  */
+    return env->interrupt_request & (CPU_INTERRUPT_HARD
+                                     | CPU_INTERRUPT_TIMER
+                                     | CPU_INTERRUPT_SMP
+                                     | CPU_INTERRUPT_MCHK);
+}
+
+#include "exec-all.h"
+
+static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+{
+    env->pc = tb->pc;
+}
+
 #endif /* !defined (__CPU_ALPHA_H__) */

diff --git a/target-alpha/exec.h b/target-alpha/exec.h
index 0f9b827015e8ffcb3ff8ca4593db4133951c8e9a..f5089963b8c83c5fa387c674d10c2079f4ccdc7d 100644 (file)
--- a/target-alpha/exec.h
+++ b/target-alpha/exec.h
@@ -37,24 +37,4 @@ register struct CPUAlphaState *env asm(AREG0);
 #include "softmmu_exec.h"
 #endif /* !defined(CONFIG_USER_ONLY) */
 
-static inline bool cpu_has_work(CPUState *env)
-{
-    /* Here we are checking to see if the CPU should wake up from HALT.
-       We will have gotten into this state only for WTINT from PALmode.  */
-    /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU
-       asleep even if (some) interrupts have been asserted.  For now, 
-       assume that if a CPU really wants to stay asleep, it will mask
-       interrupts at the chipset level, which will prevent these bits
-       from being set in the first place.  */
-    return env->interrupt_request & (CPU_INTERRUPT_HARD
-                                     | CPU_INTERRUPT_TIMER
-                                     | CPU_INTERRUPT_SMP
-                                     | CPU_INTERRUPT_MCHK);
-}
-
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
-{
-    env->pc = tb->pc;
-}
-
 #endif /* !defined (__ALPHA_EXEC_H__) */

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 01f5b57fbc2698636c73213d991d33dbe6100d67..116131eef845a12c20c0ac6347638d74b88b9443 100644 (file)
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -512,4 +512,17 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
     }
 }
 
+static inline bool cpu_has_work(CPUState *env)
+{
+    return env->interrupt_request &
+        (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
+}
+
+#include "exec-all.h"
+
+static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+{
+    env->regs[15] = tb->pc;
+}
+
 #endif

diff --git a/target-arm/exec.h b/target-arm/exec.h
index 9c31418a14ef332bfe8068ce5798affd82ef6168..007b7cb6df3ed75179a92753a4d3c7a89a9ed988 100644 (file)
--- a/target-arm/exec.h
+++ b/target-arm/exec.h
@@ -24,20 +24,8 @@ register struct CPUARMState *env asm(AREG0);
 #include "cpu.h"
 #include "exec-all.h"
 
-static inline bool cpu_has_work(CPUState *env)
-{
-    return env->interrupt_request &
-        (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
-}
-
 #if !defined(CONFIG_USER_ONLY)
 #include "softmmu_exec.h"
 #endif
 
 void raise_exception(int);
-
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
-{
-    env->regs[15] = tb->pc;
-}
-

diff --git a/target-cris/cpu.h b/target-cris/cpu.h
index 2bc35e49754a3d78a2d955aa3b9bc3945b245164..ecb0df1d337eadfec954a41b16b3a8c7497b3f96 100644 (file)
--- a/target-cris/cpu.h
+++ b/target-cris/cpu.h
@@ -268,4 +268,15 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
 #define cpu_list cris_cpu_list
 void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 
+static inline bool cpu_has_work(CPUState *env)
+{
+    return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
+}
+
+#include "exec-all.h"
+
+static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+{
+    env->pc = tb->pc;
+}
 #endif

diff --git a/target-cris/exec.h b/target-cris/exec.h
index 70d99d184fde63473055c24e6e0936b7cc339af1..9838159172ffcbc74f9c3ec146349fa8781c2ba1 100644 (file)
--- a/target-cris/exec.h
+++ b/target-cris/exec.h
@@ -27,14 +27,3 @@ register struct CPUCRISState *env asm(AREG0);
 #if !defined(CONFIG_USER_ONLY)
 #include "softmmu_exec.h"
 #endif
-
-static inline bool cpu_has_work(CPUState *env)
-{
-    return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
-}
-
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
-{
-    env->pc = tb->pc;
-}
-

diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 656d36071615a95b69ad1b33d4914812860b74ad..9819b5fdb9977734fb1340cc9915a0aa2bd91f28 100644 (file)
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -957,6 +957,36 @@ static inline int cpu_mmu_index (CPUState *env)
     return (env->hflags & HF_CPL_MASK) == 3 ? 1 : 0;
 }
 
+#undef EAX
+#define EAX (env->regs[R_EAX])
+#undef ECX
+#define ECX (env->regs[R_ECX])
+#undef EDX
+#define EDX (env->regs[R_EDX])
+#undef EBX
+#define EBX (env->regs[R_EBX])
+#undef ESP
+#define ESP (env->regs[R_ESP])
+#undef EBP
+#define EBP (env->regs[R_EBP])
+#undef ESI
+#define ESI (env->regs[R_ESI])
+#undef EDI
+#define EDI (env->regs[R_EDI])
+#undef EIP
+#define EIP (env->eip)
+#define DF  (env->df)
+
+#define CC_SRC (env->cc_src)
+#define CC_DST (env->cc_dst)
+#define CC_OP  (env->cc_op)
+
+/* float macros */
+#define FT0    (env->ft0)
+#define ST0    (env->fpregs[env->fpstt].d)
+#define ST(n)  (env->fpregs[(env->fpstt + (n)) & 7].d)
+#define ST1    ST(1)
+
 /* translate.c */
 void optimize_flags_init(void);
 
@@ -981,6 +1011,23 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
 #include "hw/apic.h"
 #endif
 
+static inline bool cpu_has_work(CPUState *env)
+{
+    return ((env->interrupt_request & CPU_INTERRUPT_HARD) &&
+            (env->eflags & IF_MASK)) ||
+           (env->interrupt_request & (CPU_INTERRUPT_NMI |
+                                      CPU_INTERRUPT_INIT |
+                                      CPU_INTERRUPT_SIPI |
+                                      CPU_INTERRUPT_MCE));
+}
+
+#include "exec-all.h"
+
+static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+{
+    env->eip = tb->pc - tb->cs_base;
+}
+
 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
                                         target_ulong *cs_base, int *flags)
 {

diff --git a/target-i386/exec.h b/target-i386/exec.h
index 77bb356d7def44bf39272eaa5b7036bc899cea16..90a6b368820329625399828a392485c8a17ddc72 100644 (file)
--- a/target-i386/exec.h
+++ b/target-i386/exec.h
@@ -33,36 +33,6 @@ register struct CPUX86State *env asm(AREG0);
 #include "qemu-common.h"
 #include "qemu-log.h"
 
-#undef EAX
-#define EAX (env->regs[R_EAX])
-#undef ECX
-#define ECX (env->regs[R_ECX])
-#undef EDX
-#define EDX (env->regs[R_EDX])
-#undef EBX
-#define EBX (env->regs[R_EBX])
-#undef ESP
-#define ESP (env->regs[R_ESP])
-#undef EBP
-#define EBP (env->regs[R_EBP])
-#undef ESI
-#define ESI (env->regs[R_ESI])
-#undef EDI
-#define EDI (env->regs[R_EDI])
-#undef EIP
-#define EIP (env->eip)
-#define DF  (env->df)
-
-#define CC_SRC (env->cc_src)
-#define CC_DST (env->cc_dst)
-#define CC_OP  (env->cc_op)
-
-/* float macros */
-#define FT0    (env->ft0)
-#define ST0    (env->fpregs[env->fpstt].d)
-#define ST(n)  (env->fpregs[(env->fpstt + (n)) & 7].d)
-#define ST1    ST(1)
-
 #include "cpu.h"
 #include "exec-all.h"
 
@@ -160,16 +130,6 @@ static inline void load_eflags(int eflags, int update_mask)
         (eflags & update_mask) | 0x2;
 }
 
-static inline bool cpu_has_work(CPUState *env)
-{
-    return ((env->interrupt_request & CPU_INTERRUPT_HARD) &&
-            (env->eflags & IF_MASK)) ||
-           (env->interrupt_request & (CPU_INTERRUPT_NMI |
-                                      CPU_INTERRUPT_INIT |
-                                      CPU_INTERRUPT_SIPI |
-                                      CPU_INTERRUPT_MCE));
-}
-
 /* load efer and update the corresponding hflags. XXX: do consistency
    checks with cpuid bits ? */
 static inline void cpu_load_efer(CPUState *env, uint64_t val)
@@ -181,9 +141,3 @@ static inline void cpu_load_efer(CPUState *env, uint64_t val)
     if (env->efer & MSR_EFER_SVME)
         env->hflags |= HF_SVME_MASK;
 }
-
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
-{
-    env->eip = tb->pc - tb->cs_base;
-}
-

diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h
index 8e2d26b995ce03442f25f822d8a4b519e62f13ce..876b5be2bdbdf38334168317ea28db70796d5984 100644 (file)
--- a/target-lm32/cpu.h
+++ b/target-lm32/cpu.h
@@ -241,4 +241,17 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
     *cs_base = 0;
     *flags = 0;
 }
+
+static inline bool cpu_has_work(CPUState *env)
+{
+    return env->interrupt_request & CPU_INTERRUPT_HARD;
+}
+
+#include "exec-all.h"
+
+static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+{
+    env->pc = tb->pc;
+}
+
 #endif

diff --git a/target-lm32/exec.h b/target-lm32/exec.h
index 83ddb6587f4afad23ec9220842c57a7b8e0b623e..61eb914cfae74d4c59906f3827acbd313ed8d3b2 100644 (file)
--- a/target-lm32/exec.h
+++ b/target-lm32/exec.h
@@ -24,11 +24,6 @@ register struct CPULM32State *env asm(AREG0);
 #include "cpu.h"
 #include "exec-all.h"
 
-static inline bool cpu_has_work(CPUState *env)
-{
-    return env->interrupt_request & CPU_INTERRUPT_HARD;
-}
-
 static inline int cpu_halted(CPUState *env)
 {
     if (!env->halted) {
@@ -42,9 +37,3 @@ static inline int cpu_halted(CPUState *env)
     }
     return EXCP_HALTED;
 }
-
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
-{
-    env->pc = tb->pc;
-}
-

diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h
index 4d8ba287b1dc110bd7da86a1f6d409cb7bfe8199..e0f9b3201476476d01ecb54a84613e495f3c6a06 100644 (file)
--- a/target-m68k/cpu.h
+++ b/target-m68k/cpu.h
@@ -255,4 +255,16 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
             | ((env->macsr >> 4) & 0xf);        /* Bits 0-3 */
 }
 
+static inline bool cpu_has_work(CPUState *env)
+{
+    return env->interrupt_request & CPU_INTERRUPT_HARD;
+}
+
+#include "exec-all.h"
+
+static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+{
+    env->pc = tb->pc;
+}
+
 #endif

diff --git a/target-m68k/exec.h b/target-m68k/exec.h
index f7abbf4d26a8bf8a37d7b1394df73c9798e3c707..568260c3ddd4b32aecc906e3a635a6ad7292a27d 100644 (file)
--- a/target-m68k/exec.h
+++ b/target-m68k/exec.h
@@ -27,14 +27,3 @@ register struct CPUM68KState *env asm(AREG0);
 #if !defined(CONFIG_USER_ONLY)
 #include "softmmu_exec.h"
 #endif
-
-static inline bool cpu_has_work(CPUState *env)
-{
-    return env->interrupt_request & (CPU_INTERRUPT_HARD);
-}
-
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
-{
-    env->pc = tb->pc;
-}
-

diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
index 78fe14ff35d4aacac183560d7bd34ec26a256e41..51a13e38d139e07b3aaad3ef8defc2daa8341fc7 100644 (file)
--- a/target-microblaze/cpu.h
+++ b/target-microblaze/cpu.h
@@ -350,4 +350,17 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
                           int is_asi, int size);
 #endif
+
+static inline bool cpu_has_work(CPUState *env)
+{
+    return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
+}
+
+#include "exec-all.h"
+
+static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+{
+    env->sregs[SR_PC] = tb->pc;
+}
+
 #endif

diff --git a/target-microblaze/exec.h b/target-microblaze/exec.h
index bb2b7db0b0662e9aace36049a8f4700364b014aa..b7f85cf3af993df612b2379f43990cd852e9a543 100644 (file)
--- a/target-microblaze/exec.h
+++ b/target-microblaze/exec.h
@@ -26,14 +26,3 @@ register struct CPUMBState *env asm(AREG0);
 #if !defined(CONFIG_USER_ONLY)
 #include "softmmu_exec.h"
 #endif
-
-static inline bool cpu_has_work(CPUState *env)
-{
-    return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
-}
-
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
-{
-    env->sregs[SR_PC] = tb->pc;
-}
-

diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 0b98d10266ba3d66636ac153860395dc1c625e87..b0ac4da5a7a7c9a5992462ce3e4e3c6c69644db0 100644 (file)
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -656,4 +656,28 @@ static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
     env->tls_value = newtls;
 }
 
+static inline int cpu_has_work(CPUState *env)
+{
+    int has_work = 0;
+
+    /* It is implementation dependent if non-enabled interrupts
+       wake-up the CPU, however most of the implementations only
+       check for interrupts that can be taken. */
+    if ((env->interrupt_request & CPU_INTERRUPT_HARD) &&
+        cpu_mips_hw_interrupts_pending(env)) {
+        has_work = 1;
+    }
+
+    return has_work;
+}
+
+#include "exec-all.h"
+
+static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+{
+    env->active_tc.PC = tb->pc;
+    env->hflags &= ~MIPS_HFLAG_BMASK;
+    env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
+}
+
 #endif /* !defined (__MIPS_CPU_H__) */

diff --git a/target-mips/exec.h b/target-mips/exec.h
index e908c3f04b8684f1d401d2dacbb598ce022f8af4..a3a7262a84bdb875a9ec89a02c4b81c9ebeb5057 100644 (file)
--- a/target-mips/exec.h
+++ b/target-mips/exec.h
@@ -17,21 +17,6 @@ register struct CPUMIPSState *env asm(AREG0);
 #include "softmmu_exec.h"
 #endif /* !defined(CONFIG_USER_ONLY) */
 
-static inline bool cpu_has_work(CPUState *env)
-{
-    int has_work = 0;
-
-    /* It is implementation dependent if non-enabled interrupts
-       wake-up the CPU, however most of the implementations only
-       check for interrupts that can be taken. */
-    if ((env->interrupt_request & CPU_INTERRUPT_HARD) &&
-        cpu_mips_hw_interrupts_pending(env)) {
-        has_work = 1;
-    }
-
-    return has_work;
-}
-
 static inline void compute_hflags(CPUState *env)
 {
     env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
@@ -73,11 +58,4 @@ static inline void compute_hflags(CPUState *env)
     }
 }
 
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
-{
-    env->active_tc.PC = tb->pc;
-    env->hflags &= ~MIPS_HFLAG_BMASK;
-    env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
-}
-
 #endif /* !defined(__QEMU_MIPS_EXEC_H__) */

diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 8e4582f6abfcb41663b51ee5b37fcb714590ea51..6d60d147691276ed3cb21edbd0bb67209b2fdb19 100644 (file)
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1999,4 +1999,16 @@ static inline ppcemb_tlb_t *booke206_get_tlbe(CPUState *env, const int tlbn,
 
 extern void (*cpu_ppc_hypercall)(CPUState *);
 
+static inline bool cpu_has_work(CPUState *env)
+{
+    return msr_ee && (env->interrupt_request & CPU_INTERRUPT_HARD);
+}
+
+#include "exec-all.h"
+
+static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+{
+    env->nip = tb->pc;
+}
+
 #endif /* !defined (__CPU_PPC_H__) */

diff --git a/target-ppc/exec.h b/target-ppc/exec.h
index 81c3c547f8e821aad2e99595292abdd831929cb8..1e144bee3b8080f413cce8754eeba6e6711fd397 100644 (file)
--- a/target-ppc/exec.h
+++ b/target-ppc/exec.h
@@ -32,15 +32,4 @@ register struct CPUPPCState *env asm(AREG0);
 #include "softmmu_exec.h"
 #endif /* !defined(CONFIG_USER_ONLY) */
 
-static inline bool cpu_has_work(CPUState *env)
-{
-    return msr_ee && (env->interrupt_request & CPU_INTERRUPT_HARD);
-}
-
-
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
-{
-    env->nip = tb->pc;
-}
-
 #endif /* !defined (__PPC_H__) */

diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
index b5e587fbe635691d76f5598feb135f41d4b93c49..d48a9b7a0c0f84420843a6273e3976289eea53cc 100644 (file)
--- a/target-s390x/cpu.h
+++ b/target-s390x/cpu.h
@@ -962,4 +962,15 @@ static inline void cpu_inject_ext(CPUState *env, uint32_t code, uint32_t param,
     cpu_interrupt(env, CPU_INTERRUPT_HARD);
 }
 
+static inline bool cpu_has_work(CPUState *env)
+{
+    return (env->interrupt_request & CPU_INTERRUPT_HARD) &&
+        (env->psw.mask & PSW_MASK_EXT);
+}
+
+static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock* tb)
+{
+    env->psw.addr = tb->pc;
+}
+
 #endif

diff --git a/target-s390x/exec.h b/target-s390x/exec.h
index 9ababe174fe19aab24ed6d6eb793394034af8380..d40640b675501f5a925cd9cae6b07c6d5aa1b899 100644 (file)
--- a/target-s390x/exec.h
+++ b/target-s390x/exec.h
@@ -29,12 +29,6 @@ register struct CPUS390XState *env asm(AREG0);
 #include "softmmu_exec.h"
 #endif /* !defined(CONFIG_USER_ONLY) */
 
-static inline bool cpu_has_work(CPUState *env)
-{
-    return (env->interrupt_request & CPU_INTERRUPT_HARD) &&
-        (env->psw.mask & PSW_MASK_EXT);
-}
-
 static inline void regs_to_env(void)
 {
 }
@@ -42,9 +36,3 @@ static inline void regs_to_env(void)
 static inline void env_to_regs(void)
 {
 }
-
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock* tb)
-{
-    env->psw.addr = tb->pc;
-}
-

diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index 74ff97a908fd1a22ac9203507d57bfc4e7444936..00e32f2b10bfa0e9960a07c003b32eea6a3d54fe 100644 (file)
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -361,4 +361,17 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
             | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 4 */
 }
 
+static inline bool cpu_has_work(CPUState *env)
+{
+    return env->interrupt_request & CPU_INTERRUPT_HARD;
+}
+
+#include "exec-all.h"
+
+static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+{
+    env->pc = tb->pc;
+    env->flags = tb->flags;
+}
+
 #endif                         /* _CPU_SH4_H */

diff --git a/target-sh4/exec.h b/target-sh4/exec.h
index ff068c550eec05fef028a6b7decd14beefcd345e..a537672981edb894688e6f97ed82168ec9877529 100644 (file)
--- a/target-sh4/exec.h
+++ b/target-sh4/exec.h
@@ -27,19 +27,8 @@ register struct CPUSH4State *env asm(AREG0);
 #include "cpu.h"
 #include "exec-all.h"
 
-static inline bool cpu_has_work(CPUState *env)
-{
-    return env->interrupt_request & CPU_INTERRUPT_HARD;
-}
-
 #ifndef CONFIG_USER_ONLY
 #include "softmmu_exec.h"
 #endif
 
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
-{
-    env->pc = tb->pc;
-    env->flags = tb->flags;
-}
-
 #endif                         /* _EXEC_SH4_H */

diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 94321f8392e2cc7f03fef02eebe7078551fcf292..4edae78ca3ca67022825ac2c6d92eef07643d42e 100644 (file)
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -662,4 +662,18 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
 /* helper.c */
 void do_interrupt(CPUState *env);
 
+static inline bool cpu_has_work(CPUState *env1)
+{
+    return (env1->interrupt_request & CPU_INTERRUPT_HARD) &&
+           cpu_interrupts_enabled(env1);
+}
+
+#include "exec-all.h"
+
+static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+{
+    env->pc = tb->pc;
+    env->npc = tb->cs_base;
+}
+
 #endif

diff --git a/target-sparc/exec.h b/target-sparc/exec.h
index c1ac2fd8b33da30ea567766c056f0ef5d73e7057..2395b0092f92a5a793665bfadf03cabe83c25487 100644 (file)
--- a/target-sparc/exec.h
+++ b/target-sparc/exec.h
@@ -12,18 +12,4 @@ register struct CPUSPARCState *env asm(AREG0);
 #include "softmmu_exec.h"
 #endif /* !defined(CONFIG_USER_ONLY) */
 
-/* op_helper.c */
-static inline bool cpu_has_work(CPUState *env1)
-{
-    return (env1->interrupt_request & CPU_INTERRUPT_HARD) &&
-           cpu_interrupts_enabled(env1);
-}
-
-
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
-{
-    env->pc = tb->pc;
-    env->npc = tb->cs_base;
-}
-
 #endif

diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h
index 1e10049f890f0d44ce54b58daf9228d07809a690..981760734f2f52e8e561e277df48df5e2f20b285 100644 (file)
--- a/target-unicore32/cpu.h
+++ b/target-unicore32/cpu.h
@@ -179,4 +179,10 @@ void uc32_translate_init(void);
 void do_interrupt(CPUState *);
 void switch_mode(CPUState_UniCore32 *, int);
 
+static inline bool cpu_has_work(CPUState *env)
+{
+    return env->interrupt_request &
+        (CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
+}
+
 #endif /* __CPU_UC32_H__ */

diff --git a/target-unicore32/exec.h b/target-unicore32/exec.h
index ce4132fc894dc6cf58234429d17431d35a52edee..6b9b4996454064c551fd9435cf1fafdbe93941a5 100644 (file)
--- a/target-unicore32/exec.h
+++ b/target-unicore32/exec.h
@@ -26,12 +26,6 @@ static inline void regs_to_env(void)
 {
 }
 
-static inline bool cpu_has_work(CPUState *env)
-{
-    return env->interrupt_request &
-        (CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
-}
-
 static inline int cpu_halted(CPUState *env)
 {
     if (!env->halted) {

diff --git a/xen-mapcache-stub.c b/xen-mapcache-stub.c
index 8a2380a151978a8735c797529be871b338958b05..5eb3dac366032dd37eaa961004284ac6401d02e0 100644 (file)
--- a/xen-mapcache-stub.c
+++ b/xen-mapcache-stub.c
@@ -8,6 +8,7 @@
 
 #include "config.h"
 
+#include "cpu.h"
 #include "exec-all.h"
 #include "qemu-common.h"
 #include "cpu-common.h"