drm/i915/mg: Use tc_port instead of port parameter to MG registers

All the MG registers is based on the tc_port not port, so
MG_PHY_PORT_LN() was subtracting port and PORT_C what is very
fragile.
So replacing port to tc_port in all MG register macros and users
like we have for DKL.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191001193729.123736-1-jose.souza@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index b463e51f8b45904e1c6e69c6df52c0d12ee58d0c..3c1e885e01877f3d1b9edbcb3ec722a11ba5e49b 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2681,7 +2681,7 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
                                           u32 level)
 {
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-       enum port port = encoder->port;
+       enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
        const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
        u32 n_entries, val;
        int ln;
@@ -2697,33 +2697,33 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
 
        /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
        for (ln = 0; ln < 2; ln++) {
-               val = I915_READ(MG_TX1_LINK_PARAMS(ln, port));
+               val = I915_READ(MG_TX1_LINK_PARAMS(ln, tc_port));
                val &= ~CRI_USE_FS32;
-               I915_WRITE(MG_TX1_LINK_PARAMS(ln, port), val);
+               I915_WRITE(MG_TX1_LINK_PARAMS(ln, tc_port), val);
 
-               val = I915_READ(MG_TX2_LINK_PARAMS(ln, port));
+               val = I915_READ(MG_TX2_LINK_PARAMS(ln, tc_port));
                val &= ~CRI_USE_FS32;
-               I915_WRITE(MG_TX2_LINK_PARAMS(ln, port), val);
+               I915_WRITE(MG_TX2_LINK_PARAMS(ln, tc_port), val);
        }
 
        /* Program MG_TX_SWINGCTRL with values from vswing table */
        for (ln = 0; ln < 2; ln++) {
-               val = I915_READ(MG_TX1_SWINGCTRL(ln, port));
+               val = I915_READ(MG_TX1_SWINGCTRL(ln, tc_port));
                val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
                val |= CRI_TXDEEMPH_OVERRIDE_17_12(
                        ddi_translations[level].cri_txdeemph_override_17_12);
-               I915_WRITE(MG_TX1_SWINGCTRL(ln, port), val);
+               I915_WRITE(MG_TX1_SWINGCTRL(ln, tc_port), val);
 
-               val = I915_READ(MG_TX2_SWINGCTRL(ln, port));
+               val = I915_READ(MG_TX2_SWINGCTRL(ln, tc_port));
                val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
                val |= CRI_TXDEEMPH_OVERRIDE_17_12(
                        ddi_translations[level].cri_txdeemph_override_17_12);
-               I915_WRITE(MG_TX2_SWINGCTRL(ln, port), val);
+               I915_WRITE(MG_TX2_SWINGCTRL(ln, tc_port), val);
        }
 
        /* Program MG_TX_DRVCTRL with values from vswing table */
        for (ln = 0; ln < 2; ln++) {
-               val = I915_READ(MG_TX1_DRVCTRL(ln, port));
+               val = I915_READ(MG_TX1_DRVCTRL(ln, tc_port));
                val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
                         CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
                val |= CRI_TXDEEMPH_OVERRIDE_5_0(
@@ -2731,9 +2731,9 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
                        CRI_TXDEEMPH_OVERRIDE_11_6(
                                ddi_translations[level].cri_txdeemph_override_11_6) |
                        CRI_TXDEEMPH_OVERRIDE_EN;
-               I915_WRITE(MG_TX1_DRVCTRL(ln, port), val);
+               I915_WRITE(MG_TX1_DRVCTRL(ln, tc_port), val);
 
-               val = I915_READ(MG_TX2_DRVCTRL(ln, port));
+               val = I915_READ(MG_TX2_DRVCTRL(ln, tc_port));
                val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
                         CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
                val |= CRI_TXDEEMPH_OVERRIDE_5_0(
@@ -2741,7 +2741,7 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
                        CRI_TXDEEMPH_OVERRIDE_11_6(
                                ddi_translations[level].cri_txdeemph_override_11_6) |
                        CRI_TXDEEMPH_OVERRIDE_EN;
-               I915_WRITE(MG_TX2_DRVCTRL(ln, port), val);
+               I915_WRITE(MG_TX2_DRVCTRL(ln, tc_port), val);
 
                /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
        }
@@ -2752,17 +2752,17 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
         * values from table for which TX1 and TX2 enabled.
         */
        for (ln = 0; ln < 2; ln++) {
-               val = I915_READ(MG_CLKHUB(ln, port));
+               val = I915_READ(MG_CLKHUB(ln, tc_port));
                if (link_clock < 300000)
                        val |= CFG_LOW_RATE_LKREN_EN;
                else
                        val &= ~CFG_LOW_RATE_LKREN_EN;
-               I915_WRITE(MG_CLKHUB(ln, port), val);
+               I915_WRITE(MG_CLKHUB(ln, tc_port), val);
        }
 
        /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
        for (ln = 0; ln < 2; ln++) {
-               val = I915_READ(MG_TX1_DCC(ln, port));
+               val = I915_READ(MG_TX1_DCC(ln, tc_port));
                val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
                if (link_clock <= 500000) {
                        val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
@@ -2770,9 +2770,9 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
                        val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
                                CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
                }
-               I915_WRITE(MG_TX1_DCC(ln, port), val);
+               I915_WRITE(MG_TX1_DCC(ln, tc_port), val);
 
-               val = I915_READ(MG_TX2_DCC(ln, port));
+               val = I915_READ(MG_TX2_DCC(ln, tc_port));
                val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
                if (link_clock <= 500000) {
                        val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
@@ -2780,18 +2780,18 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
                        val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
                                CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
                }
-               I915_WRITE(MG_TX2_DCC(ln, port), val);
+               I915_WRITE(MG_TX2_DCC(ln, tc_port), val);
        }
 
        /* Program MG_TX_PISO_READLOAD with values from vswing table */
        for (ln = 0; ln < 2; ln++) {
-               val = I915_READ(MG_TX1_PISO_READLOAD(ln, port));
+               val = I915_READ(MG_TX1_PISO_READLOAD(ln, tc_port));
                val |= CRI_CALCINIT;
-               I915_WRITE(MG_TX1_PISO_READLOAD(ln, port), val);
+               I915_WRITE(MG_TX1_PISO_READLOAD(ln, tc_port), val);
 
-               val = I915_READ(MG_TX2_PISO_READLOAD(ln, port));
+               val = I915_READ(MG_TX2_PISO_READLOAD(ln, tc_port));
                val |= CRI_CALCINIT;
-               I915_WRITE(MG_TX2_PISO_READLOAD(ln, port), val);
+               I915_WRITE(MG_TX2_PISO_READLOAD(ln, tc_port), val);
        }
 }
 
@@ -3150,8 +3150,7 @@ static void
 icl_phy_set_clock_gating(struct intel_digital_port *dig_port, bool enable)
 {
        struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
-       enum port port = dig_port->base.port;
-       enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
+       enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
        u32 val, bits;
        int ln;
 
@@ -3167,7 +3166,7 @@ icl_phy_set_clock_gating(struct intel_digital_port *dig_port, bool enable)
                        I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, ln));
                        val = I915_READ(DKL_DP_MODE(tc_port));
                } else {
-                       val = I915_READ(MG_DP_MODE(ln, port));
+                       val = I915_READ(MG_DP_MODE(ln, tc_port));
                }
 
                if (enable)
@@ -3178,7 +3177,7 @@ icl_phy_set_clock_gating(struct intel_digital_port *dig_port, bool enable)
                if (INTEL_GEN(dev_priv) >= 12)
                        I915_WRITE(DKL_DP_MODE(tc_port), val);
                else
-                       I915_WRITE(MG_DP_MODE(ln, port), val);
+                       I915_WRITE(MG_DP_MODE(ln, tc_port), val);
        }
 
        if (INTEL_GEN(dev_priv) == 11) {
@@ -3203,8 +3202,7 @@ icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port,
                       const struct intel_crtc_state *crtc_state)
 {
        struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
-       enum port port = intel_dig_port->base.port;
-       enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
+       enum tc_port tc_port = intel_port_to_tc(dev_priv, intel_dig_port->base.port);
        u32 ln0, ln1, pin_assignment;
        u8 width;
 
@@ -3217,8 +3215,8 @@ icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port,
                I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x1));
                ln1 = I915_READ(DKL_DP_MODE(tc_port));
        } else {
-               ln0 = I915_READ(MG_DP_MODE(0, port));
-               ln1 = I915_READ(MG_DP_MODE(1, port));
+               ln0 = I915_READ(MG_DP_MODE(0, tc_port));
+               ln1 = I915_READ(MG_DP_MODE(1, tc_port));
        }
 
        ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X1_MODE);
@@ -3280,8 +3278,8 @@ icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port,
                I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x1));
                I915_WRITE(DKL_DP_MODE(tc_port), ln1);
        } else {
-               I915_WRITE(MG_DP_MODE(0, port), ln0);
-               I915_WRITE(MG_DP_MODE(1, port), ln1);
+               I915_WRITE(MG_DP_MODE(0, tc_port), ln0);
+               I915_WRITE(MG_DP_MODE(1, tc_port), ln1);
        }
 }
 

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 058aa5ca8b73f69b6f8f19a2e2de5469afd3aa5c..eefd789b9a28229a44eba4f45055e90451fb7ce5 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1956,8 +1956,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define ICL_DPHY_CHKN(port)                    _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)
 #define   ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP     REG_BIT(7)
 
-#define MG_PHY_PORT_LN(ln, port, ln0p1, ln0p2, ln1p1) \
-       _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
+#define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \
+       _MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
 
 #define MG_TX_LINK_PARAMS_TX1LN0_PORT1         0x16812C
 #define MG_TX_LINK_PARAMS_TX1LN1_PORT1         0x16852C
@@ -1967,10 +1967,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define MG_TX_LINK_PARAMS_TX1LN1_PORT3         0x16A52C
 #define MG_TX_LINK_PARAMS_TX1LN0_PORT4         0x16B12C
 #define MG_TX_LINK_PARAMS_TX1LN1_PORT4         0x16B52C
-#define MG_TX1_LINK_PARAMS(ln, port) \
-       MG_PHY_PORT_LN(ln, port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
-                                MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
-                                MG_TX_LINK_PARAMS_TX1LN1_PORT1)
+#define MG_TX1_LINK_PARAMS(ln, tc_port) \
+       MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
+                                   MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
+                                   MG_TX_LINK_PARAMS_TX1LN1_PORT1)
 
 #define MG_TX_LINK_PARAMS_TX2LN0_PORT1         0x1680AC
 #define MG_TX_LINK_PARAMS_TX2LN1_PORT1         0x1684AC
@@ -1980,10 +1980,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define MG_TX_LINK_PARAMS_TX2LN1_PORT3         0x16A4AC
 #define MG_TX_LINK_PARAMS_TX2LN0_PORT4         0x16B0AC
 #define MG_TX_LINK_PARAMS_TX2LN1_PORT4         0x16B4AC
-#define MG_TX2_LINK_PARAMS(ln, port) \
-       MG_PHY_PORT_LN(ln, port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
-                                MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
-                                MG_TX_LINK_PARAMS_TX2LN1_PORT1)
+#define MG_TX2_LINK_PARAMS(ln, tc_port) \
+       MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
+                                   MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
+                                   MG_TX_LINK_PARAMS_TX2LN1_PORT1)
 #define   CRI_USE_FS32                 (1 << 5)
 
 #define MG_TX_PISO_READLOAD_TX1LN0_PORT1               0x16814C
@@ -1994,10 +1994,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define MG_TX_PISO_READLOAD_TX1LN1_PORT3               0x16A54C
 #define MG_TX_PISO_READLOAD_TX1LN0_PORT4               0x16B14C
 #define MG_TX_PISO_READLOAD_TX1LN1_PORT4               0x16B54C
-#define MG_TX1_PISO_READLOAD(ln, port) \
-       MG_PHY_PORT_LN(ln, port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
-                                MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
-                                MG_TX_PISO_READLOAD_TX1LN1_PORT1)
+#define MG_TX1_PISO_READLOAD(ln, tc_port) \
+       MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
+                                   MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
+                                   MG_TX_PISO_READLOAD_TX1LN1_PORT1)
 
 #define MG_TX_PISO_READLOAD_TX2LN0_PORT1               0x1680CC
 #define MG_TX_PISO_READLOAD_TX2LN1_PORT1               0x1684CC
@@ -2007,10 +2007,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define MG_TX_PISO_READLOAD_TX2LN1_PORT3               0x16A4CC
 #define MG_TX_PISO_READLOAD_TX2LN0_PORT4               0x16B0CC
 #define MG_TX_PISO_READLOAD_TX2LN1_PORT4               0x16B4CC
-#define MG_TX2_PISO_READLOAD(ln, port) \
-       MG_PHY_PORT_LN(ln, port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
-                                MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
-                                MG_TX_PISO_READLOAD_TX2LN1_PORT1)
+#define MG_TX2_PISO_READLOAD(ln, tc_port) \
+       MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
+                                   MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
+                                   MG_TX_PISO_READLOAD_TX2LN1_PORT1)
 #define   CRI_CALCINIT                                 (1 << 1)
 
 #define MG_TX_SWINGCTRL_TX1LN0_PORT1           0x168148
@@ -2021,10 +2021,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define MG_TX_SWINGCTRL_TX1LN1_PORT3           0x16A548
 #define MG_TX_SWINGCTRL_TX1LN0_PORT4           0x16B148
 #define MG_TX_SWINGCTRL_TX1LN1_PORT4           0x16B548
-#define MG_TX1_SWINGCTRL(ln, port) \
-       MG_PHY_PORT_LN(ln, port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
-                                MG_TX_SWINGCTRL_TX1LN0_PORT2, \
-                                MG_TX_SWINGCTRL_TX1LN1_PORT1)
+#define MG_TX1_SWINGCTRL(ln, tc_port) \
+       MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
+                                   MG_TX_SWINGCTRL_TX1LN0_PORT2, \
+                                   MG_TX_SWINGCTRL_TX1LN1_PORT1)
 
 #define MG_TX_SWINGCTRL_TX2LN0_PORT1           0x1680C8
 #define MG_TX_SWINGCTRL_TX2LN1_PORT1           0x1684C8
@@ -2034,10 +2034,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define MG_TX_SWINGCTRL_TX2LN1_PORT3           0x16A4C8
 #define MG_TX_SWINGCTRL_TX2LN0_PORT4           0x16B0C8
 #define MG_TX_SWINGCTRL_TX2LN1_PORT4           0x16B4C8
-#define MG_TX2_SWINGCTRL(ln, port) \
-       MG_PHY_PORT_LN(ln, port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
-                                MG_TX_SWINGCTRL_TX2LN0_PORT2, \
-                                MG_TX_SWINGCTRL_TX2LN1_PORT1)
+#define MG_TX2_SWINGCTRL(ln, tc_port) \
+       MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
+                                   MG_TX_SWINGCTRL_TX2LN0_PORT2, \
+                                   MG_TX_SWINGCTRL_TX2LN1_PORT1)
 #define   CRI_TXDEEMPH_OVERRIDE_17_12(x)               ((x) << 0)
 #define   CRI_TXDEEMPH_OVERRIDE_17_12_MASK             (0x3F << 0)
 
@@ -2049,10 +2049,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define MG_TX_DRVCTRL_TX1LN1_TXPORT3                   0x16A544
 #define MG_TX_DRVCTRL_TX1LN0_TXPORT4                   0x16B144
 #define MG_TX_DRVCTRL_TX1LN1_TXPORT4                   0x16B544
-#define MG_TX1_DRVCTRL(ln, port) \
-       MG_PHY_PORT_LN(ln, port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
-                                MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
-                                MG_TX_DRVCTRL_TX1LN1_TXPORT1)
+#define MG_TX1_DRVCTRL(ln, tc_port) \
+       MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
+                                   MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
+                                   MG_TX_DRVCTRL_TX1LN1_TXPORT1)
 
 #define MG_TX_DRVCTRL_TX2LN0_PORT1                     0x1680C4
 #define MG_TX_DRVCTRL_TX2LN1_PORT1                     0x1684C4
@@ -2062,10 +2062,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define MG_TX_DRVCTRL_TX2LN1_PORT3                     0x16A4C4
 #define MG_TX_DRVCTRL_TX2LN0_PORT4                     0x16B0C4
 #define MG_TX_DRVCTRL_TX2LN1_PORT4                     0x16B4C4
-#define MG_TX2_DRVCTRL(ln, port) \
-       MG_PHY_PORT_LN(ln, port, MG_TX_DRVCTRL_TX2LN0_PORT1, \
-                                MG_TX_DRVCTRL_TX2LN0_PORT2, \
-                                MG_TX_DRVCTRL_TX2LN1_PORT1)
+#define MG_TX2_DRVCTRL(ln, tc_port) \
+       MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX2LN0_PORT1, \
+                                   MG_TX_DRVCTRL_TX2LN0_PORT2, \
+                                   MG_TX_DRVCTRL_TX2LN1_PORT1)
 #define   CRI_TXDEEMPH_OVERRIDE_11_6(x)                        ((x) << 24)
 #define   CRI_TXDEEMPH_OVERRIDE_11_6_MASK              (0x3F << 24)
 #define   CRI_TXDEEMPH_OVERRIDE_EN                     (1 << 22)
@@ -2082,10 +2082,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define MG_CLKHUB_LN1_PORT3                    0x16A79C
 #define MG_CLKHUB_LN0_PORT4                    0x16B39C
 #define MG_CLKHUB_LN1_PORT4                    0x16B79C
-#define MG_CLKHUB(ln, port) \
-       MG_PHY_PORT_LN(ln, port, MG_CLKHUB_LN0_PORT1, \
-                                MG_CLKHUB_LN0_PORT2, \
-                                MG_CLKHUB_LN1_PORT1)
+#define MG_CLKHUB(ln, tc_port) \
+       MG_PHY_PORT_LN(ln, tc_port, MG_CLKHUB_LN0_PORT1, \
+                                   MG_CLKHUB_LN0_PORT2, \
+                                   MG_CLKHUB_LN1_PORT1)
 #define   CFG_LOW_RATE_LKREN_EN                                (1 << 11)
 
 #define MG_TX_DCC_TX1LN0_PORT1                 0x168110
@@ -2096,10 +2096,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define MG_TX_DCC_TX1LN1_PORT3                 0x16A510
 #define MG_TX_DCC_TX1LN0_PORT4                 0x16B110
 #define MG_TX_DCC_TX1LN1_PORT4                 0x16B510
-#define MG_TX1_DCC(ln, port) \
-       MG_PHY_PORT_LN(ln, port, MG_TX_DCC_TX1LN0_PORT1, \
-                                MG_TX_DCC_TX1LN0_PORT2, \
-                                MG_TX_DCC_TX1LN1_PORT1)
+#define MG_TX1_DCC(ln, tc_port) \
+       MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX1LN0_PORT1, \
+                                   MG_TX_DCC_TX1LN0_PORT2, \
+                                   MG_TX_DCC_TX1LN1_PORT1)
 #define MG_TX_DCC_TX2LN0_PORT1                 0x168090
 #define MG_TX_DCC_TX2LN1_PORT1                 0x168490
 #define MG_TX_DCC_TX2LN0_PORT2                 0x169090
@@ -2108,10 +2108,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define MG_TX_DCC_TX2LN1_PORT3                 0x16A490
 #define MG_TX_DCC_TX2LN0_PORT4                 0x16B090
 #define MG_TX_DCC_TX2LN1_PORT4                 0x16B490
-#define MG_TX2_DCC(ln, port) \
-       MG_PHY_PORT_LN(ln, port, MG_TX_DCC_TX2LN0_PORT1, \
-                                MG_TX_DCC_TX2LN0_PORT2, \
-                                MG_TX_DCC_TX2LN1_PORT1)
+#define MG_TX2_DCC(ln, tc_port) \
+       MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX2LN0_PORT1, \
+                                   MG_TX_DCC_TX2LN0_PORT2, \
+                                   MG_TX_DCC_TX2LN1_PORT1)
 #define   CFG_AMI_CK_DIV_OVERRIDE_VAL(x)       ((x) << 25)
 #define   CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK     (0x3 << 25)
 #define   CFG_AMI_CK_DIV_OVERRIDE_EN           (1 << 24)
@@ -2124,10 +2124,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define MG_DP_MODE_LN1_ACU_PORT3                       0x16A7A0
 #define MG_DP_MODE_LN0_ACU_PORT4                       0x16B3A0
 #define MG_DP_MODE_LN1_ACU_PORT4                       0x16B7A0
-#define MG_DP_MODE(ln, port)   \
-       MG_PHY_PORT_LN(ln, port, MG_DP_MODE_LN0_ACU_PORT1, \
-                                MG_DP_MODE_LN0_ACU_PORT2, \
-                                MG_DP_MODE_LN1_ACU_PORT1)
+#define MG_DP_MODE(ln, tc_port)        \
+       MG_PHY_PORT_LN(ln, tc_port, MG_DP_MODE_LN0_ACU_PORT1, \
+                                   MG_DP_MODE_LN0_ACU_PORT2, \
+                                   MG_DP_MODE_LN1_ACU_PORT1)
 #define   MG_DP_MODE_CFG_DP_X2_MODE                    (1 << 7)
 #define   MG_DP_MODE_CFG_DP_X1_MODE                    (1 << 6)
 #define   MG_DP_MODE_CFG_TR2PWR_GATING                 (1 << 5)