net: hns3: add int_gl_idx setup for TX and RX queues

BugLink: http://bugs.launchpad.net/bugs/1756097
If the int_gl_idx does not be set, the default interrupt coalesce index
is 0. The TX queues and the RX queues will both use the GL0 as the
interrupt coalesce GL switch. But it should be GL1 for TX queues and GL0
for RX queues.

This patch adds the int_gl_idx setup for TX queues and RX queues.

Fixes: 76ad4f0ee747 ("net: hns3: Add support of HNS3 Ethernet Driver for hip08 SoC")
Signed-off-by: Fuyun Liang <liangfuyun1@huawei.com>
Signed-off-by: Peng Li <lipeng321@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit 11af96a47beda880e07b6f2f68efaae60794ae78)
Signed-off-by: Manoj Iyer <manoj.iyer@canonical.com>
Signed-off-by: Seth Forshee <seth.forshee@canonical.com>

diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
index 0bad0e37edbda6f1131e933448f2180a453b2fe6..634e9327968b481a218b6e946459164a42bf99e2 100644 (file)
--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
@@ -133,11 +133,16 @@ struct hnae3_vector_info {
 #define HNAE3_RING_TYPE_B 0
 #define HNAE3_RING_TYPE_TX 0
 #define HNAE3_RING_TYPE_RX 1
+#define HNAE3_RING_GL_IDX_S 0
+#define HNAE3_RING_GL_IDX_M GENMASK(1, 0)
+#define HNAE3_RING_GL_RX 0
+#define HNAE3_RING_GL_TX 1
 
 struct hnae3_ring_chain_node {
        struct hnae3_ring_chain_node *next;
        u32 tqp_index;
        u32 flag;
+       u32 int_gl_idx;
 };
 
 #define HNAE3_IS_TX_RING(node) \

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
index 2e9e61c1a50d129ba41a7309e4985d8e8b56697b..34879c45830923a1bda43129fd08cc03d01935e6 100644 (file)
--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
@@ -2523,6 +2523,8 @@ static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
                cur_chain->tqp_index = tx_ring->tqp->tqp_index;
                hnae_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
                             HNAE3_RING_TYPE_TX);
+               hnae_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
+                              HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX);
 
                cur_chain->next = NULL;
 
@@ -2538,6 +2540,10 @@ static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
                        chain->tqp_index = tx_ring->tqp->tqp_index;
                        hnae_set_bit(chain->flag, HNAE3_RING_TYPE_B,
                                     HNAE3_RING_TYPE_TX);
+                       hnae_set_field(chain->int_gl_idx,
+                                      HNAE3_RING_GL_IDX_M,
+                                      HNAE3_RING_GL_IDX_S,
+                                      HNAE3_RING_GL_TX);
 
                        cur_chain = chain;
                }
@@ -2549,6 +2555,8 @@ static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
                cur_chain->tqp_index = rx_ring->tqp->tqp_index;
                hnae_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
                             HNAE3_RING_TYPE_RX);
+               hnae_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
+                              HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
 
                rx_ring = rx_ring->next;
        }
@@ -2562,6 +2570,9 @@ static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
                chain->tqp_index = rx_ring->tqp->tqp_index;
                hnae_set_bit(chain->flag, HNAE3_RING_TYPE_B,
                             HNAE3_RING_TYPE_RX);
+               hnae_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
+                              HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
+
                cur_chain = chain;
 
                rx_ring = rx_ring->next;

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
index d7352f5f75c3f8ed0d4b21d1c222d5eb66563cf3..27f0ab695f5a8386062dd4607c82891112fdfdbc 100644 (file)
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
@@ -3409,6 +3409,11 @@ int hclge_bind_ring_with_vector(struct hclge_vport *vport,
                               hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
                hnae_set_field(tqp_type_and_id, HCLGE_TQP_ID_M,
                               HCLGE_TQP_ID_S, node->tqp_index);
+               hnae_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M,
+                              HCLGE_INT_GL_IDX_S,
+                              hnae_get_field(node->int_gl_idx,
+                                             HNAE3_RING_GL_IDX_M,
+                                             HNAE3_RING_GL_IDX_S));
                req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id);
                if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
                        req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;