drm/amd/pp: Implement get_performance_level for legacy dgpu

display can get clock info through this function.
implement this function for vega10 and old asics.
from vega12, there is no power state management,
so need to add new interface to notify display
the clock info

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
index 6ef3c875fedd555edbd667267639a6ed4aeb4485..85119c2bdcc8ff2e2bbd54b53e204b095decb2d4 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
@@ -359,7 +359,7 @@ int phm_get_clock_info(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *s
                        PHM_PerformanceLevelDesignation designation)
 {
        int result;
-       PHM_PerformanceLevel performance_level;
+       PHM_PerformanceLevel performance_level = {0};
 
        PHM_FUNC_CHECK(hwmgr);
 

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 052e60dfaf9fd77003bc49e82eb2d35646fdace2..380f282a64ba22fd4e24930ed1103937d2ef9aeb 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -5008,6 +5008,29 @@ static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint
        return 0;
 }
 
+static int smu7_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
+                               PHM_PerformanceLevelDesignation designation, uint32_t index,
+                               PHM_PerformanceLevel *level)
+{
+       const struct smu7_power_state *ps;
+       struct smu7_hwmgr *data;
+       uint32_t i;
+
+       if (level == NULL || hwmgr == NULL || state == NULL)
+               return -EINVAL;
+
+       data = hwmgr->backend;
+       ps = cast_const_phw_smu7_power_state(state);
+
+       i = index > ps->performance_level_count - 1 ?
+                       ps->performance_level_count - 1 : index;
+
+       level->coreClock = ps->performance_levels[i].engine_clock;
+       level->memory_clock = ps->performance_levels[i].memory_clock;
+
+       return 0;
+}
+
 static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
        .backend_init = &smu7_hwmgr_backend_init,
        .backend_fini = &smu7_hwmgr_backend_fini,
@@ -5064,6 +5087,7 @@ static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
        .set_power_limit = smu7_set_power_limit,
        .get_power_profile_mode = smu7_get_power_profile_mode,
        .set_power_profile_mode = smu7_set_power_profile_mode,
+       .get_performance_level = smu7_get_performance_level,
 };
 
 uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index fb86c24394ff463f3ee565125d72e27434889038..704b237ecf7051da521d7d955471d57473ddca57 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -4854,6 +4854,29 @@ static int vega10_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
        return 0;
 }
 
+static int vega10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
+                               PHM_PerformanceLevelDesignation designation, uint32_t index,
+                               PHM_PerformanceLevel *level)
+{
+       const struct vega10_power_state *ps;
+       struct vega10_hwmgr *data;
+       uint32_t i;
+
+       if (level == NULL || hwmgr == NULL || state == NULL)
+               return -EINVAL;
+
+       data = hwmgr->backend;
+       ps = cast_const_phw_vega10_power_state(state);
+
+       i = index > ps->performance_level_count - 1 ?
+                       ps->performance_level_count - 1 : index;
+
+       level->coreClock = ps->performance_levels[i].gfx_clock;
+       level->memory_clock = ps->performance_levels[i].mem_clock;
+
+       return 0;
+}
+
 static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
        .backend_init = vega10_hwmgr_backend_init,
        .backend_fini = vega10_hwmgr_backend_fini,
@@ -4913,6 +4936,7 @@ static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
        .set_power_profile_mode = vega10_set_power_profile_mode,
        .set_power_limit = vega10_set_power_limit,
        .odn_edit_dpm_table = vega10_odn_edit_dpm_table,
+       .get_performance_level = vega10_get_performance_level,
 };
 
 int vega10_enable_smc_features(struct pp_hwmgr *hwmgr,