arm64: dts: qcom: msm8996: Add PSCI cpuidle low power states

Add device bindings for cpuidle states for cpu devices.

msm8996 features 4 cpus - 2 in each cluster. However, all cpus implement
the same microarchitecture and the two clusters only differ in the
maximum frequency attainable by the CPUs.

Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <agross@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 0f234bef90ee85984f929bff5320106de1e8df31..778c7f0a2429263f34bc5f0ee2abf8671c2f0846 100644 (file)
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -102,6 +102,7 @@
                        compatible = "qcom,kryo";
                        reg = <0x0 0x0>;
                        enable-method = "psci";
+                       cpu-idle-states = <&CPU_SLEEP_0>;
                        next-level-cache = <&L2_0>;
                        L2_0: l2-cache {
                              compatible = "cache";
@@ -114,6 +115,7 @@
                        compatible = "qcom,kryo";
                        reg = <0x0 0x1>;
                        enable-method = "psci";
+                       cpu-idle-states = <&CPU_SLEEP_0>;
                        next-level-cache = <&L2_0>;
                };
 
@@ -122,6 +124,7 @@
                        compatible = "qcom,kryo";
                        reg = <0x0 0x100>;
                        enable-method = "psci";
+                       cpu-idle-states = <&CPU_SLEEP_0>;
                        next-level-cache = <&L2_1>;
                        L2_1: l2-cache {
                              compatible = "cache";
@@ -134,6 +137,7 @@
                        compatible = "qcom,kryo";
                        reg = <0x0 0x101>;
                        enable-method = "psci";
+                       cpu-idle-states = <&CPU_SLEEP_0>;
                        next-level-cache = <&L2_1>;
                };
 
@@ -158,6 +162,19 @@
                                };
                        };
                };
+
+               idle-states {
+                       entry-method = "psci";
+
+                       CPU_SLEEP_0: cpu-sleep-0 {
+                               compatible = "arm,idle-state";
+                               idle-state-name = "standalone-power-collapse";
+                               arm,psci-suspend-param = <0x00000004>;
+                               entry-latency-us = <40>;
+                               exit-latency-us = <80>;
+                               min-residency-us = <300>;
+                       };
+               };
        };
 
        thermal-zones {