#ifndef SDHCI_INTERNAL_H
#define SDHCI_INTERNAL_H
-#include "hw/sd/sdhci.h"
-
/* R/W SDMA System Address register 0x0 */
#define SDHC_SYSAD 0x00
sdhc_gap_write = 2 /* SDHC stopped at block gap during write operation */
};
-extern const VMStateDescription sdhci_vmstate;
-
#endif
#define SDHCI_H
#include "qemu-common.h"
-#include "hw/block/block.h"
#include "hw/pci/pci.h"
#include "hw/sysbus.h"
#include "hw/sd/sd.h"
/* SD/MMC host controller state */
typedef struct SDHCIState {
+ /*< private >*/
union {
PCIDevice pcidev;
SysBusDevice busdev;
};
+
+ /*< public >*/
SDBus sdbus;
MemoryRegion iomem;
qemu_irq ro_cb;
qemu_irq irq;
+ /* Registers cleared on reset */
uint32_t sdmasysad; /* SDMA System Address register */
uint16_t blksize; /* Host DMA Buff Boundary and Transfer BlkSize Reg */
uint16_t blkcnt; /* Blocks count for current transfer */
uint16_t acmd12errsts; /* Auto CMD12 error status register */
uint64_t admasysaddr; /* ADMA System Address Register */
+ /* Read-only registers */
uint32_t capareg; /* Capabilities Register */
uint32_t maxcurr; /* Maximum Current Capabilities Register */
+
uint8_t *fifo_buffer; /* SD host i/o FIFO buffer */
uint32_t buf_maxsz;
uint16_t data_count; /* current element in FIFO buffer */