selftests: kvm/x86: add test for pmu msr MSR_IA32_PERF_CAPABILITIES

This test will check the effect of various CPUID settings on the
MSR_IA32_PERF_CAPABILITIES MSR, check that whatever user space writes
with KVM_SET_MSR is _not_ modified from the guest and can be retrieved
with KVM_GET_MSR, and check that invalid LBR formats are rejected.

Signed-off-by: Like Xu <like.xu@linux.intel.com>
Message-Id: <20210201051039.255478-12-like.xu@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

diff --git a/tools/testing/selftests/kvm/.gitignore b/tools/testing/selftests/kvm/.gitignore
index a747260662b6c5959730947a28904f594d298c50..c08f26d0aec4537532383716c5f280189fa3f209 100644 (file)
--- a/tools/testing/selftests/kvm/.gitignore
+++ b/tools/testing/selftests/kvm/.gitignore
@@ -26,6 +26,7 @@
 /x86_64/vmx_tsc_adjust_test
 /x86_64/xapic_ipi_test
 /x86_64/xss_msr_test
+/x86_64/vmx_pmu_msrs_test
 /demand_paging_test
 /dirty_log_test
 /dirty_log_perf_test

diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile
index fcc46355d7e14d45904f8e078a96d6f5becde9fa..60410e9ebd41d48e8bf3fe9e15e62c653cf37036 100644 (file)
--- a/tools/testing/selftests/kvm/Makefile
+++ b/tools/testing/selftests/kvm/Makefile
@@ -60,6 +60,7 @@ TEST_GEN_PROGS_x86_64 += x86_64/xapic_ipi_test
 TEST_GEN_PROGS_x86_64 += x86_64/xss_msr_test
 TEST_GEN_PROGS_x86_64 += x86_64/debug_regs
 TEST_GEN_PROGS_x86_64 += x86_64/tsc_msrs_test
+TEST_GEN_PROGS_x86_64 += x86_64/vmx_pmu_msrs_test
 TEST_GEN_PROGS_x86_64 += demand_paging_test
 TEST_GEN_PROGS_x86_64 += dirty_log_test
 TEST_GEN_PROGS_x86_64 += dirty_log_perf_test

diff --git a/tools/testing/selftests/kvm/include/x86_64/processor.h b/tools/testing/selftests/kvm/include/x86_64/processor.h
index 74ce0fe420abeb633b2986b508faa45ea90eeddf..fce4cd4d489532aa23d9c446ca53db5a42280108 100644 (file)
--- a/tools/testing/selftests/kvm/include/x86_64/processor.h
+++ b/tools/testing/selftests/kvm/include/x86_64/processor.h
@@ -338,8 +338,9 @@ void vcpu_load_state(struct kvm_vm *vm, uint32_t vcpuid,
                     struct kvm_x86_state *state);
 
 struct kvm_msr_list *kvm_get_msr_index_list(void);
-
+uint64_t kvm_get_feature_msr(uint64_t msr_index);
 struct kvm_cpuid2 *kvm_get_supported_cpuid(void);
+
 void vcpu_set_cpuid(struct kvm_vm *vm, uint32_t vcpuid,
                    struct kvm_cpuid2 *cpuid);
 

diff --git a/tools/testing/selftests/kvm/lib/x86_64/processor.c b/tools/testing/selftests/kvm/lib/x86_64/processor.c
index 95e1a757c6294fcec49faa18b409b1d24efccc57..66926a7f29cc7836ccb90b4fbf849d77d3a41b7e 100644 (file)
--- a/tools/testing/selftests/kvm/lib/x86_64/processor.c
+++ b/tools/testing/selftests/kvm/lib/x86_64/processor.c
@@ -669,6 +669,40 @@ struct kvm_cpuid2 *kvm_get_supported_cpuid(void)
        return cpuid;
 }
 
+/*
+ * KVM Get MSR
+ *
+ * Input Args:
+ *   msr_index - Index of MSR
+ *
+ * Output Args: None
+ *
+ * Return: On success, value of the MSR. On failure a TEST_ASSERT is produced.
+ *
+ * Get value of MSR for VCPU.
+ */
+uint64_t kvm_get_feature_msr(uint64_t msr_index)
+{
+       struct {
+               struct kvm_msrs header;
+               struct kvm_msr_entry entry;
+       } buffer = {};
+       int r, kvm_fd;
+
+       buffer.header.nmsrs = 1;
+       buffer.entry.index = msr_index;
+       kvm_fd = open(KVM_DEV_PATH, O_RDONLY);
+       if (kvm_fd < 0)
+               exit(KSFT_SKIP);
+
+       r = ioctl(kvm_fd, KVM_GET_MSRS, &buffer.header);
+       TEST_ASSERT(r == 1, "KVM_GET_MSRS IOCTL failed,\n"
+               "  rc: %i errno: %i", r, errno);
+
+       close(kvm_fd);
+       return buffer.entry.data;
+}
+
 /*
  * Locate a cpuid entry.
  *

diff --git a/tools/testing/selftests/kvm/x86_64/vmx_pmu_msrs_test.c b/tools/testing/selftests/kvm/x86_64/vmx_pmu_msrs_test.c
new file mode 100644 (file)
index 0000000..23051d8
--- /dev/null
+++ b/tools/testing/selftests/kvm/x86_64/vmx_pmu_msrs_test.c
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * VMX-pmu related msrs test
+ *
+ * Copyright (C) 2021 Intel Corporation
+ *
+ * Test to check the effect of various CPUID settings
+ * on the MSR_IA32_PERF_CAPABILITIES MSR, and check that
+ * whatever we write with KVM_SET_MSR is _not_ modified
+ * in the guest and test it can be retrieved with KVM_GET_MSR.
+ *
+ * Test to check that invalid LBR formats are rejected.
+ */
+
+#define _GNU_SOURCE /* for program_invocation_short_name */
+#include <sys/ioctl.h>
+
+#include "kvm_util.h"
+#include "vmx.h"
+
+#define VCPU_ID              0
+
+#define X86_FEATURE_PDCM       (1<<15)
+#define PMU_CAP_FW_WRITES      (1ULL << 13)
+#define PMU_CAP_LBR_FMT                0x3f
+
+union cpuid10_eax {
+       struct {
+               unsigned int version_id:8;
+               unsigned int num_counters:8;
+               unsigned int bit_width:8;
+               unsigned int mask_length:8;
+       } split;
+       unsigned int full;
+};
+
+union perf_capabilities {
+       struct {
+               u64     lbr_format:6;
+               u64     pebs_trap:1;
+               u64     pebs_arch_reg:1;
+               u64     pebs_format:4;
+               u64     smm_freeze:1;
+               u64     full_width_write:1;
+               u64 pebs_baseline:1;
+               u64     perf_metrics:1;
+               u64     pebs_output_pt_available:1;
+               u64     anythread_deprecated:1;
+       };
+       u64     capabilities;
+};
+
+static void guest_code(void)
+{
+       wrmsr(MSR_IA32_PERF_CAPABILITIES, PMU_CAP_LBR_FMT);
+}
+
+int main(int argc, char *argv[])
+{
+       struct kvm_cpuid2 *cpuid;
+       struct kvm_cpuid_entry2 *entry_1_0;
+       struct kvm_cpuid_entry2 *entry_a_0;
+       bool pdcm_supported = false;
+       struct kvm_vm *vm;
+       int ret;
+       union cpuid10_eax eax;
+       union perf_capabilities host_cap;
+
+       host_cap.capabilities = kvm_get_feature_msr(MSR_IA32_PERF_CAPABILITIES);
+       host_cap.capabilities &= (PMU_CAP_FW_WRITES | PMU_CAP_LBR_FMT);
+
+       /* Create VM */
+       vm = vm_create_default(VCPU_ID, 0, guest_code);
+       cpuid = kvm_get_supported_cpuid();
+
+       if (kvm_get_cpuid_max_basic() >= 0xa) {
+               entry_1_0 = kvm_get_supported_cpuid_index(1, 0);
+               entry_a_0 = kvm_get_supported_cpuid_index(0xa, 0);
+               pdcm_supported = entry_1_0 && !!(entry_1_0->ecx & X86_FEATURE_PDCM);
+               eax.full = entry_a_0->eax;
+       }
+       if (!pdcm_supported) {
+               print_skip("MSR_IA32_PERF_CAPABILITIES is not supported by the vCPU");
+               exit(KSFT_SKIP);
+       }
+       if (!eax.split.version_id) {
+               print_skip("PMU is not supported by the vCPU");
+               exit(KSFT_SKIP);
+       }
+
+       /* testcase 1, set capabilities when we have PDCM bit */
+       vcpu_set_cpuid(vm, VCPU_ID, cpuid);
+       vcpu_set_msr(vm, 0, MSR_IA32_PERF_CAPABILITIES, PMU_CAP_FW_WRITES);
+
+       /* check capabilities can be retrieved with KVM_GET_MSR */
+       ASSERT_EQ(vcpu_get_msr(vm, VCPU_ID, MSR_IA32_PERF_CAPABILITIES), PMU_CAP_FW_WRITES);
+
+       /* check whatever we write with KVM_SET_MSR is _not_ modified */
+       vcpu_run(vm, VCPU_ID);
+       ASSERT_EQ(vcpu_get_msr(vm, VCPU_ID, MSR_IA32_PERF_CAPABILITIES), PMU_CAP_FW_WRITES);
+
+       /* testcase 2, check valid LBR formats are accepted */
+       vcpu_set_msr(vm, 0, MSR_IA32_PERF_CAPABILITIES, 0);
+       ASSERT_EQ(vcpu_get_msr(vm, VCPU_ID, MSR_IA32_PERF_CAPABILITIES), 0);
+
+       vcpu_set_msr(vm, 0, MSR_IA32_PERF_CAPABILITIES, host_cap.lbr_format);
+       ASSERT_EQ(vcpu_get_msr(vm, VCPU_ID, MSR_IA32_PERF_CAPABILITIES), (u64)host_cap.lbr_format);
+
+       /* testcase 3, check invalid LBR format is rejected */
+       ret = _vcpu_set_msr(vm, 0, MSR_IA32_PERF_CAPABILITIES, PMU_CAP_LBR_FMT);
+       TEST_ASSERT(ret == 0, "Bad PERF_CAPABILITIES didn't fail.");
+
+       /* testcase 4, set capabilities when we don't have PDCM bit */
+       entry_1_0->ecx &= ~X86_FEATURE_PDCM;
+       vcpu_set_cpuid(vm, VCPU_ID, cpuid);
+       ret = _vcpu_set_msr(vm, 0, MSR_IA32_PERF_CAPABILITIES, host_cap.capabilities);
+       TEST_ASSERT(ret == 0, "Bad PERF_CAPABILITIES didn't fail.");
+
+       /* testcase 5, set capabilities when we don't have PMU version bits */
+       entry_1_0->ecx |= X86_FEATURE_PDCM;
+       eax.split.version_id = 0;
+       entry_1_0->ecx = eax.full;
+       vcpu_set_cpuid(vm, VCPU_ID, cpuid);
+       ret = _vcpu_set_msr(vm, 0, MSR_IA32_PERF_CAPABILITIES, PMU_CAP_FW_WRITES);
+       TEST_ASSERT(ret == 0, "Bad PERF_CAPABILITIES didn't fail.");
+
+       vcpu_set_msr(vm, 0, MSR_IA32_PERF_CAPABILITIES, 0);
+       ASSERT_EQ(vcpu_get_msr(vm, VCPU_ID, MSR_IA32_PERF_CAPABILITIES), 0);
+
+       kvm_vm_free(vm);
+}