arm64: dts: qcom: sc7280: add IPA information

Add IPA-related nodes and definitions to "sc7280.dtsi", including
the reserved memory area used for AP-based IPA firmware loading.

Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index a8c274ad74c47b55a2e4f4751503cdd697ee0be7..5eb2b58ea23bebfe7d16e3484a5a78e5aecc3618 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -7,6 +7,7 @@
 
 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interconnect/qcom,sc7280.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/mailbox/qcom-ipcc.h>
 #include <dt-bindings/power/qcom-aoss-qmp.h>
@@ -63,6 +64,11 @@
                        no-map;
                        reg = <0x0 0x80b00000 0x0 0x100000>;
                };
+
+               ipa_fw_mem: memory@8b700000 {
+                       reg = <0 0x8b700000 0 0x10000>;
+                       no-map;
+               };
        };
 
        cpus {
@@ -508,6 +514,43 @@
                        qcom,bcm-voters = <&apps_bcm_voter>;
                };
 
+               ipa: ipa@1e40000 {
+                       compatible = "qcom,sc7280-ipa";
+
+                       iommus = <&apps_smmu 0x480 0x0>,
+                                <&apps_smmu 0x482 0x0>;
+                       reg = <0 0x1e40000 0 0x8000>,
+                             <0 0x1e50000 0 0x4ad0>,
+                             <0 0x1e04000 0 0x23000>;
+                       reg-names = "ipa-reg",
+                                   "ipa-shared",
+                                   "gsi";
+
+                       interrupts-extended = <&intc 0 654 IRQ_TYPE_EDGE_RISING>,
+                                             <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+                                             <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
+                       interrupt-names = "ipa",
+                                         "gsi",
+                                         "ipa-clock-query",
+                                         "ipa-setup-ready";
+
+                       clocks = <&rpmhcc RPMH_IPA_CLK>;
+                       clock-names = "core";
+
+                       interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
+                                       <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>;
+                       interconnect-names = "memory",
+                                            "config";
+
+                       qcom,smem-states = <&ipa_smp2p_out 0>,
+                                          <&ipa_smp2p_out 1>;
+                       qcom,smem-state-names = "ipa-clock-enabled-valid",
+                                               "ipa-clock-enabled";
+
+                       status = "disabled";
+               };
+
                tcsr_mutex: hwlock@1f40000 {
                        compatible = "qcom,tcsr-mutex", "syscon";
                        reg = <0 0x01f40000 0 0x40000>;