PCI: cadence: Fix Gen2 Link Retraining process

BugLink: https://bugs.launchpad.net/bugs/2034469
[ Upstream commit 0e12f830236928b6fadf40d917a7527f0a048d2f ]

The Link Retraining process is initiated to account for the Gen2 defect in
the Cadence PCIe controller in J721E SoC. The errata corresponding to this
is i2085, documented at:
https://www.ti.com/lit/er/sprz455c/sprz455c.pdf

The existing workaround implemented for the errata waits for the Data Link
initialization to complete and assumes that the link retraining process
at the Physical Layer has completed. However, it is possible that the
Physical Layer training might be ongoing as indicated by the
PCI_EXP_LNKSTA_LT bit in the PCI_EXP_LNKSTA register.

Fix the existing workaround, to ensure that the Physical Layer training
has also completed, in addition to the Data Link initialization.

Link: https://lore.kernel.org/r/20230315070800.1615527-1-s-vadapalli@ti.com
Fixes: 4740b969aaf5 ("PCI: cadence: Retrain Link to work around Gen2 training defect")
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Signed-off-by: Kamal Mostafa <kamal@canonical.com>
Signed-off-by: Stefan Bader <stefan.bader@canonical.com>

diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
index 940c7dd701d689862084b6a1a1fb943f0493340b..5b14f7ee3c798ed8ad6b381ddac92b626c55b03d 100644 (file)
--- a/drivers/pci/controller/cadence/pcie-cadence-host.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
@@ -12,6 +12,8 @@
 
 #include "pcie-cadence.h"
 
+#define LINK_RETRAIN_TIMEOUT HZ
+
 static u64 bar_max_size[] = {
        [RP_BAR0] = _ULL(128 * SZ_2G),
        [RP_BAR1] = SZ_2G,
@@ -77,6 +79,27 @@ static struct pci_ops cdns_pcie_host_ops = {
        .write          = pci_generic_config_write,
 };
 
+static int cdns_pcie_host_training_complete(struct cdns_pcie *pcie)
+{
+       u32 pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET;
+       unsigned long end_jiffies;
+       u16 lnk_stat;
+
+       /* Wait for link training to complete. Exit after timeout. */
+       end_jiffies = jiffies + LINK_RETRAIN_TIMEOUT;
+       do {
+               lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA);
+               if (!(lnk_stat & PCI_EXP_LNKSTA_LT))
+                       break;
+               usleep_range(0, 1000);
+       } while (time_before(jiffies, end_jiffies));
+
+       if (!(lnk_stat & PCI_EXP_LNKSTA_LT))
+               return 0;
+
+       return -ETIMEDOUT;
+}
+
 static int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie)
 {
        struct device *dev = pcie->dev;
@@ -118,6 +141,10 @@ static int cdns_pcie_retrain(struct cdns_pcie *pcie)
                cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL,
                                    lnk_ctl);
 
+               ret = cdns_pcie_host_training_complete(pcie);
+               if (ret)
+                       return ret;
+
                ret = cdns_pcie_host_wait_for_link(pcie);
        }
        return ret;