drm/amdgpu: define convert_error_address for umc v8.7

So the code can be simplified.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v8_7.c b/drivers/gpu/drm/amd/amdgpu/umc_v8_7.c
index e2623685cb44f03a064ca08b43b459a1cdc1ffca..b717fdaa46e45281db06b6f273c5d56a72afe507 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/umc_v8_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v8_7.c
@@ -108,20 +108,35 @@ static void umc_v8_7_ecc_info_query_ras_error_count(struct amdgpu_device *adev,
        }
 }
 
+static void umc_v8_7_convert_error_address(struct amdgpu_device *adev,
+                                       struct ras_err_data *err_data, uint64_t err_addr,
+                                       uint32_t ch_inst, uint32_t umc_inst)
+{
+       uint64_t retired_page;
+       uint32_t channel_index;
+
+       channel_index =
+               adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst];
+
+       /* translate umc channel address to soc pa, 3 parts are included */
+       retired_page = ADDR_OF_4KB_BLOCK(err_addr) |
+                       ADDR_OF_256B_BLOCK(channel_index) |
+                       OFFSET_IN_256B_BLOCK(err_addr);
+
+       amdgpu_umc_fill_error_record(err_data, err_addr,
+                               retired_page, channel_index, umc_inst);
+}
+
 static void umc_v8_7_ecc_info_query_error_address(struct amdgpu_device *adev,
                                        struct ras_err_data *err_data,
                                        uint32_t ch_inst,
                                        uint32_t umc_inst)
 {
-       uint64_t mc_umc_status, err_addr, retired_page;
-       uint32_t channel_index;
+       uint64_t mc_umc_status, err_addr;
        uint32_t eccinfo_table_idx;
        struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 
        eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst;
-       channel_index =
-               adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst];
-
        mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status;
 
        if (mc_umc_status == 0)
@@ -137,13 +152,8 @@ static void umc_v8_7_ecc_info_query_error_address(struct amdgpu_device *adev,
                err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr;
                err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
 
-               /* translate umc channel address to soc pa, 3 parts are included */
-               retired_page = ADDR_OF_4KB_BLOCK(err_addr) |
-                               ADDR_OF_256B_BLOCK(channel_index) |
-                               OFFSET_IN_256B_BLOCK(err_addr);
-
-               amdgpu_umc_fill_error_record(err_data, err_addr,
-                                       retired_page, channel_index, umc_inst);
+               umc_v8_7_convert_error_address(adev, err_data, err_addr,
+                                               ch_inst, umc_inst);
        }
 }
 
@@ -320,14 +330,12 @@ static void umc_v8_7_query_error_address(struct amdgpu_device *adev,
                                         uint32_t umc_inst)
 {
        uint32_t lsb, mc_umc_status_addr;
-       uint64_t mc_umc_status, err_addr, retired_page, mc_umc_addrt0;
-       uint32_t channel_index = adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst];
+       uint64_t mc_umc_status, err_addr, mc_umc_addrt0;
 
        mc_umc_status_addr =
                SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
        mc_umc_addrt0 =
                SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_ADDRT0);
-
        mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4);
 
        if (mc_umc_status == 0)
@@ -349,13 +357,8 @@ static void umc_v8_7_query_error_address(struct amdgpu_device *adev,
                err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
                err_addr &= ~((0x1ULL << lsb) - 1);
 
-               /* translate umc channel address to soc pa, 3 parts are included */
-               retired_page = ADDR_OF_4KB_BLOCK(err_addr) |
-                               ADDR_OF_256B_BLOCK(channel_index) |
-                               OFFSET_IN_256B_BLOCK(err_addr);
-
-               amdgpu_umc_fill_error_record(err_data, err_addr,
-                                       retired_page, channel_index, umc_inst);
+               umc_v8_7_convert_error_address(adev, err_data, err_addr,
+                                                               ch_inst, umc_inst);
        }
 
        /* clear umc status */