int msi_host_irq;
int num_lanes;
+ u32 num_viewport;
struct phy **phy;
struct device_link **link;
struct device_node *msi_intc_np;
static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
{
u32 val;
+ u32 num_viewport = ks_pcie->num_viewport;
struct dw_pcie *pci = ks_pcie->pci;
struct pcie_port *pp = &pci->pp;
- u32 num_viewport = pci->num_viewport;
u64 start, end;
struct resource *mem;
int i;
struct resource *res;
unsigned int version;
void __iomem *base;
+ u32 num_viewport;
struct phy **phy;
u32 num_lanes;
char name[10];
goto err_get_sync;
}
+ ret = of_property_read_u32(np, "num-viewport", &num_viewport);
+ if (ret < 0) {
+ dev_err(dev, "unable to read *num-viewport* property\n");
+ goto err_get_sync;
+ }
+
/*
* "Power Sequencing and Reset Signal Timings" table in
* PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 2.0
gpiod_set_value_cansleep(gpiod, 1);
}
+ ks_pcie->num_viewport = num_viewport;
pci->pp.ops = host_ops;
ret = dw_pcie_host_init(&pci->pp);
if (ret < 0)