PCI: aardvark: Implement re-issuing config requests on CRS response

BugLink: https://bugs.launchpad.net/bugs/1956380
commit 223dec14a05337a4155f1deed46d2becce4d00fd upstream.

Commit 43f5c77bcbd2 ("PCI: aardvark: Fix reporting CRS value") fixed
handling of CRS response and when CRSSVE flag was not enabled it marked CRS
response as failed transaction (due to simplicity).

But pci-aardvark.c driver is already waiting up to the PIO_RETRY_CNT count
for PIO config response and so we can with a small change implement
re-issuing of config requests as described in PCIe base specification.

This change implements re-issuing of config requests when response is CRS.
Set upper bound of wait cycles to around PIO_RETRY_CNT, afterwards the
transaction is marked as failed and an all-ones value is returned as
before.

We do this by returning appropriate error codes from function
advk_pcie_check_pio_status(). On CRS we return -EAGAIN and caller then
reissues transaction.

Link: https://lore.kernel.org/r/20211005180952.6812-10-kabel@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Kamal Mostafa <kamal@canonical.com>
Signed-off-by: Stefan Bader <stefan.bader@canonical.com>

diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
index 47becbaf21038684e2fe7d3e79a90dad6d0db010..bd5d309232a99bd037395285f45d7cb44b32c93a 100644 (file)
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -666,6 +666,7 @@ static int advk_pcie_check_pio_status(struct advk_pcie *pcie, bool allow_crs, u3
        u32 reg;
        unsigned int status;
        char *strcomp_status, *str_posted;
+       int ret;
 
        reg = advk_readl(pcie, PIO_STAT);
        status = (reg & PIO_COMPLETION_STATUS_MASK) >>
@@ -690,6 +691,7 @@ static int advk_pcie_check_pio_status(struct advk_pcie *pcie, bool allow_crs, u3
        case PIO_COMPLETION_STATUS_OK:
                if (reg & PIO_ERR_STATUS) {
                        strcomp_status = "COMP_ERR";
+                       ret = -EFAULT;
                        break;
                }
                /* Get the read result */
@@ -697,9 +699,11 @@ static int advk_pcie_check_pio_status(struct advk_pcie *pcie, bool allow_crs, u3
                        *val = advk_readl(pcie, PIO_RD_DATA);
                /* No error */
                strcomp_status = NULL;
+               ret = 0;
                break;
        case PIO_COMPLETION_STATUS_UR:
                strcomp_status = "UR";
+               ret = -EOPNOTSUPP;
                break;
        case PIO_COMPLETION_STATUS_CRS:
                if (allow_crs && val) {
@@ -717,6 +721,7 @@ static int advk_pcie_check_pio_status(struct advk_pcie *pcie, bool allow_crs, u3
                         */
                        *val = CFG_RD_CRS_VAL;
                        strcomp_status = NULL;
+                       ret = 0;
                        break;
                }
                /* PCIe r4.0, sec 2.3.2, says:
@@ -732,21 +737,24 @@ static int advk_pcie_check_pio_status(struct advk_pcie *pcie, bool allow_crs, u3
                 * Request and taking appropriate action, e.g., complete the
                 * Request to the host as a failed transaction.
                 *
-                * To simplify implementation do not re-issue the Configuration
-                * Request and complete the Request as a failed transaction.
+                * So return -EAGAIN and caller (pci-aardvark.c driver) will
+                * re-issue request again up to the PIO_RETRY_CNT retries.
                 */
                strcomp_status = "CRS";
+               ret = -EAGAIN;
                break;
        case PIO_COMPLETION_STATUS_CA:
                strcomp_status = "CA";
+               ret = -ECANCELED;
                break;
        default:
                strcomp_status = "Unknown";
+               ret = -EINVAL;
                break;
        }
 
        if (!strcomp_status)
-               return 0;
+               return ret;
 
        if (reg & PIO_NON_POSTED_REQ)
                str_posted = "Non-posted";
@@ -756,7 +764,7 @@ static int advk_pcie_check_pio_status(struct advk_pcie *pcie, bool allow_crs, u3
        dev_dbg(dev, "%s PIO Response Status: %s, %#x @ %#x\n",
                str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS));
 
-       return -EFAULT;
+       return ret;
 }
 
 static int advk_pcie_wait_pio(struct advk_pcie *pcie)
@@ -764,13 +772,13 @@ static int advk_pcie_wait_pio(struct advk_pcie *pcie)
        struct device *dev = &pcie->pdev->dev;
        int i;
 
-       for (i = 0; i < PIO_RETRY_CNT; i++) {
+       for (i = 1; i <= PIO_RETRY_CNT; i++) {
                u32 start, isr;
 
                start = advk_readl(pcie, PIO_START);
                isr = advk_readl(pcie, PIO_ISR);
                if (!start && isr)
-                       return 0;
+                       return i;
                udelay(PIO_RETRY_DELAY);
        }
 
@@ -974,6 +982,7 @@ static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
                             int where, int size, u32 *val)
 {
        struct advk_pcie *pcie = bus->sysdata;
+       int retry_count;
        bool allow_crs;
        u32 reg;
        int ret;
@@ -1016,16 +1025,22 @@ static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
        /* Program the data strobe */
        advk_writel(pcie, 0xf, PIO_WR_DATA_STRB);
 
-       /* Clear PIO DONE ISR and start the transfer */
-       advk_writel(pcie, 1, PIO_ISR);
-       advk_writel(pcie, 1, PIO_START);
+       retry_count = 0;
+       do {
+               /* Clear PIO DONE ISR and start the transfer */
+               advk_writel(pcie, 1, PIO_ISR);
+               advk_writel(pcie, 1, PIO_START);
 
-       ret = advk_pcie_wait_pio(pcie);
-       if (ret < 0)
-               goto try_crs;
+               ret = advk_pcie_wait_pio(pcie);
+               if (ret < 0)
+                       goto try_crs;
+
+               retry_count += ret;
+
+               /* Check PIO status and get the read result */
+               ret = advk_pcie_check_pio_status(pcie, allow_crs, val);
+       } while (ret == -EAGAIN && retry_count < PIO_RETRY_CNT);
 
-       /* Check PIO status and get the read result */
-       ret = advk_pcie_check_pio_status(pcie, allow_crs, val);
        if (ret < 0)
                goto fail;
 
@@ -1057,6 +1072,7 @@ static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
        struct advk_pcie *pcie = bus->sysdata;
        u32 reg;
        u32 data_strobe = 0x0;
+       int retry_count;
        int offset;
        int ret;
 
@@ -1098,19 +1114,22 @@ static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
        /* Program the data strobe */
        advk_writel(pcie, data_strobe, PIO_WR_DATA_STRB);
 
-       /* Clear PIO DONE ISR and start the transfer */
-       advk_writel(pcie, 1, PIO_ISR);
-       advk_writel(pcie, 1, PIO_START);
+       retry_count = 0;
+       do {
+               /* Clear PIO DONE ISR and start the transfer */
+               advk_writel(pcie, 1, PIO_ISR);
+               advk_writel(pcie, 1, PIO_START);
 
-       ret = advk_pcie_wait_pio(pcie);
-       if (ret < 0)
-               return PCIBIOS_SET_FAILED;
+               ret = advk_pcie_wait_pio(pcie);
+               if (ret < 0)
+                       return PCIBIOS_SET_FAILED;
 
-       ret = advk_pcie_check_pio_status(pcie, false, NULL);
-       if (ret < 0)
-               return PCIBIOS_SET_FAILED;
+               retry_count += ret;
 
-       return PCIBIOS_SUCCESSFUL;
+               ret = advk_pcie_check_pio_status(pcie, false, NULL);
+       } while (ret == -EAGAIN && retry_count < PIO_RETRY_CNT);
+
+       return ret < 0 ? PCIBIOS_SET_FAILED : PCIBIOS_SUCCESSFUL;
 }
 
 static struct pci_ops advk_pcie_ops = {