ARM: dts: stm32: Add DHSOM based DRC02 board

Add DT for DH DRC02 unit, which is a universal controller device.
The system has two ethernet ports, two CANs, RS485 and RS232, USB,
capacitive buttons and an OLED display.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 4572db3fa5ae3029d589789c3afb0da4a46713a2..8cdcf7316ca264db9f3030b58a45afe4a9675704 100644 (file)
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1047,6 +1047,7 @@ dtb-$(CONFIG_ARCH_STM32) += \
        stm32746g-eval.dtb \
        stm32h743i-eval.dtb \
        stm32h743i-disco.dtb \
+       stm32mp153c-dhcom-drc02.dtb \
        stm32mp157a-avenger96.dtb \
        stm32mp157a-dhcor-avenger96.dtb \
        stm32mp157a-dk1.dtb \

diff --git a/arch/arm/boot/dts/stm32mp153c-dhcom-drc02.dts b/arch/arm/boot/dts/stm32mp153c-dhcom-drc02.dts
new file mode 100644 (file)
index 0000000..02a3913
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp153c-dhcom-drc02.dts
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2020 Marek Vasut <marex@denx.de>
+ *
+ * DHCOM STM32MP1 variant:
+ * DHCM-STM32MP153C-C065-R102-F0819-SPI-E2-CAN2-RTC-I-01D2
+ * DHCOM PCB number: 587-200 or newer
+ * DRC02 PCB number: 568-100 or newer
+ */
+/dts-v1/;
+
+#include "stm32mp153.dtsi"
+#include "stm32mp15xc.dtsi"
+#include "stm32mp15xx-dhcom-som.dtsi"
+#include "stm32mp15xx-dhcom-drc02.dtsi"
+
+/ {
+       model = "DH electronics STM32MP153C DHCOM DRC02";
+       compatible = "dh,stm32mp153c-dhcom-drc02", "dh,stm32mp153c-dhcom-som",
+                    "st,stm32mp153";
+};
+
+&m_can1 {
+       pinctrl-names = "default", "sleep";
+       pinctrl-0 = <&m_can1_pins_a>;
+       pinctrl-1 = <&m_can1_sleep_pins_a>;
+       status = "okay";
+};
+
+&m_can2 {
+       pinctrl-names = "default", "sleep";
+       pinctrl-0 = <&m_can2_pins_a>;
+       pinctrl-1 = <&m_can2_sleep_pins_a>;
+       status = "okay";
+};

diff --git a/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts b/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts
index 197aa98d49e2b90970e428156ddaa25d629d47c8..d3b81382f97c3e2d8d330edef8e2a614d9bcae63 100644 (file)
--- a/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts
+++ b/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts
@@ -4,7 +4,7 @@
  *
  * DHCOM STM32MP1 variant:
  * DHCM-STM32MP157C-C065-R102-F0819-SPI-E2-CAN2-SDR104-RTC-WBT-T-DSI-I-01D2
- * DHCOR PCB number: 587-200 or newer
+ * DHCOM PCB number: 587-200 or newer
  * PDK2 PCB number: 516-400 or newer
  */
 /dts-v1/;
@@ -15,7 +15,7 @@
 #include "stm32mp15xx-dhcom-pdk2.dtsi"
 
 / {
-       model = "DH Electronics STM32MP157C DHCOM Premium Developer Kit (2)";
+       model = "DH electronics STM32MP157C DHCOM Premium Developer Kit (2)";
        compatible = "dh,stm32mp157c-dhcom-pdk2", "dh,stm32mp157c-dhcom-som",
                     "st,stm32mp157";
 };

diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi
new file mode 100644 (file)
index 0000000..62ab238
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2020 Marek Vasut <marex@denx.de>
+ */
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+       aliases {
+               serial0 = &uart4;
+               serial1 = &usart3;
+               serial2 = &uart8;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+};
+
+&adc {
+       status = "disabled";
+};
+
+&dac {
+       status = "disabled";
+};
+
+&gpiob {
+       /*
+        * NOTE: On DRC02, the RS485_RX_En is controlled by a separate
+        * GPIO line, however the STM32 UART driver assumes RX happens
+        * during TX anyway and that it only controls drive enable DE
+        * line. Hence, the RX is always enabled here.
+        */
+       rs485-rx-en {
+               gpio-hog;
+               gpios = <8 GPIO_ACTIVE_HIGH>;
+               output-low;
+               line-name = "rs485-rx-en";
+       };
+};
+
+&gpiod {
+       gpio-line-names = "", "", "", "",
+                         "", "", "", "",
+                         "", "", "", "Out1",
+                         "Out2", "", "", "";
+};
+
+&gpioi {
+       gpio-line-names = "In1", "", "", "",
+                         "", "", "", "",
+                         "In2", "", "", "",
+                         "", "", "", "";
+
+       /*
+        * NOTE: The USB Hub on the DRC02 needs a reset signal to be
+        * pulled high in order to be detected by the USB Controller.
+        * This signal should be handled by USB power sequencing in
+        * order to reset the Hub when USB bus is powered down, but
+        * so far there is no such functionality.
+        */
+       usb-hub {
+               gpio-hog;
+               gpios = <2 GPIO_ACTIVE_HIGH>;
+               output-high;
+               line-name = "usb-hub-reset";
+       };
+};
+
+&i2c2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&i2c2_pins_a>;
+       i2c-scl-rising-time-ns = <185>;
+       i2c-scl-falling-time-ns = <20>;
+       status = "okay";
+       /* spare dmas for other usage */
+       /delete-property/dmas;
+       /delete-property/dma-names;
+       status = "okay";
+
+       eeprom@50 {
+               compatible = "atmel,24c04";
+               reg = <0x50>;
+               pagesize = <16>;
+       };
+};
+
+&i2c5 {        /* TP7/TP8 */
+       pinctrl-names = "default";
+       pinctrl-0 = <&i2c5_pins_a>;
+       i2c-scl-rising-time-ns = <185>;
+       i2c-scl-falling-time-ns = <20>;
+       status = "okay";
+       /* spare dmas for other usage */
+       /delete-property/dmas;
+       /delete-property/dma-names;
+};
+
+&sdmmc3 {
+       /*
+        * On DRC02, the SoM does not have SDIO WiFi. The pins
+        * are used for on-board microSD slot instead.
+        */
+       /delete-property/broken-cd;
+       cd-gpios = <&gpioi 10 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+       disable-wp;
+};
+
+&spi1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&spi1_pins_a>;
+       cs-gpios = <&gpioz 3 0>;
+       /* Use PIO for the display */
+       /delete-property/dmas;
+       /delete-property/dma-names;
+       status = "disabled";    /* Enable once there is display driver */
+       /*
+        * Note: PF3/GPIO_A , PD6/GPIO_B , PG0/GPIO_C , PC6/GPIO_E are
+        * also connected to the display board connector.
+        */
+};
+
+&usart3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&usart3_pins_a>;
+       status = "okay";
+};
+
+/*
+ * Note: PI3 is UART1_RTS and PI5 is UART1_CTS on DRC02 (uart4 of STM32MP1),
+ *       however the STM32MP1 pinmux cannot map them to UART4 .
+ */
+
+&uart8 {       /* RS485 */
+       linux,rs485-enabled-at-boot-time;
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart8_pins_a>;
+       rts-gpios = <&gpioe 6 GPIO_ACTIVE_HIGH>;
+       status = "okay";
+};
+
+&usbh_ehci {
+       phys = <&usbphyc_port0>;
+       status = "okay";
+};
+
+&usbphyc {
+       status = "okay";
+};
+
+&usbphyc_port0 {
+       phy-supply = <&vdd_usb>;
+       vdda1v1-supply = <&reg11>;
+       vdda1v8-supply = <&reg18>;
+};