static inline void check_cp0_enabled(DisasContext *ctx)
{
- if (!(ctx->hflags & MIPS_HFLAG_CP0))
+ if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0)))
generate_exception_err(ctx, EXCP_CpU, 1);
}
static inline void check_cp1_enabled(DisasContext *ctx)
{
- if (!(ctx->hflags & MIPS_HFLAG_FPU))
+ if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU)))
generate_exception_err(ctx, EXCP_CpU, 1);
}
static inline void check_cp1_64bitmode(DisasContext *ctx)
{
- if (!(ctx->hflags & MIPS_HFLAG_F64))
+ if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64)))
generate_exception(ctx, EXCP_RI);
}
*/
void check_cp1_registers(DisasContext *ctx, int regs)
{
- if (!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))
+ if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1)))
generate_exception(ctx, EXCP_RI);
}
CPU is not MIPS MT capable. */
static inline void check_mips_mt(CPUState *env, DisasContext *ctx)
{
- if (!(env->CP0_Config3 & (1 << CP0C3_MT)))
+ if (unlikely(!(env->CP0_Config3 & (1 << CP0C3_MT))))
generate_exception(ctx, EXCP_RI);
}
instructions are not enabled. */
static inline void check_mips_64(DisasContext *ctx)
{
- if (!(ctx->hflags & MIPS_HFLAG_64))
+ if (unlikely(!(ctx->hflags & MIPS_HFLAG_64)))
generate_exception(ctx, EXCP_RI);
}