drm/amd/display: Trivial swizzle-related code clean-ups

This is a very trivial code clean-up related to commit 5468c36d6285
("drm/amd/display: Filter Invalid 420 Modes for HDMI TMDS"). This commit
added a validation on driver probe to prevent invalid TMDS modes, but one
of the fake properties (swizzle) ended-up causing a warning on driver
probe; was reported here: https://gitlab.freedesktop.org/drm/amd/-/issues/2264.

It was fixed by commit a1cbe6916f44 ("drm/amd/display: patch cases with
unknown plane state to prevent warning"), but the validation code had
a double variable assignment, which we hereby remove. Also, the fix relies
in the dcn2{0,1}patch_unknown_plane_state() callbacks, so while at it we
took the opportunity to perform a small code clean-up in such routines.

Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Cc: Daniel Wheeler <daniel.wheeler@amd.com>
Cc: Fangzhi Zuo <Jerry.Zuo@amd.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Leo Li <sunpeng.li@amd.com>
Cc: Mark Broadworth <mark.broadworth@amd.com>
Cc: Melissa Wen <mwen@igalia.com>
Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Cc: Sung Joon Kim <Sungjoon.Kim@amd.com>
Cc: Swapnil Patel <Swapnil.Patel@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Guilherme G. Piccoli <gpiccoli@igalia.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 39bc8fd33cce588c9699d5c59c4a5584621c0c39..2096ad00a2dedd2cde727689aaa26b85eb11afaa 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6365,7 +6365,6 @@ static enum dc_status dm_validate_stream_and_context(struct dc *dc,
        dc_plane_state->plane_size.surface_size.width  = stream->src.width;
        dc_plane_state->plane_size.chroma_size.height  = stream->src.height;
        dc_plane_state->plane_size.chroma_size.width   = stream->src.width;
-       dc_plane_state->tiling_info.gfx9.swizzle =  DC_SW_UNKNOWN;
        dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
        dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;
        dc_plane_state->rotation = ROTATION_ANGLE_0;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 531f405d255443af1819fada7c6d9e89055af4f7..3af24ef9cb2de9db9b499afccce844a12c059e94 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2225,14 +2225,10 @@ enum dc_status dcn20_patch_unknown_plane_state(struct dc_plane_state *plane_stat
        enum surface_pixel_format surf_pix_format = plane_state->format;
        unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);
 
-       enum swizzle_mode_values swizzle = DC_SW_LINEAR;
-
+       plane_state->tiling_info.gfx9.swizzle = DC_SW_64KB_S;
        if (bpp == 64)
-               swizzle = DC_SW_64KB_D;
-       else
-               swizzle = DC_SW_64KB_S;
+               plane_state->tiling_info.gfx9.swizzle = DC_SW_64KB_D;
 
-       plane_state->tiling_info.gfx9.swizzle = swizzle;
        return DC_OK;
 }
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index fbcf0afeae0db9d430d23394b96cd36066016fd9..8f9244fe5c8682ecbacf1a6aa9e1d1ed01cda9ae 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -1393,15 +1393,13 @@ static uint32_t read_pipe_fuses(struct dc_context *ctx)
 
 static enum dc_status dcn21_patch_unknown_plane_state(struct dc_plane_state *plane_state)
 {
-       enum dc_status result = DC_OK;
-
        if (plane_state->ctx->dc->debug.disable_dcc == DCC_ENABLE) {
                plane_state->dcc.enable = 1;
                /* align to our worst case block width */
                plane_state->dcc.meta_pitch = ((plane_state->src_rect.width + 1023) / 1024) * 1024;
        }
-       result = dcn20_patch_unknown_plane_state(plane_state);
-       return result;
+
+       return dcn20_patch_unknown_plane_state(plane_state);
 }
 
 static const struct resource_funcs dcn21_res_pool_funcs = {