Fix typos in comments (interupt -> interrupt)

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>

diff --git a/cpu-exec.c b/cpu-exec.c
index 395cd8cf9047bc1eec16290ffbb638afe251a0ea..2cdcdc5e76458b88dd4c1c9f91aa3dc3dd18f6f0 100644 (file)
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -569,7 +569,7 @@ int cpu_exec(CPUState *env1)
                         next_tb = 0;
                     }
 #endif
-                   /* Don't use the cached interupt_request value,
+                   /* Don't use the cached interrupt_request value,
                       do_interrupt may have updated the EXITTB flag. */
                     if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
                         env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;

diff --git a/hw/mst_fpga.c b/hw/mst_fpga.c
index a04355cc7fe4256e77d983ef3698afc05f140cbf..4e47574b63162181fe0c3490963b7a23ba73e346 100644 (file)
--- a/hw/mst_fpga.c
+++ b/hw/mst_fpga.c
@@ -154,7 +154,7 @@ mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
        case MST_MSCRD:
                s->mscrd =  value;
                break;
-       case MST_INTMSKENA:     /* Mask interupt */
+       case MST_INTMSKENA:     /* Mask interrupt */
                s->intmskena = (value & 0xFEEFF);
                qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
                break;

diff --git a/hw/pl031.c b/hw/pl031.c
index 8c2f9d0bc7f885f6745ae82a65a5eb56e47026a3..017a313fdab30f1db83dfa142a24fab1ee92d71c 100644 (file)
--- a/hw/pl031.c
+++ b/hw/pl031.c
@@ -161,7 +161,7 @@ static void pl031_write(void * opaque, target_phys_addr_t offset,
         pl031_update(s);
         break;
     case RTC_ICR:
-        /* The PL031 documentation (DDI0224B) states that the interupt is
+        /* The PL031 documentation (DDI0224B) states that the interrupt is
            cleared when bit 0 of the written value is set.  However the
            arm926e documentation (DDI0287B) states that the interrupt is
            cleared when any value is written.  */

diff --git a/hw/pl061.c b/hw/pl061.c
index 2e181f8c2fe666b1b4da7268f376e39e546ccc08..372dfc2da2676868a0a7dd284573798bb5082d6e 100644 (file)
--- a/hw/pl061.c
+++ b/hw/pl061.c
@@ -98,7 +98,7 @@ static uint32_t pl061_read(void *opaque, target_phys_addr_t offset)
         return s->isense;
     case 0x408: /* Interrupt both edges */
         return s->ibe;
-    case 0x40c: /* Interupt event */
+    case 0x40c: /* Interrupt event */
         return s->iev;
     case 0x410: /* Interrupt mask */
         return s->im;
@@ -156,7 +156,7 @@ static void pl061_write(void *opaque, target_phys_addr_t offset,
     case 0x408: /* Interrupt both edges */
         s->ibe = value;
         break;
-    case 0x40c: /* Interupt event */
+    case 0x40c: /* Interrupt event */
         s->iev = value;
         break;
     case 0x410: /* Interrupt mask */

diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 8d9b5b9c491652a7adc12ae5d9088799dc28686b..d55c522bf3b692664df452b8ebcc610d7f497c60 100644 (file)
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -38,7 +38,7 @@
 ((1 << CP0C2_M))
 
 /* No config4, no DSP ASE, no large physaddr (PABITS),
-   no external interrupt controller, no vectored interupts,
+   no external interrupt controller, no vectored interrupts,
    no 1kb pages, no SmartMIPS ASE, no trace logic */
 #define MIPS_CONFIG3                                              \
 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) |          \