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target/riscv: Extract virt enabled state from tb flags
[mirror_qemu.git] / target / riscv / cpu.c
2023-05-05 Weiwei Litarget/riscv: Use check for relationship between Zdinx...
2023-05-05 Daniel Henrique... target/riscv/cpu.c: redesign register_cpu_props()
2023-05-05 Daniel Henrique... target/riscv: add RVG and remove cpu->cfg.ext_g
2023-05-05 Daniel Henrique... target/riscv: remove cfg.ext_g setup from rv64_thead_c9...
2023-05-05 Daniel Henrique... target/riscv: remove riscv_cpu_sync_misa_cfg()
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_v
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_j
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_h
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_u
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_s
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_m
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_e
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_i
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_f
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_d
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_c
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_a
2023-05-05 Daniel Henrique... target/riscv: introduce riscv_cpu_add_misa_properties()
2023-05-05 Daniel Henrique... target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data
2023-05-05 Daniel Henrique... target/riscv: remove MISA properties from isa_edata_arr[]
2023-05-05 Daniel Henrique... target/riscv: sync env->misa_ext* with cpu->cfg in...
2023-05-05 Weiwei Litarget/riscv: Fix lines with over 80 characters
2023-05-05 Weiwei Litarget/riscv: Fix format for comments
2023-05-05 Weiwei Litarget/riscv: Fix format for indentation
2023-05-05 Weiwei Litarget/riscv: Remove riscv_cpu_virt_enabled()
2023-05-05 Weiwei Litarget/riscv: Add support for Zce
2023-05-05 Weiwei Litarget/riscv: expose properties for Zc* extension
2023-05-05 Weiwei Litarget/riscv: add cfg properties for Zc* extension
2023-05-05 Weiwei Litarget/riscv: Simplify type conversion for CPURISCVState
2023-05-05 LIU Zhiweitarget/riscv: Fix priv version dependency for vector...
2023-03-12 Peter MaydellMerge tag 'linux-user-for-8.0-pull-request' of https...
2023-03-10 Peter MaydellMerge tag 'pull-hex-20230306' of https://github.com...
2023-03-09 Peter MaydellMerge tag 'vfio-updates-20230307.1' of https://gitlab...
2023-03-09 Peter MaydellMerge tag 'pull-request-2023-03-07' of https://gitlab...
2023-03-09 Peter MaydellMerge tag 'pull-aspeed-20230307' of https://github...
2023-03-07 Peter MaydellMerge tag 'for-upstream-mb' of https://gitlab.com/bonzi...
2023-03-07 Peter MaydellMerge tag 'pull-riscv-to-apply-20230306' of https:...
2023-03-06 Alexandre Ghitiriscv: Introduce satp mode hw capabilities
2023-03-06 Alexandre Ghitiriscv: Allow user to set the satp mode
2023-03-06 Alexandre Ghitiriscv: Pass Object to register_cpu_props instead of...
2023-03-05 Mayuresh Chitaletarget/riscv: cpu: Implement get_arch_id callback
2023-03-05 Christoph Muellnertarget/riscv: implement Zicbom extension
2023-03-05 Christoph Muellnertarget/riscv: implement Zicboz extension
2023-03-03 Peter MaydellMerge tag 'pull-aspeed-20230302' of https://github...
2023-03-03 Peter MaydellMerge tag 'pull-loongarch-20230303' of https://gitlab...
2023-03-03 Peter MaydellMerge tag 'migration-20230302-pull-request' of https...
2023-03-03 Peter MaydellMerge tag 'for_upstream' of https://git.kernel.org...
2023-03-03 Peter MaydellMerge tag 'pull-riscv-to-apply-20230303' of https:...
2023-03-02 Peter MaydellMerge tag 'for-upstream' of https://gitlab.com/bonzini...
2023-03-02 Peter MaydellMerge tag 'pull-testing-next-010323-1' of https://gitla...
2023-03-02 Peter MaydellMerge tag 'pull-monitor-2023-03-02' of https://repo...
2023-03-02 Peter MaydellMerge tag 'bsd-user-2023q1-pull-request' of gitlab...
2023-03-02 Palmer DabbeltMerge patch series "target/riscv: some vector_helper...
2023-03-02 Palmer DabbeltMerge patch series "RISCVCPUConfig related cleanups"
2023-03-02 Palmer DabbeltMerge patch series "target/riscv: Add support for Svadu...
2023-03-02 Weiwei Litarget/riscv: Export Svadu property
2023-03-02 Weiwei Litarget/riscv: Add *envcfg.HADE related check in address...
2023-03-02 Weiwei Litarget/riscv: Add *envcfg.PBMTE related check in addres...
2023-03-02 Weiwei Litarget/riscv: Add support for Zicond extension
2023-03-02 Palmer DabbeltMerge patch series "target/riscv: Various fixes to...
2023-03-01 Palmer DabbeltMerge patch series "target/riscv: Some updates to float...
2023-03-01 Palmer DabbeltMerge patch series "make write_misa a no-op and FEATURE...
2023-03-01 Weiwei Litarget/riscv: Expose properties for Zv* extensions
2023-03-01 Weiwei Litarget/riscv: Indent fixes in cpu.c
2023-03-01 Weiwei Litarget/riscv: Add property check for Zvfh{min} extensions
2023-03-01 Weiwei Litarget/riscv: Fix relationship between V, Zve*, F and D
2023-03-01 Weiwei Litarget/riscv: Fix the relationship between Zhinxmin...
2023-03-01 Weiwei Litarget/riscv: Fix the relationship between Zfhmin and Zfh
2023-03-01 Daniel Henrique... target/riscv: remove RISCV_FEATURE_MMU
2023-03-01 Daniel Henrique... target/riscv: remove RISCV_FEATURE_PMP
2023-03-01 Daniel Henrique... target/riscv: remove RISCV_FEATURE_EPMP
2023-03-01 Daniel Henrique... target/riscv/cpu.c: error out if EPMP is enabled withou...
2023-03-01 Daniel Henrique... target/riscv: remove RISCV_FEATURE_DEBUG
2023-03-01 Daniel Henrique... target/riscv: allow MISA writes as experimental
2023-03-01 Peter MaydellMerge tag 'pull-tcg-20230301' of https://gitlab.com...
2023-03-01 Anton Johanssontarget/riscv: Replace `tb_pc()` with `tb->pc`
2023-02-27 Peter MaydellMerge tag 'for-upstream-8.0' of https://gitlab.com...
2023-02-27 Peter MaydellMerge tag 'pull-request-2023-02-27' of https://gitlab...
2023-02-26 Peter MaydellMerge tag 'pull-riscv-to-apply-20230224' of github...
2023-02-23 Frank Changtarget/riscv: Remove privileged spec version restrictio...
2023-02-07 Peter MaydellMerge tag 'for-upstream-py38' of https://gitlab.com...
2023-02-07 Peter MaydellMerge tag 'pull-aspeed-20230207' of https://github...
2023-02-07 Peter MaydellMerge tag 'pull-riscv-to-apply-20230207' of https:...
2023-02-06 Christoph MüllnerRISC-V: Adding XTheadFmv ISA extension
2023-02-06 Christoph MüllnerRISC-V: Add initial support for T-Head C906
2023-02-06 Christoph MüllnerRISC-V: Set minimum priv version for Zfh to 1.11
2023-02-06 Christoph MüllnerRISC-V: Adding T-Head FMemIdx extension
2023-02-06 Christoph MüllnerRISC-V: Adding T-Head MemIdx extension
2023-02-06 Christoph MüllnerRISC-V: Adding T-Head MemPair extension
2023-02-06 Christoph MüllnerRISC-V: Adding T-Head multiply-accumulate instructions
2023-02-06 Christoph MüllnerRISC-V: Adding XTheadCondMov ISA extension
2023-02-06 Christoph MüllnerRISC-V: Adding XTheadBs ISA extension
2023-02-06 Christoph MüllnerRISC-V: Adding XTheadBb ISA extension
2023-02-06 Christoph MüllnerRISC-V: Adding XTheadBa ISA extension
2023-02-06 Christoph MüllnerRISC-V: Adding XTheadSync ISA extension
2023-02-06 Christoph MüllnerRISC-V: Adding XTheadCmo ISA extension
2023-01-20 Peter MaydellMerge tag 'pull-riscv-to-apply-20230120' of https:...
2023-01-20 Bin Mengtarget/riscv: Use TARGET_FMT_lx for env->mhartid
2023-01-20 Daniel Henrique... target/riscv/cpu.c: do not skip misa logic in riscv_cpu...
2023-01-20 Daniel Henrique... target/riscv/cpu: set cpu->cfg in register_cpu_props()
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