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target/*: Add instance_align to all cpu base classes
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2023-10-03 Richard Hendersontarget/*: Add instance_align to all cpu base classes
2023-10-03 Stefan HajnocziMerge tag 'for-upstream' of https://gitlab.com/bonzini...
2023-10-02 Stefan HajnocziMerge tag 'migration-20231002-pull-request' of https...
2023-10-02 Stefan HajnocziMerge tag 'pull-shadow-2023-09-29' of https://repo...
2023-09-29 Alistair Francistarget/riscv: cpu: Fixup local variables shadowing
2023-09-21 Stefan HajnocziMerge tag 'pull-block-2023-09-01' of https://gitlab...
2023-09-19 Stefan HajnocziMerge tag 'firmware/edk2-20230918-pull-request' of...
2023-09-11 Stefan HajnocziMerge tag 'pull-vfio-20230911' of https://github.com...
2023-09-11 Stefan HajnocziMerge tag 'pull-riscv-to-apply-20230911' of https:...
2023-09-11 Akihiko Odakitarget/riscv: Allocate itrigger timers only once
2023-09-11 Vineet Guptariscv: zicond: make non-experimental
2023-09-11 Daniel Henrique... target/riscv: fix satp_mode_finalize() when satp_mode...
2023-09-11 Weiwei Litarget/riscv: Update CSR bits name for svadu extension
2023-09-11 Jason Chientarget/riscv: Add Zihintntl extension ISA string to DTS
2023-09-11 Max Choutarget/riscv: Add Zvksed ISA extension support
2023-09-11 Nazar Kazakovtarget/riscv: Add Zvkg ISA extension support
2023-09-11 Lawrence Huntertarget/riscv: Add Zvksh ISA extension support
2023-09-11 Kiran Ostrolenktarget/riscv: Add Zvknh ISA extension support
2023-09-11 Nazar Kazakovtarget/riscv: Add Zvkned ISA extension support
2023-09-11 Dickon Hoodtarget/riscv: Add Zvbb ISA extension support
2023-09-11 Lawrence Huntertarget/riscv: Add Zvbc ISA extension support
2023-09-11 Daniel Henrique... target/riscv/cpu.c: add smepmp isa string
2023-09-11 Daniel Henrique... target/riscv/cpu.c: add zmmul isa string
2023-09-11 Daniel Henrique... target/riscv/cpu.c: do not run 'host' CPU with TCG
2023-07-28 Richard HendersonMerge tag 'block-pull-request' of https://gitlab.com...
2023-07-24 Peter MaydellMerge tag 'pull-qapi-2023-07-10' of https://repo.or...
2023-07-20 Peter MaydellMerge tag 'linux-user-brk-fixes-pull-request' of https...
2023-07-19 Peter MaydellMerge tag 'pull-riscv-to-apply-20230719-1' of https...
2023-07-19 Daniel Henrique... target/riscv/cpu.c: check priv_ver before auto-enable...
2023-07-11 Richard HendersonMerge tag 'for_upstream' of https://git.kernel.org...
2023-07-11 Richard HendersonMerge tag 'mips-20230710' of https://github.com/philmd...
2023-07-10 Richard HendersonMerge tag 'qga-pull-2023-07-10' of https://github.com...
2023-07-10 Richard HendersonMerge tag 'pull-riscv-to-apply-20230710-1' of https...
2023-07-10 Christoph Müllnerriscv: Add support for the Zfa extension
2023-07-10 Daniel Henrique... target/riscv/cpu.c: create KVM mock properties
2023-07-10 Daniel Henrique... target/riscv/cpu.c: remove priv_ver check from riscv_is...
2023-07-10 Daniel Henrique... target/riscv/cpu.c: add satp_mode properties earlier
2023-07-10 Daniel Henrique... target/riscv/kvm.c: add multi-letter extension KVM...
2023-07-10 Daniel Henrique... target/riscv: add KVM specific MISA properties
2023-07-10 Daniel Henrique... target/riscv/cpu: add misa_ext_info_arr[]
2023-07-10 Daniel Henrique... target/riscv: use KVM scratch CPUs to init KVM properties
2023-07-10 Daniel Henrique... target/riscv/cpu.c: restrict 'marchid' value
2023-07-10 Daniel Henrique... target/riscv/cpu.c: restrict 'mimpid' value
2023-07-10 Daniel Henrique... target/riscv/cpu.c: restrict 'mvendorid' value
2023-07-10 Daniel Henrique... target/riscv: skip features setup for KVM CPUs
2023-07-10 Weiwei Litarget/riscv: Expose properties for BF16 extensions
2023-07-10 Weiwei Litarget/riscv: Add properties for BF16 extensions
2023-07-10 Ivan Klokovtarget/riscv: Add RVV registers to log
2023-07-10 Daniel Henrique... target/riscv/cpu.c: fix veyron-v1 CPU properties
2023-07-10 LIU Zhiweitarget/riscv: Use xl instead of mxl for disassemble
2023-06-30 Richard HendersonMerge tag 'pull-request-2023-06-29' of https://gitlab...
2023-06-29 Richard HendersonMerge tag 'for-upstream' of https://gitlab.com/bonzini...
2023-06-29 Richard HendersonMerge tag 'accel-20230628' of https://github.com/philmd...
2023-06-28 Philippe Mathieu... target/riscv: Restrict KVM-specific fields from ArchCPU
2023-06-21 Richard HendersonMerge tag 'seabios-hppa-v7-pull-request' of https:...
2023-06-14 Richard HendersonMerge tag 'pull-riscv-to-apply-20230614' of https:...
2023-06-13 Weiwei Litarget/riscv: Enable PC-relative translation
2023-06-13 Weiwei Litarget/riscv: Pass RISCVCPUConfig as target_info to...
2023-06-13 Mayuresh Chitaletarget/riscv: smstateen knobs
2023-06-13 Daniel Henrique... target/riscv: rework write_misa()
2023-06-13 Daniel Henrique... target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()
2023-06-13 Daniel Henrique... target/riscv/cpu.c: validate extensions before riscv_ti...
2023-06-13 Daniel Henrique... target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl()
2023-06-13 Daniel Henrique... target/riscv/cpu.c: add priv_spec validate/disable_exts...
2023-06-13 Weiwei Litarget/riscv: Mask the implicitly enabled extensions...
2023-06-13 Daniel Henrique... target/riscv: add PRIV_VERSION_LATEST
2023-06-13 Daniel Henrique... target/riscv/cpu.c: remove set_priv_version()
2023-06-13 Daniel Henrique... target/riscv/cpu.c: remove set_vext_version()
2023-06-13 Daniel Henrique... target/riscv/cpu.c: add riscv_cpu_validate_v()
2023-06-13 Weiwei Litarget/riscv: Move zc* out of the experimental properties
2023-05-17 Richard HendersonMerge tag 'linux-user-for-8.1-pull-request' of https...
2023-05-13 Richard HendersonMerge tag 'or1k-pull-request-20230513' of https://githu...
2023-05-05 Richard HendersonMerge tag 'pw-pull-request' of https://gitlab.com/marca...
2023-05-05 Richard HendersonMerge tag 'migration-20230505-pull-request' of https...
2023-05-05 Richard HendersonMerge tag 'pull-riscv-to-apply-20230505-1' of https...
2023-05-05 Rahul Pathaktarget/riscv: add Ventana's Veyron V1 CPU
2023-05-05 Daniel Henrique... target/riscv: add TYPE_RISCV_DYNAMIC_CPU
2023-05-05 LIU Zhiweitarget/riscv: Add a general status enum for extensions
2023-05-05 Weiwei Litarget/riscv: Use check for relationship between Zdinx...
2023-05-05 Daniel Henrique... target/riscv/cpu.c: redesign register_cpu_props()
2023-05-05 Daniel Henrique... target/riscv: add RVG and remove cpu->cfg.ext_g
2023-05-05 Daniel Henrique... target/riscv: remove cfg.ext_g setup from rv64_thead_c9...
2023-05-05 Daniel Henrique... target/riscv: remove riscv_cpu_sync_misa_cfg()
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_v
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_j
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_h
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_u
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_s
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_m
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_e
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_i
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_f
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_d
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_c
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_a
2023-05-05 Daniel Henrique... target/riscv: introduce riscv_cpu_add_misa_properties()
2023-05-05 Daniel Henrique... target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data
2023-05-05 Daniel Henrique... target/riscv: remove MISA properties from isa_edata_arr[]
2023-05-05 Daniel Henrique... target/riscv: sync env->misa_ext* with cpu->cfg in...
2023-05-05 Weiwei Litarget/riscv: Fix lines with over 80 characters
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