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target/riscv: Reduce overhead of MSTATUS_SUM change
[mirror_qemu.git] / target / riscv / cpu.h
2023-05-05 Fei Wutarget/riscv: Reduce overhead of MSTATUS_SUM change
2023-05-05 Fei Wutarget/riscv: Separate priv from mmu_idx
2023-05-05 LIU Zhiweitarget/riscv: Add a tb flags field for vstart
2023-05-05 Richard Hendersontarget/riscv: Remove mstatus_hs_{fs, vs} from tb_flags
2023-05-05 LIU Zhiweitarget/riscv: Encode the FS and VS on a normal way...
2023-05-05 LIU Zhiweitarget/riscv: Add a general status enum for extensions
2023-05-05 LIU Zhiweitarget/riscv: Extract virt enabled state from tb flags
2023-05-05 Weiwei Litarget/riscv: Use PRV_RESERVED instead of PRV_H
2023-05-05 Daniel Henrique... target/riscv/cpu.c: redesign register_cpu_props()
2023-05-05 Daniel Henrique... target/riscv: add RVG and remove cpu->cfg.ext_g
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_v
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_j
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_h
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_u
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_s
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_m
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_e
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_i
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_f
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_d
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_c
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_a
2023-05-05 Weiwei Litarget/riscv: Fix lines with over 80 characters
2023-05-05 Weiwei Litarget/riscv: Fix format for comments
2023-05-05 Weiwei Litarget/riscv: Remove riscv_cpu_virt_enabled()
2023-05-05 LIU Zhiweitarget/riscv: Convert env->virt to a bool env->virt_enabled
2023-05-05 Weiwei Litarget/riscv: Add support for Zce
2023-05-05 Weiwei Litarget/riscv: add support for Zcmt extension
2023-05-05 Weiwei Litarget/riscv: add cfg properties for Zc* extension
2023-05-05 Weiwei Litarget/riscv: Simplify type conversion for CPURISCVState
2023-03-12 Peter MaydellMerge tag 'linux-user-for-8.0-pull-request' of https...
2023-03-10 Peter MaydellMerge tag 'pull-hex-20230306' of https://github.com...
2023-03-09 Peter MaydellMerge tag 'vfio-updates-20230307.1' of https://gitlab...
2023-03-09 Peter MaydellMerge tag 'pull-request-2023-03-07' of https://gitlab...
2023-03-09 Peter MaydellMerge tag 'pull-aspeed-20230307' of https://github...
2023-03-07 Peter MaydellMerge tag 'for-upstream-mb' of https://gitlab.com/bonzi...
2023-03-07 Peter MaydellMerge tag 'pull-riscv-to-apply-20230306' of https:...
2023-03-06 Alexandre Ghitiriscv: Introduce satp mode hw capabilities
2023-03-06 Alexandre Ghitiriscv: Allow user to set the satp mode
2023-03-05 Christoph Muellnertarget/riscv: implement Zicbom extension
2023-03-05 Christoph Muellnertarget/riscv: implement Zicboz extension
2023-03-03 Peter MaydellMerge tag 'pull-aspeed-20230302' of https://github...
2023-03-03 Peter MaydellMerge tag 'pull-loongarch-20230303' of https://gitlab...
2023-03-03 Peter MaydellMerge tag 'migration-20230302-pull-request' of https...
2023-03-03 Peter MaydellMerge tag 'for_upstream' of https://git.kernel.org...
2023-03-03 Peter MaydellMerge tag 'pull-riscv-to-apply-20230303' of https:...
2023-03-02 Palmer DabbeltMerge patch series "target/riscv: some vector_helper...
2023-03-02 Palmer DabbeltMerge patch series "RISCVCPUConfig related cleanups"
2023-03-02 Palmer DabbeltMerge patch series "target/riscv: Add support for Svadu...
2023-03-02 Weiwei Litarget/riscv: Add csr support for svadu
2023-03-02 Weiwei Litarget/riscv: Add support for Zicond extension
2023-03-02 Palmer DabbeltMerge patch series "target/riscv: Various fixes to...
2023-03-01 Palmer DabbeltMerge patch series "target/riscv: Some updates to float...
2023-03-01 Palmer DabbeltMerge patch series "make write_misa a no-op and FEATURE...
2023-03-01 Weiwei Litarget/riscv: Add cfg properties for Zv* extensions
2023-03-01 Daniel Henrique... target/riscv/cpu: remove CPUArchState::features and...
2023-03-01 Daniel Henrique... target/riscv: remove RISCV_FEATURE_MMU
2023-03-01 Daniel Henrique... target/riscv: remove RISCV_FEATURE_PMP
2023-03-01 Daniel Henrique... target/riscv: remove RISCV_FEATURE_EPMP
2023-03-01 Daniel Henrique... target/riscv: remove RISCV_FEATURE_DEBUG
2023-03-01 Daniel Henrique... target/riscv: allow MISA writes as experimental
2023-03-01 Daniel Henrique... target/riscv: introduce riscv_cpu_cfg()
2023-03-01 Paolo BonziniMerge branch 'xenfv-kvm-15' of git://git.infradead...
2023-02-28 Peter MaydellMerge tag 'buildsys-qom-qdev-ui-20230227' of https...
2023-02-27 Philippe Mathieu... target/riscv/cpu: Move Floating-Point fields closer
2023-02-27 Philippe Mathieu... target/cpu: Restrict do_transaction_failed() handlers...
2023-02-27 Philippe Mathieu... target/cpu: Restrict cpu_get_phys_page_debug() handlers...
2023-02-07 Peter MaydellMerge tag 'for-upstream-py38' of https://gitlab.com...
2023-02-07 Peter MaydellMerge tag 'pull-aspeed-20230207' of https://github...
2023-02-07 Peter MaydellMerge tag 'pull-riscv-to-apply-20230207' of https:...
2023-02-06 Christoph MüllnerRISC-V: Adding XTheadFmv ISA extension
2023-02-06 Christoph MüllnerRISC-V: Add initial support for T-Head C906
2023-02-06 Christoph MüllnerRISC-V: Adding T-Head FMemIdx extension
2023-02-06 Christoph MüllnerRISC-V: Adding T-Head MemIdx extension
2023-02-06 Christoph MüllnerRISC-V: Adding T-Head MemPair extension
2023-02-06 Christoph MüllnerRISC-V: Adding T-Head multiply-accumulate instructions
2023-02-06 Christoph MüllnerRISC-V: Adding XTheadCondMov ISA extension
2023-02-06 Christoph MüllnerRISC-V: Adding XTheadBs ISA extension
2023-02-06 Christoph MüllnerRISC-V: Adding XTheadBb ISA extension
2023-02-06 Christoph MüllnerRISC-V: Adding XTheadBa ISA extension
2023-02-06 Christoph MüllnerRISC-V: Adding XTheadSync ISA extension
2023-02-06 Christoph MüllnerRISC-V: Adding XTheadCmo ISA extension
2023-01-20 Peter MaydellMerge tag 'pull-riscv-to-apply-20230120' of https:...
2023-01-20 Daniel Henrique... target/riscv/cpu: set cpu->cfg in register_cpu_props()
2023-01-20 Bin Menghw/char: riscv_htif: Move registers from CPUArchState...
2023-01-08 Peter MaydellMerge tag 'for-upstream' of https://gitlab.com/bonzini...
2023-01-08 Peter MaydellMerge tag 'pull-tcg-20230106' of https://gitlab.com...
2023-01-07 Peter MaydellMerge tag 'pull-loongarch-20230106' of https://gitlab...
2023-01-06 Peter MaydellMerge tag 'pull-riscv-to-apply-20230106' of https:...
2023-01-06 Christoph MuellnerRISC-V: Add Zawrs ISA extension support
2023-01-06 LIU Zhiweitarget/riscv: Add itrigger_enabled field to CPURISCVState
2023-01-06 LIU Zhiweitarget/riscv: Add itrigger support when icount is enabled
2023-01-06 LIU Zhiweitarget/riscv: Add itrigger support when icount is not...
2023-01-06 Mayuresh Chitaletarget/riscv: Add smstateen support
2022-12-18 Peter MaydellMerge tag 'pull-hex-20221216-1' of https://github.com...
2022-12-18 Peter MaydellMerge tag 'pull-loongarch-20221215' of https://gitlab...
2022-12-17 Peter MaydellMerge tag 'pull-target-arm-20221216' of https://git...
2022-12-16 Peter Maydelltarget/riscv: Convert to 3-phase reset
2022-10-13 Stefan HajnocziMerge tag 'kraxel-20221013-pull-request' of https:...
2022-10-13 Stefan HajnocziMerge tag 'pull-request-2022-10-12' of https://gitlab...
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