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2020-07-02	LIU Zhiwei	target/riscv: vector integer min/max instructions	blob \| commitdiff \| raw
2020-07-02	LIU Zhiwei	target/riscv: vector integer comparison instructions	blob \| commitdiff \| raw \| diff to current
2020-07-02	LIU Zhiwei	target/riscv: vector narrowing integer right shift...	blob \| commitdiff \| raw \| diff to current
2020-07-02	LIU Zhiwei	target/riscv: vector single-width bit shift instructions	blob \| commitdiff \| raw \| diff to current
2020-07-02	LIU Zhiwei	target/riscv: vector bitwise logical instructions	blob \| commitdiff \| raw \| diff to current
2020-07-02	LIU Zhiwei	target/riscv: vector integer add-with-carry / subtract...	blob \| commitdiff \| raw \| diff to current
2020-07-02	LIU Zhiwei	target/riscv: vector widening integer add and subtract	blob \| commitdiff \| raw \| diff to current
2020-07-02	LIU Zhiwei	target/riscv: vector single-width integer add and subtract	blob \| commitdiff \| raw \| diff to current
2020-07-02	LIU Zhiwei	target/riscv: add vector amo operations	blob \| commitdiff \| raw \| diff to current
2020-07-02	LIU Zhiwei	target/riscv: add fault-only-first unit stride load	blob \| commitdiff \| raw \| diff to current
2020-07-02	LIU Zhiwei	target/riscv: add vector index load and store instructions	blob \| commitdiff \| raw \| diff to current
2020-07-02	LIU Zhiwei	target/riscv: add vector stride load and store instructions	blob \| commitdiff \| raw \| diff to current
2020-07-02	LIU Zhiwei	target/riscv: add vector configure instruction	blob \| commitdiff \| raw \| diff to current

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