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hw/openrisc/openrisc_sim: Parameterize initialization
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2022-02-23 Peter MaydellMerge remote-tracking branch 'remotes/berrange-gitlab...
2022-02-22 Peter MaydellMerge remote-tracking branch 'remotes/lvivier-gitlab...
2022-02-22 Peter MaydellMerge remote-tracking branch 'remotes/thuth-gitlab...
2022-02-21 Peter MaydellMerge remote-tracking branch 'remotes/bonzini-gitlab...
2022-02-21 Philippe Mathieu... target: Add missing "qemu/timer.h" include
2022-02-16 Peter MaydellMerge remote-tracking branch 'remotes/alistair/tags...
2022-02-16 Weiwei Litarget/riscv: add support for svpbmt extension
2022-02-16 Weiwei Litarget/riscv: add support for svinval extension
2022-02-16 Weiwei Litarget/riscv: add support for svnapot extension
2022-02-16 Weiwei Litarget/riscv: add PTE_A/PTE_D/PTE_U bits check for...
2022-02-16 Guo Rentarget/riscv: Ignore reserved bits in PTE for RV64
2022-02-16 Anup Pateltarget/riscv: Allow users to force enable AIA CSRs...
2022-02-16 Anup Pateltarget/riscv: Implement AIA IMSIC interface CSRs
2022-02-16 Anup Pateltarget/riscv: Implement AIA xiselect and xireg CSRs
2022-02-16 Anup Pateltarget/riscv: Implement AIA mtopi, stopi, and vstopi...
2022-02-16 Anup Pateltarget/riscv: Implement AIA interrupt filtering CSRs
2022-02-16 Anup Pateltarget/riscv: Implement AIA hvictl and hviprioX CSRs
2022-02-16 Anup Pateltarget/riscv: Implement AIA CSRs for 64 local interrupt...
2022-02-16 Anup Pateltarget/riscv: Implement AIA local interrupt priorities
2022-02-16 Anup Pateltarget/riscv: Allow AIA device emulation to set ireg...
2022-02-16 Anup Pateltarget/riscv: Add defines for AIA CSRs
2022-02-16 Anup Pateltarget/riscv: Add AIA cpu feature
2022-02-16 Anup Pateltarget/riscv: Allow setting CPU feature from machine...
2022-02-16 Anup Pateltarget/riscv: Improve delivery of guest external interrupts
2022-02-16 Anup Pateltarget/riscv: Implement hgeie and hgeip CSRs
2022-02-16 Anup Pateltarget/riscv: Implement SGEIP bit in hip and hie CSRs
2022-02-16 Anup Pateltarget/riscv: Fix trap cause for RV32 HS-mode CSR acces...
2022-02-16 LIU Zhiweitarget/riscv: Fix vill field write in vtype
2022-02-16 Philipp Tomsichtarget/riscv: Add XVentanaCondOps custom extension
2022-02-16 Philipp Tomsichtarget/riscv: iterate over a table of decoders
2022-02-16 Philipp Tomsichtarget/riscv: access cfg structure through DisasContext
2022-02-16 Philipp Tomsichtarget/riscv: access configuration through cfg_ptr...
2022-02-16 Philipp Tomsichtarget/riscv: riscv_tr_init_disas_context: copy pointer...
2022-02-16 Philipp Tomsichtarget/riscv: refactor (anonymous struct) RISCVCPU...
2022-02-16 Frédéric Pétrottarget/riscv: correct "code should not be reached"...
2022-02-02 Peter MaydellMerge remote-tracking branch 'remotes/hdeller/tags...
2022-01-21 Peter MaydellMerge remote-tracking branch 'remotes/alistair/tags...
2022-01-21 LIU Zhiweitarget/riscv: Relax UXL field for debugging
2022-01-21 LIU Zhiweitarget/riscv: Enable uxl field write
2022-01-21 LIU Zhiweitarget/riscv: Set default XLEN for hypervisor
2022-01-21 LIU Zhiweitarget/riscv: Adjust scalar reg in vector with XLEN
2022-01-21 LIU Zhiweitarget/riscv: Adjust vector address with mask
2022-01-21 LIU Zhiweitarget/riscv: Fix check range for first fault only
2022-01-21 LIU Zhiweitarget/riscv: Remove VILL field in VTYPE
2022-01-21 LIU Zhiweitarget/riscv: Adjust vsetvl according to XLEN
2022-01-21 LIU Zhiweitarget/riscv: Split out the vill from vtype
2022-01-21 LIU Zhiweitarget/riscv: Split pm_enabled into mask and base
2022-01-21 LIU Zhiweitarget/riscv: Calculate address according to XLEN
2022-01-21 LIU Zhiweitarget/riscv: Alloc tcg global for cur_pm[mask|base]
2022-01-21 LIU Zhiweitarget/riscv: Create current pm fields in env
2022-01-21 LIU Zhiweitarget/riscv: Adjust csr write mask with XLEN
2022-01-21 LIU Zhiweitarget/riscv: Relax debug check for pm write
2022-01-21 LIU Zhiweitarget/riscv: Use gdb xml according to max mxlen
2022-01-21 LIU Zhiweitarget/riscv: Extend pc for runtime pc write
2022-01-21 LIU Zhiweitarget/riscv: Ignore the pc bits above XLEN
2022-01-21 LIU Zhiweitarget/riscv: Create xl field in env
2022-01-21 LIU Zhiweitarget/riscv: Sign extend pc for different XLEN
2022-01-21 LIU Zhiweitarget/riscv: Sign extend link reg for jal and jalr
2022-01-21 LIU Zhiweitarget/riscv: Don't save pc when exception return
2022-01-21 LIU Zhiweitarget/riscv: Adjust pmpcfg access with mxl
2022-01-21 Frank Changtarget/riscv: rvv-1.0: Allow Zve32f extension to be...
2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve32f support for narrowing...
2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve32f support for widening...
2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve32f support for single...
2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve32f support for scalar...
2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve32f support for configura...
2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve32f extension into RISC-V
2022-01-21 Frank Changtarget/riscv: rvv-1.0: Allow Zve64f extension to be...
2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve64f support for narrowing...
2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve64f support for widening...
2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve64f support for single...
2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve64f support for scalar...
2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve64f support for vsmul...
2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve64f support for vmulh...
2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve64f support for load...
2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve64f support for configura...
2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve64f extension into RISC-V
2022-01-21 Yifei Jiangtarget/riscv: Support virtual time context synchronization
2022-01-21 Yifei Jiangtarget/riscv: Implement virtual time adjusting with...
2022-01-21 Yifei Jiangtarget/riscv: Add kvm_riscv_get/put_regs_timer
2022-01-21 Yifei Jiangtarget/riscv: Add host cpu type
2022-01-21 Yifei Jiangtarget/riscv: Handle KVM_EXIT_RISCV_SBI exit
2022-01-21 Yifei Jiangtarget/riscv: Support setting external interrupt by KVM
2022-01-21 Yifei Jiangtarget/riscv: Support start kernel directly by KVM
2022-01-21 Yifei Jiangtarget/riscv: Implement kvm_arch_put_registers
2022-01-21 Yifei Jiangtarget/riscv: Implement kvm_arch_get_registers
2022-01-21 Yifei Jiangtarget/riscv: Implement function kvm_arch_init_vcpu
2022-01-21 Yifei Jiangtarget/riscv: Add target/riscv/kvm.c to place the publi...
2022-01-12 Cédric Le GoaterMerge tag 'qemu-slof-20220110' of github.com:aik/qemu...
2022-01-11 Peter MaydellMerge remote-tracking branch 'remotes/philmd/tags/sdmmc...
2022-01-11 Peter MaydellMerge remote-tracking branch 'remotes/mst/tags/for_upst...
2022-01-08 Richard HendersonMerge tag 'bsd-user-arm-pull-request' of gitlab.com...
2022-01-08 Richard HendersonMerge tag 'pull-riscv-to-apply-20220108' of github...
2022-01-08 Alistair Francistarget/riscv: Implement the stval/mtval illegal instruction
2022-01-08 Alistair Francistarget/riscv: Fixup setting GVA
2022-01-08 Alistair Francistarget/riscv: Set the opcode in DisasContext
2022-01-08 Frédéric Pétrottarget/riscv: actual functions to realize crs 128-bit...
2022-01-08 Frédéric Pétrottarget/riscv: modification of the trans_csrxx for 128...
2022-01-08 Frédéric Pétrottarget/riscv: helper functions to wrap calls to 128...
2022-01-08 Frédéric Pétrottarget/riscv: adding high part of some csrs
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