Gerd Hoffmann [Thu, 27 Aug 2020 10:26:17 +0000 (12:26 +0200)]
meson: fix keymaps without qemu-keymap
In case the qemu-keymap tool generating them is neither installed on the
system nor built from sources (due to xkbcommon not being available)
qemu will not find the keymaps when started directly from the build
tree,
This happens because commit ddcf607fa3d6 ("meson: drop keymaps symlink")
removed the symlink to the source tree, and the special handling for
install doesn't help in case we do not install qemu.
Lets fix that by simply copying over the file from the source tree as
fallback.
Reported-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Message-Id: <20200827102617.14448-1-kraxel@redhat.com>
[thuth: Rebased, changed "config_host['qemu_datadir']" to "qemu_datadir",
added Gerd's UNLINK fix to configure script] Signed-off-by: Thomas Huth <thuth@redhat.com>
Thomas Huth [Mon, 24 Aug 2020 06:25:21 +0000 (08:25 +0200)]
cirrus.yml: Split FreeBSD job into two parts
The FreeBSD jobs currently hit the 1h time limit in the Cirrus-CI.
We have to split the build targets here to make sure that the job
finishes in time again. According to the Cirrus-CI docs and some
tests that I did, it also seems like the total amount of CPUs that
can be used for FreeBSD jobs is limited to 8, so each job now only
gets 4 CPUs. That increases the compilation time of each job a little
bit, but it still seems to be better to run two jobs with 4 CPUs each
in parallel than to run two jobs with 8 CPUs sequentially.
Message-Id: <20200831154405.229706-1-thuth@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
Thomas Huth [Fri, 24 Jul 2020 13:18:56 +0000 (15:18 +0200)]
cirrus.yml: Update the macOS jobs to Catalina
When looking at the CI jobs on cirrus-ci.com, it seems like the mojave-based
images have been decomissioned a while ago already, since apparently all our
jobs get automatically upgraded to catalina. So let's update our YML script
accordingly to avoid confusion.
Reviewed-by: Ed Maste <emaste@freebsd.org>
Message-Id: <20200728074405.13118-5-thuth@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
Thomas Huth [Mon, 27 Jul 2020 15:24:26 +0000 (17:24 +0200)]
cirrus.yml: Compile macOS with -Werror
Compiler warnings currently go unnoticed in our macOS builds, since -Werror
is only enabled for Linux and MinGW builds by default. So let's enable them
here now, too.
Unfortunately, the sasl header is marked as deprecated in the macOS headers
and thus generates a lot of deprecation warnings. Thus we have to also use
-Wno-error=deprecated-declarations to be able to compile the code here.
Message-Id: <20200728074405.13118-4-thuth@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
Thomas Huth [Wed, 15 Jul 2020 17:47:07 +0000 (19:47 +0200)]
cirrus.yml: Compile FreeBSD with -Werror
Compiler warnings currently go unnoticed in our FreeBSD builds, since
-Werror is only enabled for Linux and MinGW builds by default. So let's
enable them here now, too.
Reviewed-by: Ed Maste <emaste@freebsd.org>
Message-Id: <20200728074405.13118-3-thuth@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
Thomas Huth [Thu, 16 Jul 2020 10:23:48 +0000 (12:23 +0200)]
configure: Fix atomic64 test for --enable-werror on macOS
When using --enable-werror for the macOS builders in the Cirrus-CI,
the atomic64 test is currently failing, and config.log shows a bunch
of error messages like this:
config-temp/qemu-conf.c:6:7: error: implicit declaration of function
'__atomic_load_8' is invalid in C99 [-Werror,-Wimplicit-function-declaration]
y = __atomic_load_8(&x, 0);
^
config-temp/qemu-conf.c:6:7: error: this function declaration is not a
prototype [-Werror,-Wstrict-prototypes]
Seems like these __atomic_*_8 functions are available in one of the
libraries there, so that the test links and passes there when not
using --enable-werror. But there does not seem to be a valid prototype
for them in any of the header files, so that the test fails when using
--enable-werror.
Fix it by using the "official" built-in functions instead (see e.g.
https://gcc.gnu.org/onlinedocs/gcc/_005f_005fatomic-Builtins.html).
We are not using the *_8 variants in QEMU anyway.
Suggested-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Reviewed-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20200728074405.13118-2-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
QOM Cleanups:
* Fix typo in AARCH64_CPU_GET_CLASS
* Rename QOM macros for consistency and/or to avoid
conflicts with other symbols
* Move typedefs to header files
* Correct instance/class sizes
* remotes/rth/tags/pull-mb-20200901: (76 commits)
target/microblaze: Reduce linux-user address space to 32-bit
target/microblaze: Add flags markup to some helpers
target/microblaze: Remove cpu_R[0]
target/microblaze: Remove last of old decoder
target/microblaze: Convert dec_stream to decodetree
target/microblaze: Convert dec_msr to decodetree
target/microblaze: Convert msrclr, msrset to decodetree
target/microblaze: Tidy do_rti, do_rtb, do_rte
target/microblaze: Convert dec_rts to decodetree
target/microblaze: Convert dec_bcc to decodetree
target/microblaze: Convert dec_br to decodetree
target/microblaze: Reorganize branching
target/microblaze: Convert mbar to decodetree
target/microblaze: Convert brk and brki to decodetree
target/microblaze: Tidy mb_cpu_dump_state
target/microblaze: Replace delayed_branch with tb_flags_to_set
target/microblaze: Replace clear_imm with tb_flags_to_set
target/microblaze: Use cc->do_unaligned_access
tcg: Add tcg_get_insn_start_param
target/microblaze: Store "current" iflags in insn_start
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Cornelia Huck [Mon, 24 Aug 2020 12:20:51 +0000 (14:20 +0200)]
virtio: add Virtio*BusClass sizes
Both VirtioPCIBusClass and VirtioCcwBusClass are typedefs of
VirtioBusClass, but set .class_size in the TypeInfo anyway
to be safe if that changes in the future.
Eduardo Habkost [Wed, 26 Aug 2020 17:10:05 +0000 (13:10 -0400)]
tls-cipher-suites: Correct instance_size
We do have a QCryptoTLSCipherSuites struct. It must be used when
setting instance_size of the QOM type. Luckily this never caused
problems because the QCryptoTLSCipherSuites struct has only a
parent_obj field and nothing else.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20200826171005.4055015-5-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Eduardo Habkost [Tue, 25 Aug 2020 19:20:48 +0000 (15:20 -0400)]
rx: Rename QOM type check macros
Currently we have a RXCPU typedef and a RXCPU type checking
macro, but OBJECT_DECLARE* would transform the RXCPU macro into a
function, and the function name would conflict with the typedef
name.
Rename the RXCPU* QOM type check macros to RX_CPU*, so we will
avoid the conflict and make the macro names consistent with the
TYPE_RX_CPU constant name.
This will make future conversion to OBJECT_DECLARE* easier.
Eduardo Habkost [Tue, 25 Aug 2020 19:20:42 +0000 (15:20 -0400)]
x86-iommu: Rename QOM type macros
Some QOM macros were using a X86_IOMMU_DEVICE prefix, and others
were using a X86_IOMMU prefix. Rename all of them to use the
same X86_IOMMU_DEVICE prefix.
This will make future conversion to OBJECT_DECLARE* easier.
Greg Kurz [Tue, 1 Sep 2020 14:20:16 +0000 (16:20 +0200)]
Makefile: Fix in-tree clean/distclean
Doing 'make clean' or 'make distclean' in a freshly cloned tree results in:
make: *** No rule to make target 'ninja-clean', needed by 'clean'. Stop.
Make the fallback rules global. While here, change the ninjatool recipe to
always have a zero exit status and thus prevent make to emit a warning.
Fixes: a56650518f5b ("configure: integrate Meson in the build system") Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <159897001659.442705.15538955005543395950.stgit@bahia.lan> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Greg Kurz [Tue, 1 Sep 2020 14:20:10 +0000 (16:20 +0200)]
Makefile: Add back TAGS/ctags/cscope rules
It is a bit of a pain to be forced to run configure before being able
to use cscope and friends. Add back the rules to build them in-tree
as before commit a56650518f5b.
Fixes: a56650518f5b ("configure: integrate Meson in the build system") Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <159897001005.442705.16516671603870288336.stgit@bahia.lan> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Peter Maydell [Tue, 1 Sep 2020 15:51:37 +0000 (16:51 +0100)]
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200901' into staging
target-arm queue:
* Implement fp16 support for AArch32 VFP and Neon
* hw/arm/sbsa-ref: add "reg" property to DT cpu nodes
* hw/arm/sbsa-ref : Add embedded controller in secure memory
target/microblaze: Reduce linux-user address space to 32-bit
User-space programs cannot use the 64-bit lwea/swea instructions.
We can improve code generation and runtime by restricting the
user-only address space to 32-bit.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
target/microblaze: Add flags markup to some helpers
The mmu_read, mmu_write, get, and put helpers do not touch the
general registers, or any of the other variables managed by tcg.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Do not initialize cpu_R[0], as this should be totally unused.
The cpu_for_read and cpu_for_write functions use a local temp.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
All instructions have been convered. Issue sigill if decodetree
does not match. Remove argument decode from DisasContext.
Remove microblaze-decode.h.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
target/microblaze: Convert dec_stream to decodetree
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
target/microblaze: Convert msrclr, msrset to decodetree
Split this out of dec_msr.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Since cpu_msr is no longer a 64-bit quantity, we can simplify
the arithmetic in these functions.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Remove the btaken variable, and simplify things by always computing
the full branch destination into btarget. This avoids all need for
sync_jmpstate().
Retain the direct branch behaviour by remembering the jump destination
in jmp_dest, discarding btarget. In the normal case, where the branch
delay slot cannot trap (e.g. arithmetic), tcg will remove the computation
into btarget, leaving us with just the tcg direct branching at the end.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Split this out of the normal branch instructions,
as it requires special handling.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
target/microblaze: Convert brk and brki to decodetree
Split these out of the normal branch instructions, as they require
special handling. Perform the entire operation inline, instead of
raising EXCP_BREAK to do the work in mb_cpu_do_interrupt.
This fixes a bug in that brki rd, imm, for imm != 0x18 is not
supposed to set MSR_BIP. This fixes a bug in that imm == 0 is
the reset vector and 0x18 is the debug vector, and neither should
raise a tcg exception in system mode.
Introduce EXCP_SYSCALL for microblaze-linux-user.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Using lookup_symbol is quite slow; remove that. Decode the
various bits of iflags; only show imm, btaken, btarget when
they are relevant to iflags. Improve formatting.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
target/microblaze: Replace delayed_branch with tb_flags_to_set
The multi-stage counter can be replaced by clearing D_FLAG,
the or'ing in tb_flags_to_set. The jump then happens when
D_FLAG is finally cleared.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
target/microblaze: Replace clear_imm with tb_flags_to_set
This more general update variable will be able to handle
delay slots as well.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This fixes the problem in which unaligned stores succeeded,
but then we raised the exception after modifying memory.
Store the ESS for the unaligned data access in the iflags
for the insn, so that it can be found during unwind.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
MicroBlaze will shortly need to update a parameter in place.
Add an interface to read to match that for write.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
target/microblaze: Store "current" iflags in insn_start
This data is available during exception unwinding, thus
we can restore it from there directly, rather than saving
it during the TB. Thus we may remove the t_sync_flags()
calls in the load/store operations.
Note that these calls were missing from the other places
where runtime exceptions may be raised, such as idiv and
the floating point operations.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Do not call cpu_restore_state when no exception will be
delivered. This can lead to inconsistent cpu state.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reported-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
It makes sense to keep BIMM with D_FLAG, as they can be written
back to iflags at the same time. BIMM_FLAG does not need to be
added to IFLAGS_TB_MASK because it does not affect the next TB,
only the exception path out of the current TB. Renumber IMM_FLAG,
as the value 4 holds no particular significance; pack these two
flags at the bottom of the bitfield.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
target/microblaze: Assert no overlap in flags making up tb_flags
Create MSR_TB_MASK. Use it in cpu_get_tb_cpu_state, and check
that IFLAGS_TB_MASK does not overlap.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
target/microblaze: Convert dec_load and dec_store to decodetree
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Restore the correct PC when an exception must be raised.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
target/microblaze: Cache mem_index in DisasContext
Ideally, nothing outside the top-level of translation even
has access to env. Cache the value in init_disas_context.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
target/microblaze: Replace MSR_EE_FLAG with MSR_EE
There's no reason to define MSR_EE_FLAG; we can just use the
original MSR_EE define. Document the other flags copied into
tb_flags with iflag to reserve those bits.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
target/microblaze: Mark fpu helpers TCG_CALL_NO_WG
Now that FSR is no longer a tcg global temp, we can say that
the fpu helpers do not write to tcg temps. All temps are
read implicitly by the fpu exception path.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
target/microblaze: Fix cpu unwind for fpu exceptions
Restore the correct PC when an exception must be raised.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
The current dec_check_fpuv2 test, raising an FPU exception for
an unimplemented instruction, appears to be contradictory to
the manual. Drop that and merely check use_fpu == 2.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
target/microblaze: Convert dec_barrel to decodetree
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
target/microblaze: Unwind properly when raising divide-by-zero
Restore the correct pc when raising divide-by-zero. Also, the
MSR[DZO] bit is sticky -- it is not cleared with a successful divide.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
target/microblaze: Convert dec_and, dec_or, dec_xor to decodetree
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
target/microblaze: Convert dec_pattern to decodetree
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
These are simple enough operations; we do not need to
call an out-of-line helper.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Use tcg_gen_add2_i32 for computing carry.
This removes the last use of helper_carry, so remove that.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Adds infrastrucure for translation of instructions, which could
not be added before their first use. Cache a temporary which
represents r0 as the immediate 0 value, or a sink.
Move the special case of opcode_0_illegal from old_decode()
into decodetree as well, lest this get interpreted as add.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
The new interface is a stub that recognizes no instructions.
It falls back to the old decoder for all instructions.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
target/microblaze: Ensure imm constant is always available
Include the env->imm value in the TB values when IMM_FLAG is set.
This means that we can always reconstruct the complete 32-bit imm.
Discard env_imm when its contents can no longer be accessed.
Fix user-mode checks for BRK/BRKI, which depend on IMM.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Also remove the related defines, DISAS_MB and DEBUG_DISAS.
Rely on print_insn_microblaze.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This is never used in op_helper.c and translate.c. There are
two trivial uses in helper.c which can be improved by always
logging MMU_EXCP to CPU_LOG_INT.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Finish the conversion to the generic translator_loop.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Part one of conversion to the generic translator_loop is to
use the DisasContextBase and the members therein.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
target/microblaze: Check singlestep_enabled in gen_goto_tb
Do not use goto_tb if we're single-stepping.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Both exceptions and gen_goto_tb do not return. Use the
official DISAS_NORETURN enumerator for this case.
This eliminates all use of DISAS_TB_JUMP.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
target/microblaze: Split out MSR[C] to its own variable
Having the MSR[C] bit separate will improve arithmetic that operates
on the carry bit. Having mb_cpu_read_msr() populate MSR[CC] will
prevent the carry copy not matching the carry bit.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
All of the tcg globals can be recorded in the same table.
Drop the "r" prefix from "rpc" and "rmsr". Obviates the
need for regnames[], which was incorrectly not const.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
target/microblaze: Rename env_* tcg variables to cpu_*
This is cpu_imm, cpu_btaken, cpu_iflags, cpu_res_addr and cpu_res_val.
It is standard for these file-scope globals to begin with cpu_*.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
target/microblaze: Remove helper_debug and env->debug
This is not used, and seems redundant with -d cpu.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
target/microblaze: Mark raise_exception as noreturn
This will allow tcg to remove any dead code that might
follow an exception.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Split out gen_raise_exception which does no cpu state sync.
Rename t_gen_raise_exception to gen_raise_exception_sync to
emphasize that it does a sync. Create gen_raise_hw_excp to
simplify code raising EXCP_HW_EXCP.
Since there is now only one use of cpu_esr, perform a store
instead and remove the TCG variable.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Since cpu_ear is only used during MSR and MTR instructions,
we can just as easily use an explicit load and store, so
eliminate the variable.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
The exception data register is only 32-bits wide. Do not use a
64-bit type to represent it. Since cpu_edr is only used during
MSR and MTR instructions, we can just as easily use an explicit
load and store, so eliminate the variable.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
The branch target register is only 32-bits wide. Do not use a
64-bit type to represent it. Since cpu_btr is only used during
MSR and MTR instructions, we can just as easily use an explicit
load and store, so eliminate the variable.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
The exception status register is only 32-bits wide. Do not use a
64-bit type to represent it. Since cpu_fsr is only used during
MSR and MTR instructions, we can just as easily use an explicit
load and store, so eliminate the variable.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
The exception status register is only 32-bits wide.
Do not use a 64-bit type to represent it.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
The machine status register is only 32-bits wide.
Do not use a 64-bit type to represent it.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
The program counter is only 32-bits wide. Do not use a 64-bit
type to represent it. Since they are so closely related, fix
btarget at the same time.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Similar to splitting the sregs array, this will allow further
fixes and cleanups.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Finish eliminating the sregs array in favor of individual members.
Does not correct the width of EDR, yet.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Continue eliminating the sregs array in favor of individual members.
Does not correct the width of BTR, yet.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Continue eliminating the sregs array in favor of individual members.
Does not correct the width of FSR, yet.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
projects / mirror_qemu.git / log