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5 years agodrm/amd/powerplay: move the smc_if_version to asic file
Kevin Wang [Mon, 11 Mar 2019 03:00:48 +0000 (11:00 +0800)]
drm/amd/powerplay: move the smc_if_version to asic file

each asic may be has different smc if version,
so move its to asic file to implement.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: simplify sw-smu message map macro
Kevin Wang [Wed, 6 Mar 2019 11:45:16 +0000 (19:45 +0800)]
drm/amd/powerplay: simplify sw-smu message map macro

simplify macro of MSG_MAP for sw-smu

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: Cosmetic change for calling func amdgpu_gmc_vram_location
Oak Zeng [Thu, 7 Mar 2019 23:00:20 +0000 (17:00 -0600)]
drm/amdgpu: Cosmetic change for calling func amdgpu_gmc_vram_location

Use function parameter mc as the second parameter of amdgpu_gmc_vram_location,
so codes look more consistent.

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Christian Konig <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Fix plane address updates for video surface formats
Nicholas Kazlauskas [Mon, 11 Mar 2019 13:38:35 +0000 (09:38 -0400)]
drm/amd/display: Fix plane address updates for video surface formats

[Why]
For new DC planes the correct plane address fields are filled based
on whether the plane had a graphics or video format.

However, when we perform stream and plane updates using DC we only ever
fill in the graphics format fields. This causing corruption and hangs
when using video surface formats like NV12 for planes.

[How]
Use the same logic everywhere we update dc_plane_address - always
fill in the correct fields based on the surface format type.

There are 3 places this is done:

- Atomic check, during DC plane creation
- Atomic commit, during plane prepare_fb
- Atomic commit tail, during amdgpu_dm_commit_planes

We use the fill_plane_tiling_attributes in all 3 locations and it
already needs the address to update DCC attributes, so the surface
address update logic can be moved into this helper.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: Move IB pool init and fini v2
Andrey Grodzovsky [Wed, 6 Mar 2019 21:16:28 +0000 (16:16 -0500)]
drm/amdgpu: Move IB pool init and fini v2

Problem:
Using SDMA for TLB invalidation in certain ASICs exposed a problem
of IB pool not being ready while SDMA already up on Init and already
shutt down while SDMA still running on Fini. This caused
IB allocation failure. Temproary fix was commited into a
bringup branch but this is the generic fix.

Fix:
Init IB pool rigth after GMC is ready but before SDMA is ready.
Do th opposite for Fini.

v2: Remove restriction on SDMA early init and move amdgpu_ib_pool_fini

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: On DCN1, Wait for vupdate on cursor updates
David Francis [Thu, 21 Feb 2019 20:04:05 +0000 (15:04 -0500)]
drm/amd/display: On DCN1, Wait for vupdate on cursor updates

[Why]
Cursor updates must acquire the pipe control lock to
prevent vupdate from triggering in the middle of cursor
programming. On DCN1 the pipe control lock prevents
pageflips from occurring. This means that a cursor update
right before vupdate can delay a pending pageflip

[How]
If the time until the next vupdate is less than a
conservative estimate of the cursor programming time,
wait until the vupdate has passed before locking.

Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: add i2c over aux failure handling
Wenjing Liu [Sat, 23 Feb 2019 21:07:45 +0000 (16:07 -0500)]
drm/amd/display: add i2c over aux failure handling

[why]
We will not retry when EDID read failure using i2c over aux

[how]
treat i2c over aux failure the same as defer

Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: David Francis <David.Francis@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: fix up reference clock abstractions
Jun Lei [Fri, 22 Feb 2019 21:50:00 +0000 (16:50 -0500)]
drm/amd/display: fix up reference clock abstractions

[why]
"reference clock" is a very overloaded variable in DC and causes confusion
as there are multiple sources of reference clock, which may be different values
incorrect input values to DML will cause DCHUB to be programmed improperly
and lead to hard to debug underflow issues

[how]
instead of using ref clock everywhere, specify WHICH ref clock:
- xtalin
- dccg refclk
- dchub refclk

these are all distinct values which may not be equal

Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: David Francis <David.Francis@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Expose support for alpha blending on overlays
Nicholas Kazlauskas [Thu, 21 Feb 2019 19:57:48 +0000 (14:57 -0500)]
drm/amd/display: Expose support for alpha blending on overlays

[Why]
The DRM overlay planes DM exposes support RGBA formats but are currently
forced as fully opaque over whatever they overlay.

[How]
Expose DRM blending mode and alpha properties to userspace.

The overlays exposed support per-pixel pre-multiplied alpha along with
global plane opacity.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: add HW i2c arbitration with dmcu
Charlene Liu [Fri, 22 Feb 2019 18:55:46 +0000 (13:55 -0500)]
drm/amd/display: add HW i2c arbitration with dmcu

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: implement bounding box update based on uclk breakdown
Jun Lei [Tue, 19 Feb 2019 15:33:21 +0000 (10:33 -0500)]
drm/amd/display: implement bounding box update based on uclk breakdown

[why]
Actual breakdown of DPM level varies by SKU (for the same family)
DC needs some ability to ammend pre-silicon numbers

Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: 3.2.21
Aric Cyr [Fri, 22 Feb 2019 22:02:14 +0000 (17:02 -0500)]
drm/amd/display: 3.2.21

Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: reduce abm min reduction, deviation gain and contrast factor
Josip Pavic [Fri, 22 Feb 2019 21:55:08 +0000 (16:55 -0500)]
drm/amd/display: reduce abm min reduction, deviation gain and contrast factor

[Why]
Increased power savings are desired for ABM 2.2.

[How]
Reduce the minimum reduction level, the deviation gain and the contrast factor
to allow for more aggressive operation of the algorithm.

Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Rename is_hdmi to is_hdmi_tmds type
Eric Bernstein [Fri, 15 Feb 2019 14:27:22 +0000 (09:27 -0500)]
drm/amd/display: Rename is_hdmi to is_hdmi_tmds type

HDMI has TMDS and FRL signal types. Be specific about what is used.

Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: add pipe lock during stream update
Wenjing Liu [Wed, 20 Feb 2019 19:00:55 +0000 (14:00 -0500)]
drm/amd/display: add pipe lock during stream update

[why]
Stream update will adjust both info packets and stream params,
need to make sure all things are applied togather.

[how]
add pipe lock during stream update

Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Increase DP blank timeout from 30 ms to 50 ms
Ken Chalmers [Fri, 15 Feb 2019 15:31:52 +0000 (09:31 -0600)]
drm/amd/display: Increase DP blank timeout from 30 ms to 50 ms

[Why]
At 24 Hz, a frame is 41.7 ms, so a 30 ms wait can (and does often)
timeout.

[How]
Bump timeout from 30 ms to 50 ms.

Signed-off-by: Ken Chalmers <ken.chalmers@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Combine field toggle macro and sequence write macro.
Yongqiang Sun [Fri, 15 Feb 2019 22:05:43 +0000 (17:05 -0500)]
drm/amd/display: Combine field toggle macro and sequence write macro.

[Why]
field toggle write is actual field sequence write with the same
field name.

[How]
Use REG_UPDATE_SEQ_2 for both sequence write and toggle.
Rename REG_UPDATE_1by1_3 to REG_UPDATE_SEQ_3.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Add PSR SMU Interrupt support
SivapiriyanKumarasamy [Mon, 10 Sep 2018 22:59:42 +0000 (18:59 -0400)]
drm/amd/display: Add PSR SMU Interrupt support

[WHY]
We have new bios capabilities enabling s0i2 entry on SMU interrupt. We want
this interrupt to be fired on PSR transitions such that we enter s0i2
when entering PSR active.

[HOW]
Add code to send the SMU interrupt with the appropriate
staticscreen flag when entering and exting PSR. Protect this
code with a config flag since it currently impacts BL PWM.

Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Refactor reg_set and reg_update.
Yongqiang Sun [Wed, 13 Feb 2019 15:35:43 +0000 (10:35 -0500)]
drm/amd/display: Refactor reg_set and reg_update.

[Why]
Current reg update and reg set use same functions and
only delta is update reads reg value and call update function.

[How]
Refactor reg update and reg set functions.
1.Implement different functions for reg update and reg set.
2.Wrap same process to a help function, both reg update and
reg set will call it.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Free DCN version of stream encoder
Eric Bernstein [Wed, 13 Feb 2019 22:56:38 +0000 (17:56 -0500)]
drm/amd/display: Free DCN version of stream encoder

Cross a TODO item off the list. Cleanup SIGNAL_TYPE_HDMI_FRL, it's
not currently supported.

Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: clean up dml_init_instance
Dmytro Laktyushkin [Mon, 11 Feb 2019 22:18:41 +0000 (17:18 -0500)]
drm/amd/display: clean up dml_init_instance

Get rid of DV style dml init in favour of the cleaner DC
style.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: apply Vega20 BACO workaround
Evan Quan [Thu, 7 Mar 2019 02:20:12 +0000 (10:20 +0800)]
drm/amd/powerplay: apply Vega20 BACO workaround

Applied vdci flush workaround for Vega20 BACO.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: XGMI pstate switch initial support
shaoyunl [Thu, 21 Feb 2019 21:30:25 +0000 (16:30 -0500)]
drm/amdgpu: XGMI pstate switch initial support

Driver vote low to high pstate switch whenever there is an outstanding
XGMI mapping request. Driver vote high to low pstate when all the
outstanding XGMI mapping is terminated.

Signed-off-by: shaoyunl <shaoyun.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: Enable XGMI mapping for peer device
shaoyunl [Fri, 22 Feb 2019 21:20:38 +0000 (16:20 -0500)]
drm/amdgpu: Enable XGMI mapping for peer device

Adjust vram base offset for XGMI mapping when update the PT entry so
the address will fall into correct XGMI aperture for peer device

Signed-off-by: shaoyunl <shaoyun.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: Add sysfs entries for xgmi hive v2.
Andrey Grodzovsky [Tue, 5 Mar 2019 15:39:08 +0000 (10:39 -0500)]
drm/amdgpu: Add sysfs entries  for xgmi hive v2.

For each device a file xgmi_device_id is created.
On the first device a subdirectory named xgmi_hive_info is created,
It contains  a file named hive_id and symlinks named node 1-4 linking
to each device in the hive.

v2: Return error codes instead of '-1' and few misspellings.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Don't ASSERT when total_planes == AMDGPU_MAX_PLANES
Nicholas Kazlauskas [Tue, 5 Mar 2019 17:24:08 +0000 (12:24 -0500)]
drm/amd/display: Don't ASSERT when total_planes == AMDGPU_MAX_PLANES

[Why]
Can happen on ASICs with 6 planes, but this isn't a bug since we haven't
written outside the array.

[How]
Use <= instead of <.

Cc: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reported-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Drop atomic_obj_lock for private obj
Nicholas Kazlauskas [Tue, 5 Mar 2019 14:14:17 +0000 (09:14 -0500)]
drm/amd/display: Drop atomic_obj_lock for private obj

[Why]
New DRM versions manage locking for private objects for us, so this
is no longer needed.

This also prevents a WARN_ON from occurring when the private object is
duplicated during the forced atomic commit that occurs from the HPD
handler.

The HPD handler calls drm_modeset_lock_all before the forced commit
and if the private object is duplicated then the
DEBUG_LOCKS_WARN_ON(ww_ctx->done_acquire) warning will be triggered
since we're trying to lock something when everything should have
already been locked.

[How]
Drop the lock and let DRM manage this.

Cc: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/amdgpu: Add ENGINE_CNTL register to vcn10 headers
Tom St Denis [Mon, 4 Mar 2019 15:58:44 +0000 (10:58 -0500)]
drm/amd/amdgpu: Add ENGINE_CNTL register to vcn10 headers

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: allow huge invalid mappings on GMC8
Christian König [Mon, 4 Feb 2019 14:00:34 +0000 (15:00 +0100)]
drm/amdgpu: allow huge invalid mappings on GMC8

Only GMC9 supports true huge pages, but we can still free invalid mappings
on GMC8.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: drop the huge page flag
Christian König [Fri, 1 Feb 2019 16:11:29 +0000 (17:11 +0100)]
drm/amdgpu: drop the huge page flag

Not needed any more since we now free PDs/PTs on demand.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: free PDs/PTs on demand
Christian König [Fri, 1 Feb 2019 13:02:10 +0000 (14:02 +0100)]
drm/amdgpu: free PDs/PTs on demand

When something is unmapped we now free the affected PDs/PTs again.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: allocate VM PDs/PTs on demand
Christian König [Wed, 30 Jan 2019 15:07:29 +0000 (16:07 +0100)]
drm/amdgpu: allocate VM PDs/PTs on demand

Let's start to allocate VM PDs/PTs on demand instead of pre-allocating
them during mapping.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: let amdgpu_vm_clear_bo figure out ats status v2
Christian König [Thu, 16 Aug 2018 08:49:41 +0000 (10:49 +0200)]
drm/amdgpu: let amdgpu_vm_clear_bo figure out ats status v2

Instead of providing it from outside figure out the ats status in the
function itself from the data structures.

v2: simplify finding the right level
v3: partially revert changes from v2, more cleanup and split code
    into more functions.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: rework shadow handling during PD clear v3
Christian König [Thu, 16 Aug 2018 11:23:48 +0000 (13:23 +0200)]
drm/amdgpu: rework shadow handling during PD clear v3

This way we only deal with the real BO in here.

v2: use a do { ... } while loop instead
v3: fix NULL pointer in v2

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: fix pcie sysfs interface when set wrong value
Likun Gao [Mon, 4 Mar 2019 02:46:27 +0000 (10:46 +0800)]
drm/amd/powerplay: fix pcie sysfs interface when set wrong value

The operation of mutex_unlock smu->mutex should be done when forced
level is larger than NUM_LINK_LEVELS in the function of force_clk_levels.

Reported-by: Julia Lawall <julia.lawall@lip6.fr>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: fix memdup.cocci warnings
kbuild test robot [Sat, 2 Mar 2019 06:50:36 +0000 (07:50 +0100)]
drm/amd/powerplay: fix memdup.cocci warnings

Simplify the code a bit by using kmemdup instead of kzalloc and memcpy.

Generated by: scripts/coccinelle/api/memdup.cocci

CC: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: kbuild test robot <fengguang.wu@intel.com>
Signed-off-by: Julia Lawall <julia.lawall@lip6.fr>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: fix missing assignment of error return code to variable ret
Colin Ian King [Sat, 2 Mar 2019 22:16:58 +0000 (22:16 +0000)]
drm/amdgpu: fix missing assignment of error return code to variable ret

An earlier commit replaced ttm_bo_wait with amdgpu_bo_sync_wait and
removed the error return assignment to variable ret. Fix this by adding
the assignment back. Also break line to clean up checkpatch overly
long line warning.

Detected by CoverityScan, CID#1477327 ("Logically dead code")

Fixes: c60cd590cb7d ("drm/amdgpu: Replace ttm_bo_wait with amdgpu_bo_sync_wait")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: also reroute VMC and UMD to IH ring 1 on Vega 20
Christian König [Mon, 4 Mar 2019 18:34:34 +0000 (19:34 +0100)]
drm/amdgpu: also reroute VMC and UMD to IH ring 1 on Vega 20

Same patch we alredy did for Vega10. Just re-route page faults to a separate
ring to avoid drowning in interrupts.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: reroute VMC and UMD to IH ring 1
Christian König [Fri, 2 Nov 2018 14:00:16 +0000 (15:00 +0100)]
drm/amdgpu: reroute VMC and UMD to IH ring 1

Page faults can easily overwhelm the interrupt handler.

So to make sure that we never lose valuable interrupts on the primary ring
we re-route page faults to IH ring 1.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Fix Divide by 0 in memory calculations
Murton Liu [Fri, 15 Feb 2019 20:05:43 +0000 (15:05 -0500)]
drm/amd/display: Fix Divide by 0 in memory calculations

Check if we get any values equal to 0, and set to 1 if so.

Signed-off-by: Murton Liu <murton.liu@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Sivapiriyan Kumarasamy <Sivapiriyan.Kumarasamy@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: add thick tile mode settings for Oland of gfx6
Tao Zhou [Fri, 1 Mar 2019 06:01:04 +0000 (14:01 +0800)]
drm/amdgpu: add thick tile mode settings for Oland of gfx6

Adding thick tile mode for Oland to prevent UMD from getting mode value 0

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Tested-by: Hui.Deng <hui.deng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu/gfx_v8_0: Mark expected switch fall-through
Gustavo A. R. Silva [Fri, 1 Mar 2019 20:58:32 +0000 (14:58 -0600)]
drm/amdgpu/gfx_v8_0: Mark expected switch fall-through

In preparation to enabling -Wimplicit-fallthrough, mark switch
cases where we are expecting to fall through.

This patch fixes the following warning:

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c: In function ‘gfx_v8_0_tiling_mode_table_init’:
./include/linux/device.h:1487:2: warning: this statement may fall through [-Wimplicit-fallthrough=]
  _dev_warn(dev, dev_fmt(fmt), ##__VA_ARGS__)
  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c:3236:3: note: in expansion of macro ‘dev_warn’
   dev_warn(adev->dev,
   ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c:3240:2: note: here
  case CHIP_CARRIZO:
  ^~~~

Warning level 3 was used: -Wimplicit-fallthrough=3

This patch is part of the ongoing efforts to enable
-Wimplicit-fallthrough.

Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/ttm: Fix spelling of "KiB"
Jakub Wilk [Thu, 28 Feb 2019 16:48:34 +0000 (17:48 +0100)]
drm/ttm: Fix spelling of "KiB"

The symbol for binary prefix kibi is "Ki", with uppercase K.
(In contrast, the symbol for decimal kilo is lowercase "k".)

Signed-off-by: Jakub Wilk <jwilk@jwilk.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: fix semicolon code style issue
Yang Wei [Thu, 28 Feb 2019 14:48:04 +0000 (22:48 +0800)]
drm/amd/powerplay: fix semicolon code style issue

Delete superfluous semicolons.

Signed-off-by: Yang Wei <yang.wei9@zte.com.cn>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: fix raven issue for sw smu
Huang Rui [Wed, 27 Feb 2019 10:51:01 +0000 (18:51 +0800)]
drm/amd/powerplay: fix raven issue for sw smu

Raven series doesn't support sw smu so far, so we have to add checking to
confirm it return false while the asic is raven.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: Bump amdgpu version for per-flip plane tiling updates
Nicholas Kazlauskas [Wed, 27 Feb 2019 17:56:36 +0000 (12:56 -0500)]
drm/amdgpu: Bump amdgpu version for per-flip plane tiling updates

To help xf86-video-amdgpu and mesa know DC supports updating the
tiling attributes for a framebuffer per-flip.

Cc: Michel Dänzer <michel@daenzer.net>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Add pp_smu null pointer check
Charlene Liu [Tue, 19 Feb 2019 17:14:19 +0000 (12:14 -0500)]
drm/amd/display: Add pp_smu null pointer check

res_pool->pp_smu may be NULL. Check before use

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: 3.2.20
Aric Cyr [Fri, 15 Feb 2019 20:14:37 +0000 (15:14 -0500)]
drm/amd/display: 3.2.20

Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Fix soft hang issue when some DPCD data invalid
Anthony Koo [Fri, 15 Feb 2019 19:19:30 +0000 (14:19 -0500)]
drm/amd/display: Fix soft hang issue when some DPCD data invalid

[Why]
AUX transaction returns success, but data has invalid lane count and rate
which when passed to VBIOS command table causes it to soft hang

[How]
Do some sanity checking and fail if the DPCD caps are invalid.

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Update plane tiling attributes for stream updates
Nicholas Kazlauskas [Mon, 28 Jan 2019 16:02:08 +0000 (11:02 -0500)]
drm/amd/display: Update plane tiling attributes for stream updates

[Why]
Tiling and DCC attributes can change when swapping framebuffers but
these will only ever get updated on full commits where
state->allow_modeset is true. But for the page-flip IOCTL
state->allow_modeset = false so these aren't updated and DCC changes
aren't being programmed.

[How]
Split out updating the tiling and DCC attributes into its own function
that's called when creating the plane for the first time but also
called when switching framebuffers before commit stream updates.

These functions also don't modify the plane state directly since the
plane state being used as reference is often the current one
being used by the hardware.

DC needs to be able to compare plane_state to the stream update
structures to determine if the hardware programming should happen. If
it's modified in place then nothing will be programmed and we can run
into concurrency issues.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Re-add custom degamma support
David Francis [Mon, 11 Feb 2019 19:15:19 +0000 (14:15 -0500)]
drm/amd/display: Re-add custom degamma support

[Why]
The dc_gamma_type CUSTOM_GAMMA is used to represent degamma
mappings passed in by drm. This type of gamma must be interpolated
into a transfer function by apply_1d_lut.  The line in
mod_color_calculate_degamma_params that handled this case
was erroneously removed.

[How]
For CUSTOM_GAMMA degamma, calculate the lut as before.

Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agoRevert "drm/amd/display: dcn add check surface in_use"
Charlene Liu [Thu, 14 Feb 2019 00:48:31 +0000 (19:48 -0500)]
Revert "drm/amd/display: dcn add check surface in_use"

This reverts commit 6bff1cc7780cca2fd2a775aa7b18b789e2a1b608.

[Description]
Revert since this will be checked at CP side.

Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: half bandwidth for YCbCr420 during validation
Martin Leung [Wed, 13 Feb 2019 22:06:31 +0000 (17:06 -0500)]
drm/amd/display: half bandwidth for YCbCr420 during validation

[Why]
used to be unable to run 4:2:0 if using a dongle because 4k60 bandwidth
exceeded dongle caps

[How]
half pixel clock during comparison to dongle cap. *Could get stuck on black
screen on monitor that don't support 420 but will be selecting 420 as
preferred mode*

Signed-off-by: Martin Leung <martin.leung@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Aidan Wood <Aidan.Wood@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Keep clocks high before seamless boot done
Anthony Koo [Sat, 9 Feb 2019 01:50:51 +0000 (20:50 -0500)]
drm/amd/display: Keep clocks high before seamless boot done

[Why]
UEFI boot usually uses a boot profile that uses higher clocks
and watermark settings.
UEFI boot surface is less optimal, for example it uses linear surface

[How]
Before we finish our seamless boot sequence, keep the clock and
watermark settings from boot.
Update to optimal settings only after first flip away from UEFI
frame buffer.

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Refactor pageflips plane commit
David Francis [Wed, 13 Feb 2019 18:20:11 +0000 (13:20 -0500)]
drm/amd/display: Refactor pageflips plane commit

[Why]
commit_planes is indented quite far

[How]
Move the pageflip code from an if statement to after a
continue

Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Allow pflips from a framebuffer to itself
David Francis [Wed, 6 Feb 2019 19:01:29 +0000 (14:01 -0500)]
drm/amd/display: Allow pflips from a framebuffer to itself

[Why]
IGT expects that pageflips can be triggered with the same
framebuffer before and after the commit

[How]
Expand the definition of pageflip to include any change
with an old framebuffer and a new framebuffer, even if they're
the same

Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Create overlay planes
Nicholas Kazlauskas [Fri, 18 Jan 2019 18:57:14 +0000 (13:57 -0500)]
drm/amd/display: Create overlay planes

[Why]
Raven has support for combining pipes for DRM_PLANE_TYPE_OVERLAY use
but no overlays are exposed to userspace.

[How]
Expose overlay planes based on DC plane caps.

If all the pipes are in use then the atomic commits can fail, but this
is expected behavior for userspace.

Only support RGB on overlays for now.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Drop underlay plane support
Nicholas Kazlauskas [Fri, 18 Jan 2019 18:42:34 +0000 (13:42 -0500)]
drm/amd/display: Drop underlay plane support

[Why]
Primary and underlay planes were previously exposed to DRM by using
max_planes and max_slave_planes.

The value for max_planes was always pipe_count + has_underlay.
If there was an underlay pipe, then max_slave_planes = 1.

Raven has pipe_count = 4, max_planes = 4, and max_slave_planes = 1.
So during plane initialziation it was actually "creating"
1 overlay plane and 3 primary planes... or it would be, had its
plane_type array not been dm_plane_type_default, which will only create
DRM_PLANE_TYPE_PRIMARY planes.

We can expose primary planes as supporting more than one CRTC at a time
to more closely resemble plane behavior on DCN but userspace doesn't
really expect planes to be used in this manner and will either
ignore the planes or crash.

Planes with index greater than max_streams are marked as supporting
all CRTCs. No ASIC currently has primary plane count greater than the
stream count but we shouldn't expose more than necessary.

[How]
Drop support for underlay planes. They aren't well tested and don't
fully work right at the moment.

Only create one primary plane per CRTC so we're not creating overlays.

Initialize plane types directly instead of referencing a misleading
array of plane types.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Add plane capabilities to dc_caps
Nicholas Kazlauskas [Tue, 5 Feb 2019 17:50:01 +0000 (12:50 -0500)]
drm/amd/display: Add plane capabilities to dc_caps

[Why]
The current dc_caps doesn't provide the information needed to
determine the count and type of each plane to be exposed to userspace.

There are three types of DRM planes that are exposed to userspace:

1. Primary planes (can be used for modesetting)
2. Overlay planes (can be blended below or above a primary plane)
3. Cursor planes (blended topmost)

We need to know the number and type of each in amdgpu_dm to expose
to userspace.

Hardware supports blending planes below, above or both ways depending
on the ASIC. Alpha support is also ASIC dependent. Some hardware has
dedicated pipes for overlays and other hardware combines the pipes.

All of this should be exposed in a way that DM can query and use.

[How]
Introduce the dc_plane_cap structure that describes the capabilities
for the hw planes.

It describes:
- the type of the plane
- whether the plane can blend with planes below it
- whether the plane can blend with planes above it
- whether the plane supports per pixel alpha blending
- supported formats on the plane (partial list for now)

Pre DCN ASICs don't have their full capabilities described for now.
They can be updated as needed in the future.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Set stream->mode_changed when connectors change
Nicholas Kazlauskas [Fri, 8 Feb 2019 18:21:05 +0000 (13:21 -0500)]
drm/amd/display: Set stream->mode_changed when connectors change

[Why]
The kms_plane@plane-position-covered-pipe-*-planes subtests can produce
a sequence of atomic commits such that neither active_changed nor
mode_changed but connectors_changed.

When this happens we remove the old stream from the context and add
a new stream but the new stream doesn't have mode_changed=true set.

This incorrect programming sequence causes CRC mismatches to occur in
the test.

The stream->mode_changed value should be set whenever a new stream
is created.

[How]
A new stream is created whenever drm_atomic_crtc_needs_modeset is true.
We previously covered the active_changed and mode_changed conditions
for the CRTC but connectors_changed is also checked within
drm_atomic_crtc_needs_modeset.

So just use drm_atomic_crtc_needs_modeset directly to determine the
mode_changed flag.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Respect aux return values
Thomas Lim [Wed, 16 Jan 2019 20:56:56 +0000 (15:56 -0500)]
drm/amd/display: Respect aux return values

[Why]
The new aux implementation was not up to spec. This caused us to fail DP
compliance as well as introduced serious delays during system resume.

[How]
Make dce_aux_transfer_raw return the operation result

Make dce_aux_transfer_with_retries delay with udelay instead
of msleep, and only on invalid reply.  Also fail on the second
invalid reply, third timeout, or first of any other error

Convert return values to drm error codes in amdgpu_dm

As the two aux transfer functions are now noticeably
different, change the names to better reflect their
functionality and document.

There was one last call to dc_link_aux_transfer that
should have retries, fix that

Signed-off-by: David Francis <David.Francis@amd.com>
Signed-off-by: Thomas Lim <Thomas.Lim@amd.com>
Reviewed-by: David Francis <David.Francis@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Eric Yang <eric.yang2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Add function to create 4d19 fixed point
Tyler DiBattista [Mon, 11 Feb 2019 16:22:49 +0000 (11:22 -0500)]
drm/amd/display: Add function to create 4d19 fixed point

[Why]
Implemented for future use

Signed-off-by: Tyler DiBattista <tyler.dibattista@amd.com>
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: add full update commit hint struct
Jun Lei [Tue, 12 Feb 2019 17:09:24 +0000 (12:09 -0500)]
drm/amd/display: add full update commit hint struct

In some cases we might need to do a full update. Add a commit_hints
struct for future use

Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Poll pending DOWN_REP before enabling the link
Martin Tsai [Mon, 11 Feb 2019 07:26:21 +0000 (15:26 +0800)]
drm/amd/display: Poll pending DOWN_REP before enabling the link

[Why]
With special monitor combination on MST, the UP_REQ could come
after clear payload table. It makes the pending DOWN_REP fail
to be handled after link training and the new DOWN_REQ will be queued
until time out .

[How]
To move the current polling pending DOWN_REP procedure to after
clear payload table to make sure the pending DOWN_REP can be
done before enabling the link.

Signed-off-by: Martin Tsai <martin.tsai@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: Add sysfs files for returning VRAM/GTT info v2
Kent Russell [Thu, 28 Feb 2019 12:05:02 +0000 (07:05 -0500)]
drm/amdgpu: Add sysfs files for returning VRAM/GTT info v2

Add 6 files that return (in bytes):
The total amount of VRAM/visible VRAM/GTT
and the current total used VRAM/visible VRAM/GTT

v2: Split used and total into separate files

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Kent Russell <kent.russell@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: add od condition for power limit
Likun Gao [Fri, 1 Feb 2019 05:22:33 +0000 (13:22 +0800)]
drm/amd/powerplay: add od condition for power limit

Add condition to judge whether overdrive is enabled and correct power
limit value for overdrive used by power limit interface.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: add limit of pp_feature for smu (v3)
Likun Gao [Thu, 31 Jan 2019 06:11:04 +0000 (14:11 +0800)]
drm/amd/powerplay: add limit of pp_feature for smu (v3)

Move pp_feature from the struct of amd_powerplay to amdgpu_device.
Add pp_feature limit for overdrive interface.

v2: put pp_feature into struct amdgpu_pm.
v3: merge feature_mask with pp_feature.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Suggested-by: Alex Deucher <alexander.deucher@amd.com>
Suggested-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: use REG32_PCIE wrapper instead for sw smu
Huang Rui [Mon, 25 Feb 2019 06:46:03 +0000 (14:46 +0800)]
drm/amd/powerplay: use REG32_PCIE wrapper instead for sw smu

This patch uses REG32_PCIE wrapper instead of writting pci_index2 and reading
pci_data2. This sequence should be protected by pcie_idx_lock.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: fix the issue of checking on message mapping
Huang Rui [Mon, 25 Feb 2019 11:43:00 +0000 (19:43 +0800)]
drm/amd/powerplay: fix the issue of checking on message mapping

The vega20_message_map[index] scope should be in PPSMC_Message_Count not in
SMU_MSG_MAX_COUNT.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: move setting allowed mask and feature enabling together
Huang Rui [Wed, 20 Feb 2019 11:58:11 +0000 (19:58 +0800)]
drm/amd/powerplay: move setting allowed mask and feature enabling together

This patch moves setting allowed mask and feature enabling together to refine
the programming sequence.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: fix byte alignment issue of smu11 pptable
Huang Rui [Tue, 12 Feb 2019 07:39:44 +0000 (15:39 +0800)]
drm/amd/powerplay: fix byte alignment issue of smu11 pptable

The smu_11_0_powerplay_table, smu_11_0_power_saving_clock_table, and
smu_11_0_overdrive_table need byte alignment. So we must add packed attribute
in the definitions.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: fix smc messsage index report
Huang Rui [Thu, 31 Jan 2019 13:09:00 +0000 (21:09 +0800)]
drm/amd/powerplay: fix smc messsage index report

We actually want to know the index of PPSMC_MSG.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: support sysfs to set/get pcie
Likun Gao [Thu, 21 Feb 2019 03:09:31 +0000 (11:09 +0800)]
drm/amd/powerplay: support sysfs to set/get pcie

Add sys interface to set and get pcie info for smu.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Gui Chengming <Jack.Gui@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: add override pcie parameters
Likun Gao [Thu, 21 Feb 2019 08:50:23 +0000 (16:50 +0800)]
drm/amd/powerplay: add override pcie parameters

PCIE parameters should be override to fix the conflict between the ASIC
capabilities and the system capabilities.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Gui Chengming <Jack.Gui@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: support sysfs to set socclk, fclk, dcefclk
Likun Gao [Wed, 20 Feb 2019 05:42:55 +0000 (13:42 +0800)]
drm/amd/powerplay: support sysfs to set socclk, fclk, dcefclk

Add sys interface to set socclk, fclk and dcefclk for smu.
Add feature_mask parameter for smu_upload_dpm_level as socclk, fclk and
dcefclk have dependency, without feature_mask to point out specific clk
will make it fail to set some clk.
Fix the function of smu_unforce_dpm_levels.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Gui Chengming <Jack.Gui@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: support sysfs to get socclk, fclk, dcefclk
Likun Gao [Tue, 19 Feb 2019 10:18:46 +0000 (18:18 +0800)]
drm/amd/powerplay: support sysfs to get socclk, fclk, dcefclk

Add sys interface to get socclk, fclk and dcefclk for smu.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Gui Chengming <Jack.Gui@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: add condition for smc table hw init
Likun Gao [Fri, 15 Feb 2019 07:47:26 +0000 (15:47 +0800)]
drm/amd/powerplay: add condition for smc table hw init

Smc table hw init should be skipped for suspend/resume when dpm running.
Unified feature enable and disable function into smu_system_features_control.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: add suspend and resume function for smu
Likun Gao [Thu, 14 Feb 2019 10:35:14 +0000 (18:35 +0800)]
drm/amd/powerplay: add suspend and resume function for smu

Functional the function of smu suspend and resume.
Modified the function of smu_smc_table_hw_init to make it useful for smu
resume.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: add is_dpm_running for SMU11
Chengming Gui [Thu, 14 Feb 2019 07:28:23 +0000 (15:28 +0800)]
drm/amd/powerplay: add is_dpm_running for SMU11

add is_dpm_running function to support smu s3 case.

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: add smu_late_init for SMU11.
Chengming Gui [Wed, 30 Jan 2019 03:38:55 +0000 (11:38 +0800)]
drm/amd/powerplay: add smu_late_init for SMU11.

add smu_late_init to complete smu init sequence for SMU11.

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: set dpm table of vclk/dclk/eclk for smu11 (v2)
Likun Gao [Mon, 28 Jan 2019 04:19:57 +0000 (12:19 +0800)]
drm/amd/powerplay: set dpm table of vclk/dclk/eclk for smu11 (v2)

Set default dpm table fo vclk, dclk and eclk.
Open clk adjust rules for vclk, dclk.

v2: Open clk adjust rules for eclk.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: get eclk/vclk/dclk for smu11
Likun Gao [Mon, 28 Jan 2019 04:04:46 +0000 (12:04 +0800)]
drm/amd/powerplay: get eclk/vclk/dclk for smu11

Get eclk, vclk and dclk info from vbios when hw init for smu11.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: set fan target interface for hwmon
Likun Gao [Fri, 25 Jan 2019 09:45:24 +0000 (17:45 +0800)]
drm/amd/powerplay: set fan target interface for hwmon

Add fan1_target set interface to set fan speed for hwmon.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: implement fan1_enable hwmon interface for SMU11 (v2)
Chengming Gui [Fri, 25 Jan 2019 10:57:34 +0000 (18:57 +0800)]
drm/amd/powerplay: implement fan1_enable hwmon interface for SMU11 (v2)

set the fan1_enable hwmon interface to call
smu_get_fan_control_mode and smu_set_fan_control_mode.

v2: fix print value.

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: implement pwm1_enable hwmon interface for SMU11 (v2)
Chengming Gui [Fri, 25 Jan 2019 08:21:27 +0000 (16:21 +0800)]
drm/amd/powerplay: implement pwm1_enable hwmon interface for SMU11 (v2)

1, set get_pwm1_enable and set_pwm1_enable functions to call
smu_get_fan_control_mode and smu_set_fan_control_mode for SMU11
2, implement set_fan_control_mode function

v2: add return value in set_fan_control_mode function

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: implement pwm1 hwmon interface for SMU11 (v2)
Chengming Gui [Thu, 24 Jan 2019 10:39:04 +0000 (18:39 +0800)]
drm/amd/powerplay: implement pwm1 hwmon interface for SMU11 (v2)

added main functions:
get_fan_speed_percent
set_fan_speed_percent.
added dependent functions:
smc_fan_control
set_fan_static_mode
get_fan_speed_percent

v2: fix coding style issue

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: add STABLE_PSTATE_SCLK and STABLE_PSTATE_MCLK when read sensor...
Chengming Gui [Thu, 24 Jan 2019 09:50:57 +0000 (17:50 +0800)]
drm/amd/powerplay: add STABLE_PSTATE_SCLK and STABLE_PSTATE_MCLK when read sensor for SMU11

add AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK and
AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK to support
read sensor for SMU11.

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Kevin Wang <kevink1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: implement power1_cap and power1_cap_max interface for SMU11 (v2)
Chengming Gui [Tue, 22 Jan 2019 09:56:16 +0000 (17:56 +0800)]
drm/amd/powerplay: implement power1_cap and power1_cap_max interface for SMU11 (v2)

add get_power_limit and set_power_limit functions
to support hwmon for SMU11.

v2: fix the code style issue.

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: add fan input interface for hwmon
Likun Gao [Fri, 25 Jan 2019 09:45:24 +0000 (17:45 +0800)]
drm/amd/powerplay: add fan input interface for hwmon

Add fan1_input and fan1_target interface to get fan speed info for hwmon.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: add fan rpm limit interface for hwmon
Likun Gao [Fri, 25 Jan 2019 10:29:31 +0000 (18:29 +0800)]
drm/amd/powerplay: add fan rpm limit interface for hwmon

Add fan1_min and fan2_max function for hwmon.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: debugfs don't check powerplay when SW SMU is enabled.
Kevin Wang [Mon, 28 Jan 2019 07:14:47 +0000 (15:14 +0800)]
drm/amd/powerplay: debugfs don't check powerplay when SW SMU is enabled.

when sw smu is enabled, the powerplay interface isn't implemented.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: enable amdgpu dpm for smu
Kevin Wang [Fri, 25 Jan 2019 09:33:40 +0000 (17:33 +0800)]
drm/amd/powerplay: enable amdgpu dpm for smu

enable amdgpu dpm global flag

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: add function to get sclk and mclk
Likun Gao [Mon, 28 Jan 2019 11:12:10 +0000 (19:12 +0800)]
drm/amd/powerplay: add function to get sclk and mclk

Add function to get sclk and mclk for smu11.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: Unify smu handle task function (v2)
Likun Gao [Thu, 24 Jan 2019 11:53:40 +0000 (19:53 +0800)]
drm/amd/powerplay: Unify smu handle task function (v2)

Unify power stade adjust function into smu_handle_task by the judgment
of task_id.
Move functions which have no relationship with smu version into the file
of amdgpu_smu.
Modified the function of smu_display_config_changed into two part.
Unify some similiar function.

v2: Correct the operation of upload dpm level when force dpm limit value.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: implement dpm enable functions of uvd & vce for smu
Kevin Wang [Fri, 25 Jan 2019 07:10:13 +0000 (15:10 +0800)]
drm/amd/powerplay: implement dpm enable functions of uvd & vce for smu

add function of dpm enable uvd & vce for extern module use.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: implement sensor of uvd & vce power state for smu11
Kevin Wang [Fri, 25 Jan 2019 08:22:20 +0000 (16:22 +0800)]
drm/amd/powerplay: implement sensor of uvd & vce power state for smu11

add functions of uvd & vce for hwmon.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: implement uvd & vce dpm enable functions
Kevin Wang [Thu, 24 Jan 2019 11:58:11 +0000 (19:58 +0800)]
drm/amd/powerplay: implement uvd & vce dpm enable functions

add dpm enable functions for vce,uvd.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: hwmon don't check powerplay when sw smu is enabled
Kevin Wang [Thu, 24 Jan 2019 11:14:22 +0000 (19:14 +0800)]
drm/amd/powerplay: hwmon don't check powerplay when sw smu is enabled

when sw-smu is enabled, the driver won't init powerplay structure.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: implement update enabled feature state to smc for smu11
Kevin Wang [Thu, 24 Jan 2019 07:27:02 +0000 (15:27 +0800)]
drm/amd/powerplay: implement update enabled feature state to smc for smu11

change:
1.when enable smu feature, the feature id will store sw-bitmap and smu
controller.
2.add feature mutex lock to protect feature bitmap changed when update
feature enabled state.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: dpm clk can be set only when performance level is manual
Likun Gao [Wed, 23 Jan 2019 05:37:39 +0000 (13:37 +0800)]
drm/amd/powerplay: dpm clk can be set only when performance level is manual

Add condition to make dpm clk can not be set when perfomance level isn't
equal to manual.
Add mutex lock to smu when set dpm clk.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>