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8 years agohw/ppc/spapr: Use POWER8 by default for the pseries-2.8 machine
Thomas Huth [Wed, 5 Oct 2016 07:44:51 +0000 (09:44 +0200)]
hw/ppc/spapr: Use POWER8 by default for the pseries-2.8 machine

A couple of distributors are compiling their distributions
with "-mcpu=power8" for ppc64le these days, so the user sooner
or later runs into a crash there when not explicitely specifying
the "-cpu POWER8" option to QEMU (which is currently using POWER7
for the "pseries" machine by default). Due to this reason, the
linux-user target already switched to POWER8 a while ago (see commit
de3f1b98410e0d5b406a0df3a48547b559d18602). Since the softmmu target
of course has the same problem, we should switch there to POWER8 for
the newer machine types, too.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
8 years agotests/pxe: Use -nodefaults to speed up ppc64/ipv6 pxe test
Thomas Huth [Wed, 5 Oct 2016 12:52:09 +0000 (14:52 +0200)]
tests/pxe: Use -nodefaults to speed up ppc64/ipv6 pxe test

SLOF is unfortunately quite slow when running with TCG, so
the pxe test is also performing rather slow here. By using
"-nodefaults" we can disable some devices (vscsi) that we
are not interested in here, so that SLOF does not have to
scan them during boot and thus starts up a little bit faster.
The ppc64 pxe-test now only takes 27 seconds on my laptop
instead of 33 seconds.
The "-nodefaults" flag seems to work fine for the x86 tests,
too, so it is added here unconditionally here (though there
is no speed-up on x86 by using this flag).

Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Laurent Vivier <lvivier@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
8 years agospapr: fix check of cpu alias name in spapr_get_cpu_core_type()
Greg Kurz [Mon, 3 Oct 2016 12:13:20 +0000 (14:13 +0200)]
spapr: fix check of cpu alias name in spapr_get_cpu_core_type()

If the user passes an alias name and a property to -cpu, QEMU fails to
find the CPU definition and exits.

$ qemu-system-ppc64 -cpu POWER8E,compat=power7
qemu-system-ppc64: Unable to find sPAPR CPU Core definition

This happens because spapr_get_cpu_core_type() passes the full string from
the command line (i.e. "POWER8E,compat=power7") to ppc_cpu_lookup_alias(),
instead of the alias name piece only (i.e. "POWER8E").

The fix is to pass model_pieces[0] to ppc_cpu_lookup_alias().

Signed-off-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
8 years agotests: enable ohci/uhci/xhci tests on PPC64
Laurent Vivier [Thu, 29 Sep 2016 10:32:47 +0000 (12:32 +0200)]
tests: enable ohci/uhci/xhci tests on PPC64

Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
8 years agolibqos: use generic qtest_shutdown()
Laurent Vivier [Thu, 29 Sep 2016 10:32:46 +0000 (12:32 +0200)]
libqos: use generic qtest_shutdown()

Machine specific shutdown function can be registered by
the machine specific qtest_XXX_boot() if needed.

So we will not have to test twice the architecture (on boot and on
shutdown) if the test can be run on several architectures.

Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
8 years agolibqos: add PCI management in qtest_vboot()/qtest_shutdown()
Laurent Vivier [Thu, 29 Sep 2016 10:32:45 +0000 (12:32 +0200)]
libqos: add PCI management in qtest_vboot()/qtest_shutdown()

Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
8 years agolibqos: add PPC64 PCI support
Laurent Vivier [Thu, 29 Sep 2016 10:32:44 +0000 (12:32 +0200)]
libqos: add PPC64 PCI support

Signed-off-by: Laurent Vivier <lvivier@redhat.com>
[dwg: Fixed build problem on 32-bit hosts]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
8 years agotarget-ppc: fix vmx instruction type/type2
Nikunj A Dadhania [Thu, 29 Sep 2016 10:22:37 +0000 (15:52 +0530)]
target-ppc: fix vmx instruction type/type2

A few of the new instructions added inadvertently changed the type of
old instruction(PPC_ALTIVEC) to PPC2_ALTIVEC_207 in the dual form
declaration.

commit: b5d569a1 (target-ppc: add vector extract instructions)
commit: e7b1e06f (target-ppc: add vector insert instructions)
commit: 3aa56a19 (target-ppc: add vector compare not equal instructions)

New ISA 3.0 instructions added:
    vextractub     PPC_NONE     PPC2_ISA300
    vextractuh     PPC_NONE     PPC2_ISA300
    vextractuw     PPC_NONE     PPC2_ISA300
    vinsertb       PPC_NONE     PPC2_ISA300
    vinserth       PPC_NONE     PPC2_ISA300
    vinsertw       PPC_NONE     PPC2_ISA300
    vcmpneb        PPC_NONE     PPC2_ISA300
    vcmpneh        PPC_NONE     PPC2_ISA300
    vcmpnew        PPC_NONE     PPC2_ISA300

Affected older instructions:
    vspltb         PPC_ALTIVEC  PPC_NONE
    vsplth         PPC_ALTIVEC  PPC_NONE
    vspltw         PPC_ALTIVEC  PPC_NONE
    vspltisb       PPC_ALTIVEC  PPC_NONE
    vspltish       PPC_ALTIVEC  PPC_NONE
    vspltisw       PPC_ALTIVEC  PPC_NONE
    vcmpequb       PPC_ALTIVEC  PPC_NONE
    vcmpequh       PPC_ALTIVEC  PPC_NONE
    vcmpequw       PPC_ALTIVEC  PPC_NONE

Change the instruction type/type2 for the older instructions back to
what it was(PPC_ALTIVEC).

CC: Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com>
Reported-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
8 years agotarget-ppc/kvm: Enable transactional memory on POWER8 with KVM-HV, too
Thomas Huth [Thu, 29 Sep 2016 10:48:07 +0000 (12:48 +0200)]
target-ppc/kvm: Enable transactional memory on POWER8 with KVM-HV, too

Transactional memory is also supported on POWER8 KVM-HV if the
KVM_CAP_PPC_HTM is not available in the kernel yet, so add a hack
to allow TM here, too.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
8 years agotarget-ppc/kvm: Add a wrapper function to check for KVM-PR
Thomas Huth [Thu, 29 Sep 2016 10:48:06 +0000 (12:48 +0200)]
target-ppc/kvm: Add a wrapper function to check for KVM-PR

It makes more sense if we have a proper function to check
for KVM-PR than to check for the GET_PVINFO extension all
over the place.

Signed-off-by: Thomas Huth <thuth@redhat.com>
[dwg: Expanded a comment to discourage overuse of this function]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
8 years agoMAINTAINERS: Add two more ppc related files
Thomas Huth [Thu, 29 Sep 2016 07:40:33 +0000 (09:40 +0200)]
MAINTAINERS: Add two more ppc related files

The file hw/intc/heathrow_pic.c belongs to the Old World Mac
machine, and pc-bios/ppc_rom.bin belongs to the PReP machine.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
8 years agotarget-ppc: Implement mtvsrws instruction
Ravi Bangoria [Thu, 29 Sep 2016 03:52:17 +0000 (09:22 +0530)]
target-ppc: Implement mtvsrws instruction

mtvsrws: Move To VSR Word & Splat

Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
8 years agotarget-ppc: add vclzlsbb/vctzlsbb instructions
Rajalakshmi Srinivasaraghavan [Wed, 28 Sep 2016 05:45:18 +0000 (11:15 +0530)]
target-ppc: add vclzlsbb/vctzlsbb instructions

The following vector instructions are added from ISA 3.0.

vclzlsbb - Vector Count Leading Zero Least-Significant Bits Byte
vctzlsbb - Vector Count Trailing Zero Least-Significant Bits Byte

Signed-off-by: Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
8 years agotarget-ppc: add vector compare not equal instructions
Rajalakshmi Srinivasaraghavan [Wed, 28 Sep 2016 05:45:17 +0000 (11:15 +0530)]
target-ppc: add vector compare not equal instructions

The following vector compare not equal instructions are added from ISA 3.0.

vcmpneb - Vector Compare Not Equal Byte
vcmpneh - Vector Compare Not Equal Halfword
vcmpnew - Vector Compare Not Equal Word

Signed-off-by: Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
8 years agotarget-ppc: fix invalid mask - cmpl, bctar
Avinesh Kumar [Wed, 28 Sep 2016 05:45:16 +0000 (11:15 +0530)]
target-ppc: fix invalid mask - cmpl, bctar

cmpl:  invalid bit mask should be 0x00400001
bctar: invalid bit mask should be 0x0000E000

Signed-off-by: Avinesh Kumar <avinesku@linux.vnet.ibm.com>
Signed-off-by: Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
8 years agotarget-ppc: add stxvb16x instruction
Nikunj A Dadhania [Wed, 28 Sep 2016 18:42:00 +0000 (00:12 +0530)]
target-ppc: add stxvb16x instruction

stxvb16x: Store VSX Vector Byte*16

Vector (8-bit elements):
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
|F0|F1|F2|F3|F4|F5|F6|F7|E0|E1|E2|E3|E4|E5|E6|E7|
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+

Store results in following:

Little/Big-endian Storage
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
|F0|F1|F2|F3|F4|F5|F6|F7|E0|E1|E2|E3|E4|E5|E6|E7|
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
8 years agotarget-ppc: add lxvb16x instruction
Nikunj A Dadhania [Wed, 28 Sep 2016 18:41:59 +0000 (00:11 +0530)]
target-ppc: add lxvb16x instruction

lxvb16x: Load VSX Vector Byte*16

Little/Big-endian Storage
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
|F0|F1|F2|F3|F4|F5|F6|F7|E0|E1|E2|E3|E4|E5|E6|E7|
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+

Vector load results in (8-bit elements):
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
|F0|F1|F2|F3|F4|F5|F6|F7|E0|E1|E2|E3|E4|E5|E6|E7|
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
8 years agotarget-ppc: add stxvh8x instruction
Nikunj A Dadhania [Wed, 28 Sep 2016 18:41:58 +0000 (00:11 +0530)]
target-ppc: add stxvh8x instruction

stxvh8x:  Store VSX Vector Halfword*8

Vector (16-bit elements):
+------+------+------+------+------+------+------+------+
| 0001 | 1011 | 2021 | 3031 | 4041 | 5051 | 6061 | 7071 |
+------+------+------+------+------+------+------+------+

Store results in following:

Big-Endian Storage
+-------+-------+-------+-------+-------+-------+-------+-------+
| 00 01 | 10 11 | 20 21 | 30 31 | 40 41 | 50 51 | 60 61 | 70 71 |
+-------+-------+-------+-------+-------+-------+-------+-------+

Little-Endian Storage
+-------+-------+-------+-------+-------+-------+-------+-------+
| 01 00 | 11 10 | 21 20 | 31 30 | 41 40 | 51 50 | 61 60 | 71 70 |
+-------+-------+-------+-------+-------+-------+-------+-------+

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
[dwg: Tweak commit description]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
8 years agotarget-ppc: add lxvh8x instruction
Nikunj A Dadhania [Wed, 28 Sep 2016 18:41:57 +0000 (00:11 +0530)]
target-ppc: add lxvh8x instruction

lxvh8x:  Load VSX Vector Halfword*8

Big-Endian Storage
+-------+-------+-------+-------+-------+-------+-------+-------+
| 00 01 | 10 11 | 20 21 | 30 31 | 40 41 | 50 51 | 60 61 | 70 71 |
+-------+-------+-------+-------+-------+-------+-------+-------+

Little-Endian Storage
+-------+-------+-------+-------+-------+-------+-------+-------+
| 01 00 | 11 10 | 21 20 | 31 30 | 41 40 | 51 50 | 61 60 | 71 70 |
+-------+-------+-------+-------+-------+-------+-------+-------+

Vector load results in (16-bit elements):
+------+------+------+------+------+------+------+------+
| 0001 | 1011 | 2021 | 3031 | 4041 | 5051 | 6061 | 7071 |
+------+------+------+------+------+------+------+------+

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
[dwg: Tweak to commit description]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
8 years agotarget-ppc: improve stxvw4x implementation
Nikunj A Dadhania [Wed, 28 Sep 2016 18:41:56 +0000 (00:11 +0530)]
target-ppc: improve stxvw4x implementation

Manipulate data and store 8bytes instead of 4bytes.

Vector (32-bit elements):
+----------+----------+----------+----------+
00112233 | 44556677 | 8899AABB | CCDDEEFF |
+----------+----------+----------+----------+

Store results in following:

Big-Endian Storage
+-------------+-------------+-------------+-------------+
| 00 11 22 33 | 44 55 66 77 | 88 99 AA BB | CC DD EE FF |
+-------------+-------------+-------------+-------------+

Little-Endian Storage
+-------------+-------------+-------------+-------------+
| 33 22 11 00 | 77 66 55 44 | BB AA 99 88 | FF EE DD CC |
+-------------+-------------+-------------+-------------+

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
8 years agotarget-ppc: improve lxvw4x implementation
Nikunj A Dadhania [Wed, 28 Sep 2016 18:41:55 +0000 (00:11 +0530)]
target-ppc: improve lxvw4x implementation

Load 8byte at a time and manipulate.

Big-Endian Storage
+-------------+-------------+-------------+-------------+
| 00 11 22 33 | 44 55 66 77 | 88 99 AA BB | CC DD EE FF |
+-------------+-------------+-------------+-------------+

Little-Endian Storage
+-------------+-------------+-------------+-------------+
| 33 22 11 00 | 77 66 55 44 | BB AA 99 88 | FF EE DD CC |
+-------------+-------------+-------------+-------------+

Vector load results in (32-bit elements):
+----------+----------+----------+----------+
00112233 | 44556677 | 8899AABB | CCDDEEFF |
+----------+----------+----------+----------+

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
[dwg: Slight tweak to commit description]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
8 years agotarget-ppc: Implement mtvsrdd instruction
Ravi Bangoria [Wed, 28 Sep 2016 18:41:53 +0000 (00:11 +0530)]
target-ppc: Implement mtvsrdd instruction

mtvsrdd: Move To VSR Double Doubleword

Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
8 years agotarget-ppc: Implement mfvsrld instruction
Ravi Bangoria [Wed, 28 Sep 2016 18:41:52 +0000 (00:11 +0530)]
target-ppc: Implement mfvsrld instruction

mfvsrld: Move From VSR Lower Doubleword

Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
8 years agoppc: Check the availability of transactional memory
Thomas Huth [Wed, 28 Sep 2016 11:16:30 +0000 (13:16 +0200)]
ppc: Check the availability of transactional memory

KVM-PR currently does not support transactional memory, and the
implementation in TCG is just a fake. We should not announce TM
support in the ibm,pa-features property when running on such a
system, so disable it by default and only enable it if the KVM
implementation supports it (i.e. recent versions of KVM-HV).
These changes are based on some earlier work from Anton Blanchard
(thanks!).

Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
8 years agohw/ppc/spapr: Fix the selection of the processor features
Thomas Huth [Wed, 28 Sep 2016 11:16:29 +0000 (13:16 +0200)]
hw/ppc/spapr: Fix the selection of the processor features

The current code uses pa_features_206 for POWERPC_MMU_2_06, and
for everything else, it uses pa_features_207. This is bad in some
cases because there is also a "degraded" MMU version of ISA 2.06,
called POWERPC_MMU_2_06a, which should of course use the flags for
2.06 instead. And there is also the possibility that the user runs
the pseries machine with a POWER5+ or even 970 processor. In that
case we certainly do not want to set the flags for 2.07, and rather
simply skip the setting of the pa-features property instead.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
8 years agohw/ppc/spapr: Move code related to "ibm,pa-features" to a separate function
Thomas Huth [Wed, 28 Sep 2016 11:16:28 +0000 (13:16 +0200)]
hw/ppc/spapr: Move code related to "ibm,pa-features" to a separate function

The function spapr_populate_cpu_dt() has become quite big
already, and since we likely have to extend the pa-features
property for every new processor generation, it is nicer
if we put the related code into a separate function.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
8 years agopseries: Add 2.8 machine type, set up compatibility macros
David Gibson [Wed, 28 Sep 2016 04:31:55 +0000 (14:31 +1000)]
pseries: Add 2.8 machine type, set up compatibility macros

Now that 2.7 is released, create the pseries-2.8 machine type and add the
boilerplate compatiblity macro stuff.  There's nothing new to put into the
2.7 compatiliby properties yet, but we'll need something eventually, so
we might as well get it ready now.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
8 years agotests: Test IPv6 and ppc64 in the PXE tester
Thomas Huth [Mon, 26 Sep 2016 20:17:46 +0000 (22:17 +0200)]
tests: Test IPv6 and ppc64 in the PXE tester

The firmware of the pseries machine, SLOF, is able to load files via
IPv6 networking, too. So to test both, network bootloading on ppc64
and IPv6 (via Slirp) , let's add some PXE tests for this environment,
too. Since we can not use the normal x86 boot sector for network boot
loading, we use a simple Forth script on ppc64 instead.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
8 years agospapr_vscsi: fix build error introduced by f19661c8
Felipe Franciosi [Mon, 26 Sep 2016 14:17:44 +0000 (15:17 +0100)]
spapr_vscsi: fix build error introduced by f19661c8

A typo introduced in f19661c8 prevents qemu from building when configured
with --enable-trace-backend=dtrace.

Signed-off-by: Felipe Franciosi <felipe@nutanix.com>
Reviewed-by: Laurent Vivier <lvivier@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
8 years agoMerge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging
Peter Maydell [Tue, 4 Oct 2016 13:25:08 +0000 (14:25 +0100)]
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging

Block layer patches

# gpg: Signature made Thu 29 Sep 2016 14:11:30 BST
# gpg:                using RSA key 0x7F09B272C88F2FD6
# gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>"
# Primary key fingerprint: DC3D EB15 9A9A F95D 3D74  56FE 7F09 B272 C88F 2FD6

* remotes/kevin/tags/for-upstream:
  oslib-posix: add a configure switch to debug stack usage
  coroutine-sigaltstack: use helper for allocating stack memory
  coroutine-ucontext: use helper for allocating stack memory
  coroutine: add a macro for the coroutine stack size
  coroutine-sigaltstack: rename coroutine struct appropriately
  oslib-posix: add helpers for stack alloc and free
  block: Remove qemu_root_bds_opts
  block: Move 'discard' option to bdrv_open_common()
  block: Use 'detect-zeroes' option for 'blockdev-change-medium'
  block: Parse 'detect-zeroes' in bdrv_open_common()
  block/qapi: Move 'aio' option to file driver
  block/qapi: Use separate options type for curl driver
  block: Drop aio/cache consistency check from qmp_blockdev_add()
  block: Fix error path in qmp_blockdev_change_medium()
  block-backend: remove blk_flush_all
  qemu: use bdrv_flush_all for vm_stop et al
  block: reintroduce bdrv_flush_all

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agoMerge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20161004' into...
Peter Maydell [Tue, 4 Oct 2016 12:48:25 +0000 (13:48 +0100)]
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20161004' into staging

target-arm queue:
 * Netduino 2 improvements (SPI, ADC devices)
 * fix some Mainstone key mappings
 * vmstateify tsc210x, tsc2005
 * virt: add 2.8 machine type
 * virt: support in-kernel GICv3 ITS
 * generic-loader device
 * A64: fix iss_sf decoding in disas_ld_lit
 * correctly handle 'sub pc, pc, 1' for ARMv6

# gpg: Signature made Tue 04 Oct 2016 13:41:34 BST
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20161004: (27 commits)
  target-arm: Correctly handle 'sub pc, pc, 1' for ARMv6
  target-arm: A64: Fix decoding of iss_sf in disas_ld_lit
  cadence_gem: Fix priority queue out of bounds access
  docs: Add a generic loader explanation document
  generic-loader: Add a generic loader
  ARM: Virt: ACPI: Add GIC ITS description in ACPI MADT table
  ACPI: Add GIC Interrupt Translation Service Structure definition
  arm/virt: Add ITS to the virt board
  hw/intc/arm_gicv3_its: Implement support for in-kernel ITS emulation
  kvm-all: Pass requester ID to MSI routing functions
  target-arm: move gicv3_class_name from machine to kvm_arm.h
  hw/intc/arm_gicv3_its: Implement ITS base class
  hw/intc/arm_gic(v3)_kvm: Initialize gsi routing
  hw/arm/virt: add 2.8 machine type
  vmstateify tsc210x
  vmstateify tsc2005
  hw/arm: Fix Integrator/CM initialization
  mainstone: Add mapping for dot, slash and backspace.
  mainstone: Fix incorrect key mapping for Enter key.
  MAINTAINERS: Add Alistair to the maintainers list
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agotarget-arm: Correctly handle 'sub pc, pc, 1' for ARMv6
Peter Maydell [Tue, 4 Oct 2016 12:28:10 +0000 (13:28 +0100)]
target-arm: Correctly handle 'sub pc, pc, 1' for ARMv6

In the ARM v6 architecture, 'sub pc, pc, 1' is not an interworking
branch, so the computed new value is written to r15 as a normal
value. The architecture says that in this case, bits [1:0] of
the value written must be ignored if we are in ARM mode (or
bit [0] ignored if in Thumb mode); this is a change from the
ARMv4/v5 specification that behaviour is UNPREDICTABLE.
Use the correct mask on the PC value when doing a non-interworking
store to PC.

A popular library used on RaspberryPi uses this instruction
as part of a trick to determine whether it is running on
ARMv6 or ARMv7, and we were mishandling the sequence.

Fixes bug: https://bugs.launchpad.net/bugs/1625295

Reported-by: <stu.axon@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1474380941-4730-1-git-send-email-peter.maydell@linaro.org

8 years agotarget-arm: A64: Fix decoding of iss_sf in disas_ld_lit
Edgar E. Iglesias [Tue, 4 Oct 2016 12:28:10 +0000 (13:28 +0100)]
target-arm: A64: Fix decoding of iss_sf in disas_ld_lit

Fix the decoding of iss_sf in disas_ld_lit.
The SF (Sixty-Four) field in the ISS (Instruction Specific Syndrome)
is a bit that specifies the width of the register that the
instruction loads to.

If cleared it specifies 32 bits.
If set it specifies 64 bits.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1475230780-8669-1-git-send-email-edgar.iglesias@gmail.com
[PMM: tweaked phrasing per on-list discussion]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agocadence_gem: Fix priority queue out of bounds access
Alistair Francis [Tue, 4 Oct 2016 12:28:09 +0000 (13:28 +0100)]
cadence_gem: Fix priority queue out of bounds access

There was an error with some of the register implementation assuming
there are 16 priority queues supported when the IP only supports 8. This
patch corrects the registers to only support 8 queues.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reported-by: Paolo Bonzini <pbonzini@redhat.com>
Message-id: 33bf2d28326d22875602234b8b15cf56fb678333.1474911607.git.alistair.francis@xilinx.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agodocs: Add a generic loader explanation document
Alistair Francis [Tue, 4 Oct 2016 12:28:09 +0000 (13:28 +0100)]
docs: Add a generic loader explanation document

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 9d991a2df990cf55e2630410a5a03ea48930af5d.1475195078.git.alistair.francis@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agogeneric-loader: Add a generic loader
Alistair Francis [Tue, 4 Oct 2016 12:28:09 +0000 (13:28 +0100)]
generic-loader: Add a generic loader

Add a generic loader to QEMU which can be used to load images or set
memory values.

Internally inside QEMU this is a device. It is a strange device that
provides no hardware interface but allows QEMU to monkey patch memory
specified when it is created. To be able to do this it has a reset
callback that does the memory operations.

This device allows the user to monkey patch memory. To be able to do
this it needs a backend to manage the datas, the same as other
memory-related devices. In this case as the backend is so trivial we
have merged it with the frontend instead of creating and maintaining a
seperate backend.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Markus Armbruster <armbru@redhat.com>
Message-id: 10f2a9dce5e5e11b6c6d959415b0ad6ee22bcba5.1475195078.git.alistair.francis@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agoARM: Virt: ACPI: Add GIC ITS description in ACPI MADT table
Shannon Zhao [Tue, 4 Oct 2016 12:28:09 +0000 (13:28 +0100)]
ARM: Virt: ACPI: Add GIC ITS description in ACPI MADT table

If GIC ITS is supported, add description in ACPI MADT table, then guest
could use ITS when booting with ACPI.

Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1474616617-366-9-git-send-email-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agoACPI: Add GIC Interrupt Translation Service Structure definition
Shannon Zhao [Tue, 4 Oct 2016 12:28:09 +0000 (13:28 +0100)]
ACPI: Add GIC Interrupt Translation Service Structure definition

ACPI Spec 6.0 introduces GIC Interrupt Translation Service Structure.
Here we add the definition of the Structure.

Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1474616617-366-8-git-send-email-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agoarm/virt: Add ITS to the virt board
Pavel Fedin [Tue, 4 Oct 2016 12:28:09 +0000 (13:28 +0100)]
arm/virt: Add ITS to the virt board

If supported by the configuration, ITS will be added automatically.

This patch also renames v2m_phandle to msi_phandle because it's now used
by both MSI implementations.

Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1474616617-366-7-git-send-email-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agohw/intc/arm_gicv3_its: Implement support for in-kernel ITS emulation
Pavel Fedin [Tue, 4 Oct 2016 12:28:09 +0000 (13:28 +0100)]
hw/intc/arm_gicv3_its: Implement support for in-kernel ITS emulation

The ITS control frame is in-kernel emulated while accesses to the
GITS_TRANSLATER are mediated through the KVM_SIGNAL_MSI ioctl (MSI
direct MSI injection advertised by the CAP_SIGNAL_MSI capability)

the kvm_gsi_direct_mapping is explicitly set to false to emphasize the
difference with GICv2M. Direct mapping cannot work with ITS since
the content of the MSI data is not the target interrupt ID but an
eventd id.

GSI routing is advertised (kvm_gsi_routing_allowed) as well as
msi/irqfd signaling (kvm_msi_via_irqfd_allowed).

The MSI frame (GITS_TRANSLATER) absolute GPA is computed on first
kvm_its_send_msi() call. It is then passed through KVM_SIGNAL_MSI
ioctl.

Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1474616617-366-6-git-send-email-eric.auger@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agokvm-all: Pass requester ID to MSI routing functions
Pavel Fedin [Tue, 4 Oct 2016 12:28:09 +0000 (13:28 +0100)]
kvm-all: Pass requester ID to MSI routing functions

Introduce global kvm_msi_use_devid flag plus associated
kvm_msi_devid_required() macro. Passes the device ID,
if needed, while building the MSI route entry. Device IDs are
required by the ARM GICv3 ITS (IRQ remapping function is based on
this information).

Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1474616617-366-5-git-send-email-eric.auger@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agotarget-arm: move gicv3_class_name from machine to kvm_arm.h
Eric Auger [Tue, 4 Oct 2016 12:28:08 +0000 (13:28 +0100)]
target-arm: move gicv3_class_name from machine to kvm_arm.h

Machine.c contains code related to migration. Let's move
gicv3_class_name to kvm_arm.h instead.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1474616617-366-4-git-send-email-eric.auger@redhat.com
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agohw/intc/arm_gicv3_its: Implement ITS base class
Pavel Fedin [Tue, 4 Oct 2016 12:28:08 +0000 (13:28 +0100)]
hw/intc/arm_gicv3_its: Implement ITS base class

This is the basic skeleton for both KVM and software-emulated ITS.
Since we already prepare status structure, we also introduce complete
VMState description. But, because we currently have no migratable
implementations, we also set unmigratable flag.

Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1474616617-366-3-git-send-email-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agohw/intc/arm_gic(v3)_kvm: Initialize gsi routing
Eric Auger [Tue, 4 Oct 2016 12:28:08 +0000 (13:28 +0100)]
hw/intc/arm_gic(v3)_kvm: Initialize gsi routing

Advertise gsi routing and set up irqchip routing entries for
GIC SPIs.

This is not mandated as long as MSI routing is not used
(because the kernel sets a default irqchip routing table).
However once MSI routing gets used (for VIRTIO-PCI vhost for
example), the first call to KVM_SET_GSI_ROUTING overrides the
kernel default irqchip table.

If no routing entry exists for the GSI, any IRQFD signaling for
this GSI will fail.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1474616617-366-2-git-send-email-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agohw/arm/virt: add 2.8 machine type
Andrew Jones [Tue, 4 Oct 2016 12:28:08 +0000 (13:28 +0100)]
hw/arm/virt: add 2.8 machine type

Signed-off-by: Andrew Jones <drjones@redhat.com>
Message-id: 1474641676-25017-1-git-send-email-drjones@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agovmstateify tsc210x
Dr. David Alan Gilbert [Tue, 4 Oct 2016 12:28:08 +0000 (13:28 +0100)]
vmstateify tsc210x

I'm now saving all 3 of the pll entries; only 2 were saved before.
There are a couple of times that were previously stored as offsets
from 'now' calculated before saving;  with vmstate it's easier
to store the 'now' and fix it up on reload.

Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Message-id: 1474977735-10156-3-git-send-email-dgilbert@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agovmstateify tsc2005
Dr. David Alan Gilbert [Tue, 4 Oct 2016 12:28:08 +0000 (13:28 +0100)]
vmstateify tsc2005

I've converted the fields in it's main data structure
to fixed size types in ways that look sane.

Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Message-id: 1474977735-10156-2-git-send-email-dgilbert@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agohw/arm: Fix Integrator/CM initialization
Jakub Jermar [Tue, 4 Oct 2016 12:28:08 +0000 (13:28 +0100)]
hw/arm: Fix Integrator/CM initialization

Initialization of a class instance cannot depend on its own properties
as these are not yet set.  Move parts of integratorcm_init() that depend
on the "memsz" property to the newly added integratorcm_realize().

This fixes: https://bugs.launchpad.net/qemu/+bug/1624726

Signed-off-by: Jakub Jermar <jakub@jermar.eu>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agomainstone: Add mapping for dot, slash and backspace.
Vijay Kumar B [Tue, 4 Oct 2016 12:28:08 +0000 (13:28 +0100)]
mainstone: Add mapping for dot, slash and backspace.

Add missed out mappings. These mappings are from the "Intel PXA27x
Processor Developer's Kit User Guide".

Signed-off-by: Vijay Kumar B. <vijaykumar@zilogic.com>
Reviewed-by: Deepak S. <deepak@zilogic.com>
Message-id: 1475063033-8176-3-git-send-email-vijaykumar@zilogic.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agomainstone: Fix incorrect key mapping for Enter key.
Vijay Kumar B [Tue, 4 Oct 2016 12:28:07 +0000 (13:28 +0100)]
mainstone: Fix incorrect key mapping for Enter key.

According to the manual the (5, 5) corresponds to backspace key, and
not Enter key. Linux kernel maps (5, 4) to the enter key. Fixing it up
to match the mapping in the Linux kernel.

Signed-off-by: Vijay Kumar B. <vijaykumar@zilogic.com>
Reviewed-by: Deepak S. <deepak@zilogic.com>
Message-id: 1475063033-8176-2-git-send-email-vijaykumar@zilogic.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agoMAINTAINERS: Add Alistair to the maintainers list
Alistair Francis [Tue, 4 Oct 2016 12:28:07 +0000 (13:28 +0100)]
MAINTAINERS: Add Alistair to the maintainers list

Add Alistair Francis as the maintainer for the Netduino 2
and SMM32F205 SoC.

Signed-off-by: Alistair Francis <alistair@alistair23.me>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 5a46ccf398b050a41cc3b3d0e94bcff4ce2d85e0.1474742262.git.alistair@alistair23.me
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agoSTM32F205: Connect the SPI devices
Alistair Francis [Tue, 4 Oct 2016 12:28:07 +0000 (13:28 +0100)]
STM32F205: Connect the SPI devices

Connect the SPI devices to the STM32F205 SoC.

Signed-off-by: Alistair Francis <alistair@alistair23.me>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: d05849120420f8db0d9aa053bd23134c33cd9180.1474742262.git.alistair@alistair23.me
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agoSTM32F205: Connect the ADC devices
Alistair Francis [Tue, 4 Oct 2016 12:28:07 +0000 (13:28 +0100)]
STM32F205: Connect the ADC devices

Connect the ADC devices to the STM32F205 SoC.

Signed-off-by: Alistair Francis <alistair@alistair23.me>
Message-id: 6214eda399da7b47014f6f895be25323d52dbc9e.1474742262.git.alistair@alistair23.me
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agoirq: Add a new irq device that allows the ORing of lines
Alistair Francis [Tue, 4 Oct 2016 12:28:07 +0000 (13:28 +0100)]
irq: Add a new irq device that allows the ORing of lines

Signed-off-by: Alistair Francis <alistair@alistair23.me>
Message-id: 52e5d361e3b5a0ea8554aca73ee65ae2b586112e.1474742262.git.alistair@alistair23.me
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agoSTM32F2xx: Add the SPI device
Alistair Francis [Tue, 4 Oct 2016 12:28:07 +0000 (13:28 +0100)]
STM32F2xx: Add the SPI device

Add the STM32F2xx SPI device.

Signed-off-by: Alistair Francis <alistair@alistair23.me>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 8197811d5c94f814fa67c6a33ca2f7fd0aa97432.1474742262.git.alistair@alistair23.me
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agoSTM32F2xx: Add the ADC device
Alistair Francis [Tue, 4 Oct 2016 12:28:07 +0000 (13:28 +0100)]
STM32F2xx: Add the ADC device

Add the STM32F2xx ADC device. This device randomly
generates values on each read.

This also includes creating a hw/adc directory.

Signed-off-by: Alistair Francis <alistair@alistair23.me>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 3240e660adaf537f55a63ce06096e844aece8cda.1474742262.git.alistair@alistair23.me
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agoSTM32F2xx: Display PWM duty cycle from timer
Alistair Francis [Tue, 4 Oct 2016 12:28:07 +0000 (13:28 +0100)]
STM32F2xx: Display PWM duty cycle from timer

If correctly configured allow the STM32F2xx timer to print
out the PWM duty cycle information.

Signed-off-by: Alistair Francis <alistair@alistair23.me>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: cdb59039a25e061615713a94b40797baa12ea9f9.1474742262.git.alistair@alistair23.me
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agoSTM32F205: Remove the individual device variables
Alistair Francis [Tue, 4 Oct 2016 12:28:06 +0000 (13:28 +0100)]
STM32F205: Remove the individual device variables

Cleanup the individual DeviceState and SysBusDevice
variables to re-use the same variable for each
device.

Signed-off-by: Alistair Francis <alistair@alistair23.me>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: fc5d75a57d320b69704df2c1146ff0fd482e4a88.1474742262.git.alistair@alistair23.me
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agoMerge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into staging
Peter Maydell [Tue, 4 Oct 2016 10:28:30 +0000 (11:28 +0100)]
Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into staging

x86 bug fixes

Fix for a XSAVE regression when using "-cpu host", and a fix on
the Opteron_G3 CPU model.

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* remotes/ehabkost/tags/x86-pull-request:
  target-i386: Correct family/model/stepping for Opteron_G3
  target-i386: Report known CPUID[EAX=0xD,ECX=0]:EAX bits as migratable

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agoMerge remote-tracking branch 'remotes/famz/tags/for-upstream' into staging
Peter Maydell [Tue, 4 Oct 2016 10:01:39 +0000 (11:01 +0100)]
Merge remote-tracking branch 'remotes/famz/tags/for-upstream' into staging

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* remotes/famz/tags/for-upstream:
  docker: Build in a clean directory
  smbios: fix uuid copy
  xenpv: Fix qemu_uuid compiling error

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agotarget-i386: Correct family/model/stepping for Opteron_G3
Evgeny Yakovlev [Mon, 3 Oct 2016 11:50:02 +0000 (14:50 +0300)]
target-i386: Correct family/model/stepping for Opteron_G3

Current CPU definition for AMD Opteron third generation includes
features like SSE4a and LAHF_LM support in emulated CPUID. These
features are present in K8 rev.E or K10 CPUs and later. However,
current G3 family and model describe 2nd generation K8 cores instead.

This is incorrect but was considered harmless until our tests found a
problem with linux kernels >= 3.10 (and maybe earlier) which specifically
check for Opteron K8 model when parsing CPUID leaf 0x80000001:
http://lxr.free-electrons.com/source/arch/x86/kernel/cpu/amd.c?v=3.16#L552
This code will disable LAHF_LM feature in /proc/cpuinfo if model number
is inconsistent.

This change sets Opteron_G3 family/model/stepping to 16/2/3 which is
a proper Opteron 3rd generation 2350 CPU.

Signed-off-by: Evgeny Yakovlev <eyakovlev@virtuozzo.com>
Signed-off-by: Denis V. Lunev <den@openvz.org>
CC: Paolo Bonzini <pbonzini@redhat.com>
CC: Richard Henderson <rth@twiddle.net>
CC: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
8 years agotarget-i386: Report known CPUID[EAX=0xD,ECX=0]:EAX bits as migratable
Eduardo Habkost [Wed, 28 Sep 2016 15:00:29 +0000 (12:00 -0300)]
target-i386: Report known CPUID[EAX=0xD,ECX=0]:EAX bits as migratable

A regression was introduced by commit 96193c22a "target-i386:
Move xsave component mask to features array": all
CPUID[EAX=0xD,ECX=0]:EAX bits were being reported as unmigratable
because they don't have feature names defined. This broke
"-cpu host" because it enables only migratable features by
default.

This adds a new field to FeatureWordInfo: migratable_flags, which
will make those features be reported as migratable even if they
don't have a property name defined.

Reported-by: Wanpeng Li <wanpeng.li@hotmail.com>
Cc: Paolo Bonzini <bonzini@gnu.org>
Reviewed-by: Wanpeng Li <wanpeng.li@hotmail.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
8 years agodocker: Build in a clean directory
Fam Zheng [Wed, 28 Sep 2016 07:31:32 +0000 (15:31 +0800)]
docker: Build in a clean directory

Currently we configure and build under "$QEMU_SRC/tests/docker" which is
dubious. Create a fixed directory (to be friendly to ccache) and change
to there before calling build_qemu.

Signed-off-by: Fam Zheng <famz@redhat.com>
Message-Id: <1475047892-11955-1-git-send-email-famz@redhat.com>

8 years agoMerge remote-tracking branch 'remotes/borntraeger/tags/s390x-20160927' into staging
Peter Maydell [Fri, 30 Sep 2016 22:45:56 +0000 (23:45 +0100)]
Merge remote-tracking branch 'remotes/borntraeger/tags/s390x-20160927' into staging

Couple of s390x patches:
- some PCI cleanups
- fix build error due to uuid rework
- fix potential deadlock in sigp handling
- enable ccw devices in BIOS and enforce checking in QEMU

# gpg: Signature made Wed 28 Sep 2016 12:27:03 BST
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# gpg: Good signature from "Christian Borntraeger (IBM) <borntraeger@de.ibm.com>"
# Primary key fingerprint: F922 9381 A334 08F9 DBAB  FBCA 117B BC80 B5A6 1C7C

* remotes/borntraeger/tags/s390x-20160927:
  s390x/kvm: fix build against qemu_uuid
  s390x/css: {c,h,t,r,x}sch: require enable AND device number valid
  pc-bios/s390-ccw.img: rebuild image
  pc-bios/s390-ccw: enable subchannel for IPL I/O devices
  s390x/kvm: Fix potential deadlock in sigp handling
  s390x/pci: code cleanup
  s390x/pci: assign msix io region for each pci device
  s390x/pci: re-arrange variable declarations

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agoMerge remote-tracking branch 'remotes/yongbok/tags/mips-20160929' into staging
Peter Maydell [Fri, 30 Sep 2016 22:14:39 +0000 (23:14 +0100)]
Merge remote-tracking branch 'remotes/yongbok/tags/mips-20160929' into staging

MIPS patches 2016-09-29

Changes:
* MIPS Maintainer update
* vmstateify rc4030

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* remotes/yongbok/tags/mips-20160929:
  hw/dma: vmstateify rc4030
  MAINTAINERS: update target-mips maintainers

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agoMerge remote-tracking branch 'remotes/jnsnow/tags/ide-pull-request' into staging
Peter Maydell [Thu, 29 Sep 2016 23:42:08 +0000 (00:42 +0100)]
Merge remote-tracking branch 'remotes/jnsnow/tags/ide-pull-request' into staging

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* remotes/jnsnow/tags/ide-pull-request:
  ide: Fix memory leak in ide_register_restart_cb()
  MAINTAINERS: Add some more headers to the IDE section
  ahci: clear aiocb in ncq_cb
  ide: fix DMA register transitions

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agoide: Fix memory leak in ide_register_restart_cb()
Ashijeet Acharya [Tue, 27 Sep 2016 16:53:32 +0000 (22:23 +0530)]
ide: Fix memory leak in ide_register_restart_cb()

Fix a memory leak in ide_register_restart_cb() in hw/ide/core.c and add
idebus_unrealize() in hw/ide/qdev.c to have calls to
qemu_del_vm_change_state_handler() to deal with the dangling change
state handler during hot-unplugging ide devices which might lead to a
crash.

Signed-off-by: Ashijeet Acharya <ashijeetacharya@gmail.com>
Reviewed-by: John Snow <jsnow@redhat.com>
Message-id: 1474995212-10580-1-git-send-email-ashijeetacharya@gmail.com
[Minor whitespace fix --js]
Signed-off-by: John Snow <jsnow@redhat.com>
8 years agoMAINTAINERS: Add some more headers to the IDE section
Thomas Huth [Fri, 23 Sep 2016 16:09:56 +0000 (18:09 +0200)]
MAINTAINERS: Add some more headers to the IDE section

The folder include/hw/ide/ belongs to the IDE section.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: John Snow <jsnow@redhat.com>
Message-id: 1474646996-30421-1-git-send-email-thuth@redhat.com
Signed-off-by: John Snow <jsnow@redhat.com>
8 years agoahci: clear aiocb in ncq_cb
John Snow [Mon, 26 Sep 2016 18:33:37 +0000 (14:33 -0400)]
ahci: clear aiocb in ncq_cb

Similar to existing fixes for IDE (87ac25fd) and ATAPI (7f951b2d), the
AIOCB must be cleared in the callback. Otherwise, we may accidentally
try to reset a dangling pointer in bdrv_aio_cancel() from a port reset.

Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-id: 1474575040-32079-2-git-send-email-jsnow@redhat.com
Signed-off-by: John Snow <jsnow@redhat.com>
8 years agoide: fix DMA register transitions
John Snow [Thu, 29 Sep 2016 18:46:15 +0000 (14:46 -0400)]
ide: fix DMA register transitions

ATA8-APT defines the state transitions for both a host controller and
for the hardware device during the lifecycle of a DMA transfer, in
section 9.7 "DMA command protocol."

One of the interesting tidbits here is that when a device transitions
from DDMA0 ("Prepare state") to DDMA1 ("Data_Transfer State"), it can
choose to set either BSY or DRQ to signal this transition, but not both.

as ide_sector_dma_start is the last point in our preparation process
before we begin the real data transfer process (for either AHCI or BMDMA),
this is the correct transition point for DDMA0 to DDMA1.

I have chosen !BSY && DRQ for QEMU to make the transition from DDMA0 the
most obvious.

Reported-by: Benjamin David Lunt <fys@fysnet.net>
Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Tested-by: Stefan Weil <sw@weilnetz.de>
Message-id: 1470175541-19344-1-git-send-email-jsnow@redhat.com
Signed-off-by: John Snow <jsnow@redhat.com>
8 years agooslib-posix: add a configure switch to debug stack usage
Peter Lieven [Tue, 27 Sep 2016 09:58:45 +0000 (11:58 +0200)]
oslib-posix: add a configure switch to debug stack usage

this adds a knob to track the maximum stack usage of stacks
created by qemu_alloc_stack.

Signed-off-by: Peter Lieven <pl@kamp.de>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
8 years agocoroutine-sigaltstack: use helper for allocating stack memory
Peter Lieven [Tue, 27 Sep 2016 09:58:44 +0000 (11:58 +0200)]
coroutine-sigaltstack: use helper for allocating stack memory

Signed-off-by: Peter Lieven <pl@kamp.de>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
8 years agocoroutine-ucontext: use helper for allocating stack memory
Peter Lieven [Tue, 27 Sep 2016 09:58:43 +0000 (11:58 +0200)]
coroutine-ucontext: use helper for allocating stack memory

Signed-off-by: Peter Lieven <pl@kamp.de>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
8 years agocoroutine: add a macro for the coroutine stack size
Peter Lieven [Tue, 27 Sep 2016 09:58:42 +0000 (11:58 +0200)]
coroutine: add a macro for the coroutine stack size

Signed-off-by: Peter Lieven <pl@kamp.de>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
8 years agocoroutine-sigaltstack: rename coroutine struct appropriately
Peter Lieven [Tue, 27 Sep 2016 09:58:41 +0000 (11:58 +0200)]
coroutine-sigaltstack: rename coroutine struct appropriately

The name of the sigaltstack coroutine struct was misleading.

Signed-off-by: Peter Lieven <pl@kamp.de>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
8 years agooslib-posix: add helpers for stack alloc and free
Peter Lieven [Tue, 27 Sep 2016 09:58:40 +0000 (11:58 +0200)]
oslib-posix: add helpers for stack alloc and free

the allocated stack will be adjusted to the minimum supported stack size
by the OS and rounded up to be a multiple of the system pagesize.
Additionally an architecture dependent guard page is added to the stack
to catch stack overflows.

Signed-off-by: Peter Lieven <pl@kamp.de>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
8 years agoblock: Remove qemu_root_bds_opts
Kevin Wolf [Tue, 20 Sep 2016 18:48:52 +0000 (20:48 +0200)]
block: Remove qemu_root_bds_opts

The remaining options in qemu_root_bds_opts (aio and copy-on-read)
aren't used any more, the QAPI schema doesn't contain them. Therefore
all the code processing qemu_root_bds_opts options is dead and can be
removed.

Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
8 years agoblock: Move 'discard' option to bdrv_open_common()
Kevin Wolf [Mon, 12 Sep 2016 16:03:18 +0000 (18:03 +0200)]
block: Move 'discard' option to bdrv_open_common()

This enables its use for nested child nodes. The compatibility
between the 'discard' and 'detect-zeroes' setting is checked in
bdrv_open_common() now as the former setting isn't available before
calling bdrv_open() any more.

Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
8 years agoblock: Use 'detect-zeroes' option for 'blockdev-change-medium'
Kevin Wolf [Mon, 12 Sep 2016 17:08:31 +0000 (19:08 +0200)]
block: Use 'detect-zeroes' option for 'blockdev-change-medium'

Instead of modifying the new BDS after it has been opened, use the newly
supported 'detect-zeroes' option in bdrv_open_common() so that all
requirements are checked (detect-zeroes=unmap requires discard=unmap).

Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
8 years agoblock: Parse 'detect-zeroes' in bdrv_open_common()
Kevin Wolf [Mon, 12 Sep 2016 19:00:41 +0000 (21:00 +0200)]
block: Parse 'detect-zeroes' in bdrv_open_common()

Amongst others, this means that you can now use the 'detect-zeroes'
option for non-top-level nodes in blockdev-add, like the QAPI schema
promises.

Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
8 years agoblock/qapi: Move 'aio' option to file driver
Kevin Wolf [Thu, 8 Sep 2016 13:09:01 +0000 (15:09 +0200)]
block/qapi: Move 'aio' option to file driver

The option whether or not to use a native AIO interface really isn't a
generic option for all drivers, but only applies to the native file
protocols. This patch moves the option in blockdev-add to the
appropriate places (raw-posix and raw-win32).

We still have to keep the flag BDRV_O_NATIVE_AIO for compatibility
because so far the AIO option was usually specified on the wrong layer
(the top-level format driver, which didn't even look at it) and then
inherited by the protocol driver (where it was actually used). We can't
forbid this use except in new interfaces.

Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
8 years agoblock/qapi: Use separate options type for curl driver
Kevin Wolf [Thu, 8 Sep 2016 11:08:20 +0000 (13:08 +0200)]
block/qapi: Use separate options type for curl driver

We're going to add an option to the file drivers which doesn't apply to
the curl drivers, so give them a separate option type.

Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
8 years agoblock: Drop aio/cache consistency check from qmp_blockdev_add()
Kevin Wolf [Wed, 7 Sep 2016 13:26:42 +0000 (15:26 +0200)]
block: Drop aio/cache consistency check from qmp_blockdev_add()

The TODO comment has been addressed a while ago and this is now checked
in raw-posix, so we don't have to special case this in blockdev-add any
more.

Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
8 years agoblock: Fix error path in qmp_blockdev_change_medium()
Kevin Wolf [Mon, 26 Sep 2016 13:03:00 +0000 (15:03 +0200)]
block: Fix error path in qmp_blockdev_change_medium()

Commit 00949bab incorrectly changed one instance of &err into errp while
touching the line. Change it back.

Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
8 years agoblock-backend: remove blk_flush_all
John Snow [Fri, 23 Sep 2016 01:45:52 +0000 (21:45 -0400)]
block-backend: remove blk_flush_all

We can teach Xen to drain and flush each device as it needs to, instead
of trying to flush ALL devices. This removes the last user of
blk_flush_all.

The function is therefore removed under the premise that any new uses
of blk_flush_all would be the wrong paradigm: either flush the single
device that requires flushing, or use an appropriate flush_all mechanism
from outside of the BlkBackend layer.

Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Acked-by: Fam Zheng <famz@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
8 years agoqemu: use bdrv_flush_all for vm_stop et al
John Snow [Fri, 23 Sep 2016 01:45:51 +0000 (21:45 -0400)]
qemu: use bdrv_flush_all for vm_stop et al

Reimplement bdrv_flush_all for vm_stop. In contrast to blk_flush_all,
bdrv_flush_all does not have device model restrictions. This allows
us to flush and halt unconditionally without error.

This allows us to do things like migrate when we have a device with
an open tray, but has a node that may need to be flushed, or nodes
that aren't currently attached to any device and need to be flushed.

Specifically, this allows us to migrate when we have a CDROM with
an open tray.

Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Acked-by: Fam Zheng <famz@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
8 years agoblock: reintroduce bdrv_flush_all
John Snow [Fri, 23 Sep 2016 01:45:50 +0000 (21:45 -0400)]
block: reintroduce bdrv_flush_all

Commit fe1a9cbc moved the flush_all routine from the bdrv layer to the
block-backend layer. In doing so, however, the semantics of the routine
changed slightly such that flush_all now used blk_flush instead of
bdrv_flush.

blk_flush can fail if the attached device model reports that it is not
"available," (i.e. the tray is open.) This changed the semantics of
flush_all such that it can now fail for e.g. open CDROM drives.

Reintroduce bdrv_flush_all to regain the old semantics without having to
alter the behavior of blk_flush or blk_flush_all, which are already
'doing the right thing.'

Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Acked-by: Fam Zheng <famz@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
8 years agohw/dma: vmstateify rc4030
Dr. David Alan Gilbert [Wed, 24 Aug 2016 10:40:43 +0000 (11:40 +0100)]
hw/dma: vmstateify rc4030

Convert rc4030 to VMState.
Now saving the whole 16 entries rather than 15.

Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Reviewed-by: Hervé Poussineau <hpoussin@reactos.org>
Tested-by: Hervé Poussineau <hpoussin@reactos.org>
[Yongbok Kim: edited commit message]
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
8 years agoMAINTAINERS: update target-mips maintainers
Leon Alrae [Thu, 22 Sep 2016 13:34:14 +0000 (14:34 +0100)]
MAINTAINERS: update target-mips maintainers

Yongbok Kim takes over the target-mips maintenance from me.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Acked-by: Yongbok Kim <yongbok.kim@imgtec.com>
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
8 years agosmbios: fix uuid copy
Marc-André Lureau [Wed, 28 Sep 2016 14:38:10 +0000 (18:38 +0400)]
smbios: fix uuid copy

Since 9c5ce8db, the uuid is wrongly copied, as QemuUUID 'in' argument is
already a pointer.

Fixes ASAN complaining:
hw/smbios/smbios.c:489:5: runtime error: load of address 0x7fffcdb91b00
with insufficient space for an object of type '__int128 unsigned'

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20160928143810.25558-1-marcandre.lureau@redhat.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
[Warp the long error message line in commit message. - Fam]
Signed-off-by: Fam Zheng <famz@redhat.com>
8 years agoxenpv: Fix qemu_uuid compiling error
Fam Zheng [Tue, 27 Sep 2016 09:20:11 +0000 (17:20 +0800)]
xenpv: Fix qemu_uuid compiling error

9c5ce8db2 switched the type of qemu_uuid and this should have followed.
Fix it.

Signed-off-by: Fam Zheng <famz@redhat.com>
Message-Id: <1474968011-29382-1-git-send-email-famz@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Acked-by: Stefano Stabellini <sstabellini@kernel.org>
8 years agoMerge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' into staging
Peter Maydell [Wed, 28 Sep 2016 23:34:20 +0000 (00:34 +0100)]
Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' into staging

# gpg: Signature made Wed 28 Sep 2016 22:30:45 BST
# gpg:                using RSA key 0x9CA4ABB381AB73C8
# gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>"
# gpg:                 aka "Stefan Hajnoczi <stefanha@gmail.com>"
# Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35  775A 9CA4 ABB3 81AB 73C8

* remotes/stefanha/tags/tracing-pull-request:
  trace: Document the execution mode of guest events
  trace: Add event "guest_cpu_reset"
  trace: Add event "guest_cpu_enter"
  trace: Properly initialize dynamic event states in hot-plugged vCPUs
  trace: move hw/virtio/virtio-balloon.c trace points into correct file
  trace: move hw/mem/pc-dimm.c trace points into correct file
  trace: move util/qemu-coroutine*.c trace points into correct file
  trace: move util/buffer.c trace points into correct file

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agoMerge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
Peter Maydell [Wed, 28 Sep 2016 22:02:56 +0000 (23:02 +0100)]
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging

* thread-safe tb_flush (Fred, Alex, Sergey, me, Richard, Emilio,... :-)
* license clarification for compiler.h (Felipe)
* glib cflags improvement (Marc-André)
* checkpatch silencing (Paolo)
* SMRAM migration fix (Paolo)
* Replay improvements (Pavel)
* IOMMU notifier improvements (Peter)
* IOAPIC now defaults to version 0x20 (Peter)

# gpg: Signature made Tue 27 Sep 2016 10:57:40 BST
# gpg:                using RSA key 0xBFFBD25F78C7AE83
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>"
# gpg:                 aka "Paolo Bonzini <pbonzini@redhat.com>"
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4  E2F7 7E15 100C CD36 69B1
#      Subkey fingerprint: F133 3857 4B66 2389 866C  7682 BFFB D25F 78C7 AE83

* remotes/bonzini/tags/for-upstream: (28 commits)
  replay: allow replay stopping and restarting
  replay: vmstate for replay module
  replay: move internal data to the structure
  cpus-common: lock-free fast path for cpu_exec_start/end
  tcg: Make tb_flush() thread safe
  cpus-common: Introduce async_safe_run_on_cpu()
  cpus-common: simplify locking for start_exclusive/end_exclusive
  cpus-common: remove redundant call to exclusive_idle()
  cpus-common: always defer async_run_on_cpu work items
  docs: include formal model for TCG exclusive sections
  cpus-common: move exclusive work infrastructure from linux-user
  cpus-common: fix uninitialized variable use in run_on_cpu
  cpus-common: move CPU work item management to common code
  cpus-common: move CPU list management to common code
  linux-user: Add qemu_cpu_is_self() and qemu_cpu_kick()
  linux-user: Use QemuMutex and QemuCond
  cpus: Rename flush_queued_work()
  cpus: Move common code out of {async_, }run_on_cpu()
  cpus: pass CPUState to run_on_cpu helpers
  build-sys: put glib_cflags in QEMU_CFLAGS
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agoMerge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging
Peter Maydell [Wed, 28 Sep 2016 19:13:05 +0000 (20:13 +0100)]
Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging

# gpg: Signature made Wed 28 Sep 2016 19:15:22 BST
# gpg:                using RSA key 0x9CA4ABB381AB73C8
# gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>"
# gpg:                 aka "Stefan Hajnoczi <stefanha@gmail.com>"
# Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35  775A 9CA4 ABB3 81AB 73C8

* remotes/stefanha/tags/block-pull-request:
  linux-aio: fix re-entrant completion processing
  test-coroutine: test qemu_coroutine_entered()
  coroutine: add qemu_coroutine_entered() function
  libqos: fix qvring_init()
  iothread: check iothread->ctx before aio_context_unref to avoid assertion
  aio-posix: avoid unnecessary aio_epoll_enabled() calls
  block: mirror: fix wrong comment of mirror_start

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agotrace: Document the execution mode of guest events
Lluís Vilanova [Thu, 22 Sep 2016 18:40:21 +0000 (20:40 +0200)]
trace: Document the execution mode of guest events

Explicitly state in which execution mode (user, softmmu, all) are guest
events available for tracing.

Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
Message-id: 147456962135.11114.6146034359114598596.stgit@fimbulvetr.bsc.es
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
8 years agotrace: Add event "guest_cpu_reset"
Lluís Vilanova [Mon, 19 Sep 2016 12:55:18 +0000 (14:55 +0200)]
trace: Add event "guest_cpu_reset"

Signals the reset of the state a virtual (guest) CPU.

Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
Message-id: 147428971851.15111.8799439252178273840.stgit@fimbulvetr.bsc.es
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
8 years agotrace: Add event "guest_cpu_enter"
Lluís Vilanova [Mon, 19 Sep 2016 12:55:13 +0000 (14:55 +0200)]
trace: Add event "guest_cpu_enter"

Signals the hot-plugging of a new virtual (guest) CPU.

Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
Message-id: 147428971313.15111.18023030883528426840.stgit@fimbulvetr.bsc.es
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
8 years agotrace: Properly initialize dynamic event states in hot-plugged vCPUs
Lluís Vilanova [Mon, 19 Sep 2016 12:55:07 +0000 (14:55 +0200)]
trace: Properly initialize dynamic event states in hot-plugged vCPUs

Every time a vCPU is hot-plugged, it will "inherit" its tracing state
from the global state array. That is, if *any* existing vCPU has an
event enabled, new vCPUs will have too.

Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
Message-id: 147428970768.15111.7664565956870423529.stgit@fimbulvetr.bsc.es
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
8 years agotrace: move hw/virtio/virtio-balloon.c trace points into correct file
Daniel P. Berrange [Wed, 14 Sep 2016 17:03:44 +0000 (18:03 +0100)]
trace: move hw/virtio/virtio-balloon.c trace points into correct file

The trace points for hw/virtio/virtio-balloon.c were mistakenly put
in the top level trace-events file, instead of util/trace-events in

  commit 270ab88f7c1112389a02cee0e3e03b20fcc7547e
  Author: Daniel P. Berrange <berrange@redhat.com>
  Date:   Thu Jun 16 09:39:57 2016 +0100

    trace: split out trace events for hw/virtio/ directory

Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-id: 1473872624-23285-5-git-send-email-berrange@redhat.com
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
8 years agotrace: move hw/mem/pc-dimm.c trace points into correct file
Daniel P. Berrange [Wed, 14 Sep 2016 17:03:43 +0000 (18:03 +0100)]
trace: move hw/mem/pc-dimm.c trace points into correct file

The trace points for hw/mem/pc-dimm.c were mistakenly put
in the hw/i386/trace-events file, instead of hw/mem/trace-events
in

  commit 5eb76e480b42206d3640c1aab8a376ba350f70bb
  Author: Daniel P. Berrange <berrange@redhat.com>
  Date:   Thu Jun 16 09:40:10 2016 +0100

    trace: split out trace events for hw/i386/ directory

Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-id: 1473872624-23285-4-git-send-email-berrange@redhat.com
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>